GB2273831A

GB2273831A - Overvoltage protection circuit; electrostatic discharge protection

Info

Publication number: GB2273831A
Application number: GB9226989A
Authority: GB
Inventors: Jo Hamid; Francois Mackre
Original assignee: Motorola Semiconducteurs SA
Current assignee: Freescale Semiconducteurs France SAS
Priority date: 1992-12-24
Filing date: 1992-12-24
Publication date: 1994-06-29
Anticipated expiration: 2012-12-24
Also published as: GB2273831B; GB9226989D0

Abstract

The protection circuit 8 has first and second input terminals 10, 11 connected to the operating power supply voltage of a user device 9 and to ground respectively, and a terminal 12 receiving an input signal voltage of varying magnitude and connected to an output terminal 13 via a node 14. A diode 15 is connected between input terminals 10, 11, a MOSFET 16 has drain and source electrodes 17, 18 coupled to node 14 and terminal 10 respectively, and a bipolar transistor 20 has its emitter 21 and collector 22 coupled to node 14 and terminal 11 respectively with its base 23 coupled to N-well substrate 24 of MOSFET 16. The transistors 16, 20 and the diode 15 provide conduction paths in the event of excess voltage occurring at the signal input terminal 12 and so provide voltage protection at the output terminal 13. The circuit 8 may be constructed from a low number of components on a single integrated circuit, the transistor 20 being formed as a parasitic element of the MOSFET 16, and the diode 15 being formed by the N-well 24 of the MOSFET 16. <IMAGE>

Description

VOLTAGE PROTECTION CIRCUIT FIELD OF THE INVENTION This invention relates to voltage protection circuits, and particularly to circuits for protecting devices from electrostatic discharge.

BACKGROUND OF THE INVENTION A voltage protection circuit may be used to safeguard a connected user device against electrostatic discharges (ESDs) associated with input signals to the device. Such protection circuits exist which can protect against both positive and negative polarity ESDs.

A simple diode arrangement coupled between supply lines and the device input terminals may be used to prevent signals which are higher than the supply voltage (VDD) or lower than the ground reference voltage from reaching the input terminals of the user device. However, in some devices, such as those adhering to the well known RS232 and RS422 specifications, the input signal of the device may, during normal operation, exceed the envelope bounded by the supply voltage and the ground reference voltage (in the case of RS422, the input signal may reach a voltage 10 volts higher or lower than the boundary of the aforementioned envelope).

For such devices, a protection circuit is required which will allow the input signal voltage to exceed the above defined envelope whilst continuing to protect the device from ESDs of a magnitude capable of damaging the device.

From US PATENT No. 4,750,078, there is known a method for providing such protection involving a circuit in which the breakdown regimes of bipolar transistors are utilised to selectively steer away the ESD from the connected device.

However, a problem with this arrangement is that damage can still occur in the device because the threshold voltages of the bipolar transistors (the voltages at which the transistors will configure to conduction modes and hence begin to steer away the ESD) may be significantly higher than the minimum voltage which would damage the device, thus allowing a proportion of the ESD through before the circuit is activated, and so not comprehensively protecting the device.

The present invention seeks to provide a voltage protection circuit in which the above mentioned disadvantages are mitigated.

SUMMARY OF THE INVENTION A voltage protection circuit which provides voltage protection for a user device, includes first and second input terminals provided for receiving first and second reference voltages respectively. A third input terminal is coupled to receive an input signal voltage of varying magnitude. An output terminal provides a connection to the user device. A node is coupled between the third input terminal and the output terminal. A diode is connected between the first input terminal and the second input terminal. A first transistor has a first current electrode coupled to the node and has a second current electrode coupled to the first input terminal. A second transistor has a first current electrode coupled to the node, has a second current electrode coupled to the second input terminal and has a control electrode coupled to the first transistor.The first and second transistors and the diode provide conduction paths in the event of excess voltage occurring at the third input terminal and so provide voltage protection at the output terminal.

The circuit may be constructed from a low number of components on a single integrated circuit, the second transistor being formed as a parasitic element of the first transistor, and the diode being formed by an Nwell connection to the first input terminal.

BRIEF DESCRIPTION OF THE DRAWING An exemplary embodiment of the invention will now be described with reference to the drawing of FIG. 1 which shows a preferred embodiment of a voltage protection circuit in accordance with the invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring to FIG. 1, there is shown a voltage protection circuit 8 for providing protection against damage for a user device 9 connected to the circuit 8. A first input terminal 10 of the circuit 8 is provided for receiving a first reference voltage, typically the operating power supply voltage of the device (VDD). A second input terminal 11 is provided for receiving a second reference voltage, typically a ground reference voltage, such that the potential difference between the terminals 10 and 11 would be the normal operating voltage of the user device 9. A third input terminal 12 is provided for receiving an input signal voltage which may exceed the range enveloped by the voltages of the first and second input terminals 10 and 11. An output terminal 13 is provided for connecting the circuit 8 to the user device 9.A node 14 is coupled between the third input terminal 12 and the output terminal 13. A diode 15 is connected between the first input terminal 10 and the second input terminal 11 for allowing current flow if the potential difference of the second input terminal 11 with respect to the first input terminal 10 is positive. A metal oxide field effect transistor (MOSFET) 16 has a drain electrode 17 coupled to the node 14 and has a source electrode 18 and a gate electrode 19 coupled to the first input terminal 10. A PNP bipolar transistor 20 has an emitter electrode coupled to the node 14, has a collector electrode 22 coupled to the second input terminal 11 and has a base electrode 23 coupled to the MOSFET 16 via an N-well substrate section 24 of the MOSFET 16.

With reference to the operation of the voltage protection circuit 8, if a positive polarity ESD appears between the third input terminal 12 and the first input terminal 10, the MOSFET 16 approaches a threshold voltage VT1 (typically 20 volts) of a conduction regime which produces a conductive path between the first input terminal 10 and the third input terminal 12 via the node 14, such that the excess voltage of the ESD will be diminished as current flows through this path.

If a negative polarity ESD appears between the third input terminal 12 and the first input terminal 10, the MOSFET 16 approaches a threshold voltage VT2 (typically 22 volts) of a breakdown conduction regime again giving rise to a conductive path between the first input terminal 10 and the third input terminal 12 via the node 14, such that the excess voltage of the ESD will be diminished as current flows through this path.

If a negative polarity ESD appears between the third input terminal 12 and the second input terminal 11, the MOSFET 16 approaches the threshold voltage VT2 Of a breakdown regime, which produces a conductive path between the first input terminal 10 and the third input terminal 12 via the node 14.

The diode 15 offers forward bias conduction, and forward collector-emitter breakdown of the Bipolar transistor 20 may also occur such that in combination with the action of the MOSFET, the excess voltage of the ESD will be diminished as current flows through these paths.

If a positive polarity ESD appears between the third input terminal 12 and the second input terminal 11, the MOSFET 16 approaches the threshold voltage VT1 of a conduction regime, which produces a conductive path between the first input terminal 10 and the third input terminal 12 via the node 14.

The diode 15 offers reverse breakdown conduction, and reverse collector-emitter breakdown of the Bipolar transistor 20 may also occur such that with the combination of these two and the action of the MOSFET, the excess voltage of the ESD will be diminished as current flows through these paths.

In this way ESDs of either positive or negative polarity and present between either the third input terminal 12 and the first input terminal 10 or between the third input terminal 12 and the second input terminal 11 are detected and prevented from reaching the user device 9 whilst their voltages are substantially less than the minimum voltage which could damage the user device 9.

In construction, the voltage protection circuit 8 may be formed entirely on a single integrated circuit, using by way of example, a CMOS process, wherein the bipolar transistor 20 is formed as a parasitic element of the MOSFET 16 and the diode 15 is formed by the Nwell of the MOSFET 16, thus enabling the entire voltage protection circuit to be built from a low number of components in a very small area of a semiconductor wafer substrate, or as part of a larger semiconductor device.

It will be appreciated that various alternatives to the above described preferred embodiment will be apparent to a person skilled in the art, such as for example the use of transistors of types other than those described or the fabrication of the circuit by processes other than a CMOS process.

Claims

1. A voltage protection circuit for providing voltage protection for a user device comprising: a first input terminal for receiving a first reference voltage; a second input terminal for receiving a second reference voltage; a third input terminal for receiving an input signal voltage of varying magnitude; an output terminal for connection to the user device; a node coupled between the third input terminal and the output terminal; a diode connected between the first input terminal and the second input terminal; a first transistor having a first current electrode coupled to the node and having a second current electrode coupled to the first input terminal;; a second transistor having a first current electrode coupled to the node, having a second current electrode coupled to the second input terminal and having a control electrode coupled to the first transistor, wherein the first and second transistors and the diode provide conduction paths in the event of excess voltage occurring at the third input terminal and so provide voltage protection at the output terminal.

2. The circuit of claim 1 wherein the first transistor is a field effect transistor.

3. The circuit of claim 2 wherein the first current electrode of the first transistor is a drain electrode and the second current electrode of the first transistor is a source electrode.

4. The circuit of claim 2 or 3 wherein the first transistor includes an N-well substrate to which the control electrode of the second transistor is coupled.

5. The circuit of any of the claims 2 to 4 inclusive wherein the first transistor includes a gate electrode coupled to the first input terminal.

6. The circuit of any preceding claim wherein the second transistor is a bipolar transistor.

7. The circuit of claim 6 wherein first current electrode of the second transistor is an emitter electrode, the second current electrode of the second transistor is a collector electrode and the control electrode of the second transistor is a base electrode.

8. The circuit of any preceding claim wherein the second transistor is formed as a parasitic element of the first transistor.

9. The circuit of any of the claims 4 to 8 inclusive wherein the diode is formed by an Nwell connection to the first input terminal.

10. The circuit of any preceding claim wherein the circuit is formed on a single integrated circuit.

11. A voltage protection circuit substantially as herebefore described and with reference to the accompanying drawing.