GB2269690A - Accessing data from first and second DRAMs - Google Patents

Accessing data from first and second DRAMs Download PDF

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Publication number
GB2269690A
GB2269690A GB9316940A GB9316940A GB2269690A GB 2269690 A GB2269690 A GB 2269690A GB 9316940 A GB9316940 A GB 9316940A GB 9316940 A GB9316940 A GB 9316940A GB 2269690 A GB2269690 A GB 2269690A
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dram
cycle
data
during
drams
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GB9316940D0 (en
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Russell Tilleman
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ANDOR INT Ltd
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ANDOR INT Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A memory control circuit is constructed so that first, second and third addresses are provided to first and second DRAMs during respective cycles 100A, 100B, 100C. A row address strobe signal is provided to both DRAMs during the first cycle, a column address strobe signal CAS-A is provided to the first DRAM during the second cycle, and a column address strobe signal CAS-B is provided to the second DRAM during the third cycle. The first address functions as a row address for both DRAMs, the second address functions as a column address for the first DRAM, and the third address functions as a column address for the second DRAM. Alternatively (Fig 5), a row address strobe signal is provided to the first DRAM during the first cycle, signal CAS-A is provided to the first DRAM during the second cycle, a row address strobe signal is provided to the second DRAM during the second cycle, and signal CAS-B is provided to the second DRAM during the third cycle. In that case the first address functions as a row address for the first DRAM, the second address functions as a column address for the first DRAM and a row address for the second DRAM, and the third address functions as a column address for the second DRAM. In either case, data can be accessed from both DRAMs in only three clock cycles. <IMAGE>

Description

METHOD AND APPARATUS FOR ACCESSING DATA FROM FIRST AND SECOND DRAMS BACKGROUND OF THE INVENTION This invention relates to computer memories and, more particularly, to a method and apparatus for rapidly accessing data from first and second Dynamic Random Access Memories (DRAMs).
Fig. 1 i5 a block diagram of a memory apparatus 10 which may be used for storing data in a computer system.
Apparatus 10 includes a first DRAM 14 and a second DRAM 18 for storing data used by the computer system. A DATA IN/OUT bus 22 is coupled to a DATA IN-A terminal of DRAM -14 and to a DATA IN-B terminal of DRAM 18 for entering data into the respective memories. DATA IN/OUT bus 22 is also coupled to a DATA OUT-A terminal of DRAM 14 and to a DATA OUT-B terminal of DRAM 18 for communicating data read from the memories to other parts of the computer system, Since DATA IN/OUT bus 22 is shared by both memories 14 and 18, data should not be output from DRAM 14 at the same time it is output from DRAM 18. An ADDR-IN bus 26 is coupled to an ADDRESS IN-A terminal of DRAM 14 and to an ADDRESS IN-B terminal of DRAM 18 for addressing the data in DRAMs 14 and 18.
A memory control circuit-30 controls the timing of accesses to DRAMS 14 and 18. Memory control circuit 30 generates a row address strobe (RAS) signal on a RAS-A line 34 to a RAS-A terminal of DRAM 14, a column address strobe (CAS) signal on a CAS-A line 38 to a CAS-A terminal of DRAM 14, a RAS signal on a RAS-B line 42 to an RAS-B terminal of DRAM 18, and a CAS signal on a CAS-B line 46 to a CAS-B terminal of DRAM 18.
Fig. 2. is a timing diagram showing how data is accessed from DRAMS 14 and 18. DRAMS 14 and 18 typically are addressed with 20 bit addresses, but ADDR-IN bus 26 is only a 10 bit bus. Thus, the 20 bit addresses are supplied to DRAMS 14 and 18 in two steps. The first step provides the first half of the address (termed a row address), and the second step provides the second half of the address (termed a column address). Initially, a row address is provided on ADDR-IN bus 26 at the same time that a RAS signal is generated on RAS-A line 34. Thereafter, a column address is provided on ADDR-IN bus 26 at the same time that a CAS signal is generated on CAS A line 38. Output of the data from DRAM 14 is enabled upon the occurrence of the CAS-A signal as shown.Thereafter, a row address is provided on ADDR-SN bus 26 at the same time that a RAS signal is generated on RAS-B line 42 A column address is then provided on ADDR-IN bus 26 at the same time that a CAS signal is generated on CAS-B line 46. Output of the data from DRAM 18 is enabled upon the occurrence of the CAS-B signal as shown.
with the above scheme, #our clock cycles are required to access the data from both DRAMs 14 and 18, and there is an empty cycle disposed between the data output from DRAM 14 and the data output from DRAM 18.
SUMMARY OF THE INVENTION The present invention is directed to a method and apparatus for accessing data from a dual-DRAM memory apparatus in less than four clock cycles and for eliminating the empty cycle disposed between the data output from the first DRAM and the data output from the second DRAM.
In one embodiment of the present invention, a memory control circuit is constructed so that a first address is provided to the memory apparatus during a first cycle, a second address is provided to the memory apparatus during a second cycle, and a third address is provided to the memory apparatus during a third cycle. A row address strobe signal is provided to the first and second DRAMs during the first cycle, a first column address strobe signal is provided to the first DRAM during the second cycle, and a second column address strobe signal is provided to the second DRAM during the third cycle. Thus, the first address functions as a row address for the first and second DRAMs, the second address functions as a column address for the first DRAM, and the third address functions as a column address for the second DRAM.
In another embodiment of the present invention, a first row address strobe signal is provided to the first DRAM during the first cycle, a first column address strobe signal is provided to the first DRAM during the second cycle, a second row address strobe signal is provided to the second DRAM during the second cycle, and a second column address strobe signal is provided to the second DRAM during the third cycle.
Thus, the first address functions as a row address for the first DRAM, the second address functions as a column address for the first DRAM and a row address for the second DRAM, and the third address functions as a column address for the second DRAM.
In both embodiments, the data is available from the first DRAM during the second cycle, and the data is available from the second DRAM during the third cycle. The teachings of the present invention thus provide a total access time to the two memories of only three clock cycles, rather than four, and eliminate the intervening empty cycle found in the prior art between the output of the data from the first DRAM and the output of the data from the second DRAM.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a particular embodiment of a memory apparatus according to the present invention; Fig. 2 is a timing diagram showing one method of accessing data from the memory apparatus shown in Fig. 1; Fig. 3 is a timing diagram showing a particular embodiment of a method according to the present invention for accessing data from the memory apparatus shown in Fig. 1; Fig. 4 is a timing diagram showing two sequential memory accesses using the method shown in Fig. 3; Fig. 5 is a timing diagram showing an alternative embodiment of a method according to the present invention for accessing data from the memory apparatus shown in Fig. 1; and Fig. 6 is a timing diagram showing two sequential memory accesses using the method shown in Fig. 5.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The teachings of the present invention may be applied to the memory apparatus 10 shown in Fig. 1 by constructing memory control circuit 30 to effect the timing scheme shown in Fig. 3. As shown in Fig. 3, a first address which functions as a row address for both DRAMs 14 and 18 is provided on ADDR-IN bus 26 during a clock cycle lOOA simultaneously with the generation of a RAS signal on both RAS-A line 34 and RAS-B line 42. Then, a second address which functions as a column address for DRAM 14 is provided on ADDR IN bus 26 during a clock cycle lOOB simultaneously with the generation of a CAS signal on CAS-A line 38.Finally, a third address which functions as a column address for DRAM 18 is provided on ADDR-IN bus 26 during a clock cycle lOOC simultaneously with the generation of a CAS signal on CAS-B line 46. As a result of the timing scheme shown in Fig. 3, data output from DRAM 14 is enabled during clock cycle ICOB, and data output from DRAM 18 is enabled during clock cycle lOOC. Data is available from both DRAMs 14 and 18 in three cycles rather than four, and the empty cycle found in the prior art between the output of the data from DRAM 14 and the output of the data from DRAM 18 is eliminated.
Fig. 4 is a timing diagram showing two immediate sequential memory accesses using the method shown in Fig. 3.
In general, Once a RAS signal returns to an inactive state (e.g., high in Figs. 3 and 4), it cannot be activated again until the RA5-prszcharge time for the associated DRAM passes.
Assume a RAS-precharge time of two clock cycles. Then, as shown in Fig. 4, RAS-B (and hence RAS-A) cannot be activated until clock cycle lOOF. That is, two full clock cycles after the data was output from DRAM 18 in clock cycle LOOT. Even with this constraint, no performance penalty results over the scheme shown in Fig. 2. Both methods require 8 clock cycles for two sequential accesses.
Fig. 5 is a timing diagram showing an alternative embodiment of a method according to the present invention for accessing data from the memory apparatus 10 shown in Fig. 1.
As shown in Fig. 5, a first address which functions as a row address for DRAM 14 is provided on ADDR-IN bus 26 during a clock cycle 200A simultaneously with the generation of a RAS signal on RAS-A line 34. Then, a second address which functions as a column address for DRAM 14 is provided on ADDR IN bus 26 during a clock cycle 200B simultaneously with the generation of a CAS signal on CAS-A line 28. In this embodiment, a RAS signal is generated on RAS-B line 42 at the same time that the CAS signal is generated on CAS-A line 38.
Thus, the second address provided on ADDR-IN bus 26 during clock cycle 200B also functions as a row address for DRAM 18 during that cycle. Thereafter, a third address which functions as a column address for DRAM 18 is provided on ADDR IN bus 26 during a clock cycle 200C simultaneously with the generation of a CAS signal on CAS-B line 46. Data output from DRAM 14 is enabled during clock cycle 200B, and data output from DRAM 18 is enabled during clock cycle 200C.
As with the embodiment shown in Fig. 3, data is available from both DRAMs 14 and 18 in three cycles rather than four.
However, this embodiment has further advantages. For example, DRAMs draw large, transient amounts of power supply current when a RAS signal is first generated. The embodiment shown in Fig. 3 generates two RAS signals simultaneously, thus producing a rather large current spike. On the other hand, the embodiment shown in Fig. 5 generates the RAS signals separately, thus producing two small current spikes which are easier to filter out.
Furthermore, Fig. 6 is a timing diagram showing two immediate sequential memory accesses using the method shown in Fig. 5. Assume the same two-cycle RAs-precharge time as before. Then, as shown in Fig. 6, RAS-A can be activated during clock cycle 200E, which is one clock cycle after the data was output from DRAM 18, and the two accesses may be completed in 7 clock cycles rather than 8.
while the above is a complete description of preferred embodiments of the present invention, various modifications may be employed. For example, the accesses could be writes as well as reads, and the order of applying the RAS and CAS signals may be reversed to access the data from DRAM 18 before DRAM 14. Consequently, the scope of the invention should not be limited except as described in the claims.

Claims (46)

CLAIMS:
1. An apparatus for accessing data from first and second DRAMS comprising: first addressing means, coupled to the first and second DRAMs, for addressing the first and second DRAMs during a first cycle; second addressing means, coupled to the first DRAM, for addressing the first DRAM during a second cycle, the second cycle occurring after the first cycle; third addressing means, coupled to the second DRAM, for addressing the second DRAM during a third cycle, the third cycle occurring after the second cycle; wherein the first DRAM includes first data output means for outputting data addressed during the first and second cycles; and wherein the second DRAM includes second data output means for outputting data addressed during the first and third cycles.
2. The apparatus according to claim 1 wherein the first data output means outputs the data during the second cycle, and wherein the second data output means outputs the data during the third cycle.
3. The apparatus according to claim 2 wherein the first, second, and third addressing means together comprise a common address bus coupled to an address input terminal of the first DRAM and to an address input terminal of the second DRAM.
4. The apparatus according to claim 3 further comprising a common data bus coupled to a data output terminal of the first DRAM and to a data output terminal of the second DRAM.
5. The apparatus according to claim 4 wherein the common data bus is coupled to a data input terminal of the first DRAM and to a data input terminal of the second DRAM.
6. An apparatus for accessing data from first and second DRAMS comprising: first addressing means, coupled to the first DRAM, for addressing the first DRAM during a first cycle; second addressing means, coupled to the first and second DRAMs, for simultaneously addressing the first and second DRAMs during a second cycle, the second cycle occurring after the first cycle; third addressing means, coupled to the second DRAM, for addressing the second DRAM during a third cycle, the third cycle occurring after the second cycle; wherein the first DRAM includes first data output means for outputting data addressed during the first and second cycles; and wherein the second DRAM includes second data output means for outputting data addressed during the second and third cycles.
7. The apparatus according to claim 6 wherein the first data output means outputs the data during the second cycle, and wherein the second data output means outputs the data during the third cycle.
8. The apparatus according to claim 7 wherein the first, second, and third addressing means together comprise a common address bus coupled to an address input terminal of the first DRAM and to an address input terminal of the second DRAM.
9. The apparatus according to claim 8 further comprising a common data bus coupled to a data output terminal of the first DRAM and to a data output terminal of the second DRAM.
10. The apparatus according to claim 9 wherein the common data bus is coupled to a data input terminal of the first DRAM and to a data input terminal of the second DRAM.
11. An apparatus for accessing data from first and second DRAMS comprising: addressing means, coupled to the first and second DRAMS, for providing a first address to the first and second DRAMS during a first cycle, for providing a second address to the first and second DRAMS during a second cycle, the second cycle occurring after the first cycle, and for providing a third address to the first and second DRAMS during a third cycle, the third cycle occurring after the second cycle; first row address strobe means, coupled to the first DRAM, for providing a first row address strobe signal to the first DRAM during the first cycle; second row address strobe means, coupled to the second DRAM, for providing a second row address strobe signal to the second DRAM during the first cycle;; first column address strobe means, coupled to the first DRAM, for providing a first column address strobe signal to the first DRAM during the second cycle; and second column address strobe means, coupled to the second DRAM, for providing a second column address strobe signal to the second DRAM during the third cycle.
12. The apparatus according to claim 11 wherein the first DRAM includes first data output means for outputting data addressed during the first and second cycles in response to the first column address strobe signal, and wherein the second DRAM includes second data output means for outputting data addressed during the first and third cycles in response to the second column address strobe signal.
13. The apparatus according to claim 12 wherein the first data output means outputs the data from the first DRAM during the second cycle, and wherein the second data output means outputs the data from the second DRAM during the third cycle.
14. The apparatus according to claim 13 wherein the addressing means comprises a common address bus coupled to an address input terminal of the first DRAM and to an address input terminal of the second DRAM.
15. The apparatus according to claim 14 further comprising a common data bus coupled to a data output terminal of the first DRAM and to a data output terminal of the second DRAM.
16. The apparatus according to claim 15 wherein the common data bus is coupled to a data input terminal of the first DRAM and to a data input terminal of the second DRAM.
17. An apparatus for accessing data from first and second DRAMS comprising: addressing means, coupled to the first and second DRAMS, for providing a first address to the first and second DRAMS during a first cycle, for providing a second address to the first and second DRAMS during a second cycle, the second cycle occurring after the first cycle, and for providing a third address to the first and second DRAMS during a third cycle, the third cycle occurring after the second cycle; first row address strobe means, coupled to the first DRAM, for providing a first row address strobe signal to the first DRAM during the first cycle; first column address strobe means, coupled to the first DRAM, for providing a first column address strobe signal to the first DRAM during the second cycle; ; second row address strobe means, coupled to the second DRAM, for providing a second row address strobe signal to the second DRAM during the second cycle; and second column address strobe means, coupled to the second DRAM, for providing a second column address strobe signal to the second DRAM during the third cycle.
18. The apparatus according to claim 17 wherein the first DRAM includes first data output means for outputting data addressed during the first and second cycles in response to the first column address strobe signal, and wherein the second DRAM includes second data output means for outputting data addressed during the second and third cycles in response to the second column address strobe signal.
19. The apparatus according to claim 18 wherein the first data output means outputs the data from the first DRAM during the second cycle, and wherein the second data output means outputs the data from the second DRAM during the third cycle.
20. The apparatus according to claim 19 wherein the addressing means comprises a common address bus coupled to an address input terminal of the first DRAM and to an address input terminal of the second DRAM.
21. The apparatus according to claim 20 further comprising a common data bus coupled to a data output terminal of the first DRAM and to a data output terminal of the second DRAM.
22. The apparatus according to claim 21 wherein the common data bus is coupled to a data input terminal of the first DRAM and to a data input terminal of the second DRAM.
23. A method tor accessing data from first and second DRAMS comprising the steps of: simultaneously addressing the first and second DRAMs during a first cycle; addressing the first DRAM during a second cycle, the second cycle occurring after the first cycle; addressing the second DRAM during a third cycle, the third cycle occurring after the second cycle; outputting data addressed during the first and second cycles from the first DRAM; and outputting data addressed during the first and third cycles from the second DRAM.
24. The method according to claim 23 wherein the step of outputting the data from the first DRAM comprises the step of outputting the data during the second cycle, and wherein the step of outputting the data from the second DRAM comprises the step of outputting the data during the third cycle.
25. The method according to claim 24 further comprising the step of providing the first, second, and third addressas to the first and second DRAMS through a common address bus.
26. The method according to claim 25 further comprising the step of outputting the data from the first and second DRAMS through a common data bus.
27. A method for accessing data from first and second DRAMS comprising the steps of: providing a first address to the first and second DRAMS during a first cycle; providing a second address to the first and second DRAMS during a second cycle; providing a third address to the first and second DRAMS during a third cycle; providing a first row address strobe signal to the first DRAM during the first cycle; providing a second row address strobe signal to the second DRAM during the first cycle; providing a first column address strobe signal to the first DRAM during the second cycle; and providing a second column address strobe signal to the second DRAM during the third cycle.
28. The method according to claim 27 further comprising the steps of; outputting the data addressed during the first and second cycles from the first DRAM in response to the first column address strobe signal; and outputting the data addressed during the second and third cycles from the second DRAM in response to the second column address strobe signal.
29. The method according to claim 28 wherein the step of outputting the data from the first DRAM comprises the step of outputting the data during the second cycle, and wherein the step of outputting the data from the second DRAM comprises the step of outputting the data during the third cycle.
30. The method according to claim 29 further comprising the step of providing the first, second, and third addresses to the first and second DRAMS through a common address bus.
31. The method according to claim 30 further comprising the step of outputting the data from the first and second DRAMS through a common data bus.
32. A method for accessing data from first and second DRAMS comprising the steps of: addressing the first DRAM during a first cycle; simultaneously addressing the first and second DRAMS during a second cycle, the second cycle occurring after the first cycle; addressing the second DRAM during a third cycle, the third cycle occurring after the second cycle; outputting data addressed during the first and second cycles from the first DRAM; and outputting data addressed during the second and third cycles from the second DRAM.
33. The method according to claim 32 wherein the step of outputting the data from the first DRAM comprises the step of outputting the data during the second cycle, and wherein the step of outputting the data from the second DRAM comprises the step of outputting the data during the third cycle.
34. The method according to claim 33 further comprising the step of providing the first, second, and third addresses to the first and second DRAMS through a common address bus.
35. The method according to claim 34 further comprising the step of outputting the data from the first and second DRAMS through a common data bus.
36. A method for accessing data from first and second DRAMS comprising the steps of: providing a first address to the first and second DRAMS during a first cycle; providing a second address to the first and second DRAMS during a second cycle, the second cycle occurring after the first cycle; providing a third address to the first and second DRAMS during a third cycle, the third cycle occurring after the second cycle; providing a first row address strobe signal to the first DRAM during the first cycle; providing a first column address strobe signal to the first DRAM during the second cycle; providing a second row address strobe signal to the second DRAM during the second cycle; and providing a second column address strobe signal to the second DRAM during the third cycle.
37. The method according to claim 36 further comprising the steps of: outputting the data addressed during the first and second cycles from the first DRAM in response to the first column address strobe signal; and outputting the data addressed during the second and third cycles from the second DRAM in response to the second column address strobe signal.
38. The method according to claim 37 wherein the step of outputting the data from the first DRAM comprises the step of outputting the data during the second cycle, and wherein the step of outputting the data from the second DRAM comprises the step of outputting the data during the third cycle.
39. The method according to claim 38 further comprising the step of providing the first, second, and third addresses to the first and second DRAMS through a common address bus.
40. The method according to claim 19 further comprising the step of outputting the data from the first and second DRAMS through a common data bus.
41. A method of reading/writing data from/to first and second memories, in which addressing one memory location of each memory requires an address cycle which is greater than one clock cycle, characterised by simultaneously supplying to said first and second memories a common address signal in at least one clock cycle so that data may be read from/written to two memory locations, one of each memory, in a number of clock cycles which is less than that of two address cycles.
42. Apparatus for reading/writing data from/to first and second memories, in which addressing one memory location of each memory requires an address cycle which is greater than one clock cycle, comprising control means for supplying address signals to said first and second memories so that data may be read from/written to an addressed location via a data bus coupled to the memories, characterised in that the control means is adapted to simultaneously supply to said first and second memories a common address signal in at least one clock cycle so that data may be read from/written to two memory locations, one of each memory, in a number of clock cycles which is less than that of two address cycles.
43. Apparatus substantially as hereinbefore described with reference to Figs. 1, 3 and 4 of the accompanying drawings.
44. Apparatus substantially as hereinbefore described with reference to Figs. 1, 5 and 6 of the accompanying drawings.
45. Method substantially as hereinbefore described with reference to Figs. 3 and 4 of the accompanying drawings.
46. Method substantially as hereinbefore described with reference to Figs. 5 and 6 of the accompanying drawings.
GB9316940A 1992-08-13 1993-08-13 Accessing data from first and second DRAMs Withdrawn GB2269690A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2112256A (en) * 1981-11-18 1983-07-13 Texas Instruments Ltd Memory apparatus
EP0145320A2 (en) * 1983-11-15 1985-06-19 Motorola, Inc. Method for multiplexing a memory data bus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2112256A (en) * 1981-11-18 1983-07-13 Texas Instruments Ltd Memory apparatus
EP0145320A2 (en) * 1983-11-15 1985-06-19 Motorola, Inc. Method for multiplexing a memory data bus

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