GB2269249A - Clock speed control of an integrated circuit. - Google Patents

Abstract

An integrated circuit (2) in which first and second clock signals having different frequencies are input at respective clock signal input connection pins (6,8). A clock detector (14) detects if the second clock signal is present and if so controls a clock signal selector (12) to supply the second clock signal for use in a variable speed portion (16) of the integrated circuit. If the second clock signal is not present, then the clock signal detector controls the clock signal selector to select the first clock signal for use in the variable speed portion of the integrated circuit. <IMAGE>

Description

INTEGRATED CIRCUIT CLOCK SPEED CONTROL This invention relates to the field of integrated circuits. More particularly, this invention relates to the field of the control of clock speed of an integrated circuit.

It is known from United States Patent 4,322,580 and United States Patent 4,322,581 to provide high reliability telephone switching systems with four independent clock signals all having the same frequency. Only one of the clocks signals is used at a time, the remaining clock signals being provided as back-ups. Logic circuitry is used to detect the failure of the active clock signal and scan the remaining clocks to switch to the next available clock signal.

It is desired to provide an integrated circuit that can be clocked at two different frequencies. The advantage of this is that, if the integrated circuit is used in conjunction with appropriate high speed components, then a high clocking frequency can be used to provide increased performance and yet, if it is desired to use less expensive slower components in conjunction with the integrated circuit, the same integrated circuit can still be used if clocked at a lower frequency.

The ability of the integrated circuit to be clocked at different frequencies depending upon the components it is working with removes the need to produce two different specific integrated circuits for the different speeds of operation and provides a relatively straightforward way of upgrading performance.

The different external clock sources that may be used each have an associated input connection through which they are supplied to the integrated circuit. A mechanism must be provided for selecting which input connection should be used as the source of the clock signal for the integrated circuit.

One way in which this might be achieved is to provide a third input connection to supply the integrated circuit with a signal for selecting between the two alternative clock signal input connections.

The need to provide an additional input connection for this selection signal is a disadvantage given the limited space available around an integrated circuit package and the large number of pins required for other purposes.

An alternative approach might be to provide software support for selecting between the two clock signals. Software instructions could be used to generate an internal signal within the integrated circuit to select between the different clock signal input connections as appropriate. However, this software approach has the disadvantage of making the fundamental hardware operation of the integrated circuit dependent upon software support and therefore vulnerable to problems such as software bugs and system crashes.

The invention is concerned with providing a mechanism for selecting between alternative clock signals without incurring the above described disadvantages.

Viewed from one aspect this invention provides an integrated circuit operable under control of an externally applied clock signal, said integrated circuit comprising: a first clock signal input connection for receiving a first clock signal; a second clock signal input connection for receiving a second clock signal; a clock signal detector for detecting if said second clock signal is being applied to said second clock signal input connection; and a clock signal selector responsive to said clock signal detector for selecting said second clock signal to control a variable speed portion of said integrated circuit if said second clock signal is being applied to said second clock signal input connection and for selecting said first clock signal to control said variable speed portion of said integrated circuit if said second clock signal is not being applied to said second clock signal input connection, said second clock signal having a frequency different from said first clock signal at said clock signal selector.

The invention provides an integrated circuit having an internal clock signal detector and an internal clock signal selector for respectively detecting and selecting for use a second clock signal if this is present. Either the lower frequency clock signal could be detected and, if present, used or the higher frequency clock signal could detected and, if present, used. There is no need to provide a third input connection for a clock selection signal thereby releasing space on the integrated circuit package for a pin of another purpose.

In addition, the integrated circuit of the invention utilises a hardware based clock selection mechanism which is not vulnerable to software errors.

It will be appreciated that whilst in general the second clock signal may be lower or higher in frequency than the first clock signal, in preferred embodiments it will be usual that said second clock signal has a higher frequency than said first clock signal.

A convenient way in which the clock signal detector can be made to have the desired type of operation, whereby the first clock signal is used as a default, is that said clock signal detector acts as a retriggerable monostable.

In turn, the action of a retriggerable monostable is advantageously achieved in embodiments in which said clock signal detector is reset into a state indicative of a presence of clock signals applied to said second clock signal input connection if clock signals are detected on said second clock signal input connection and decays into a state indicative of an absence of clock signals applied to said second clock signal input connection if no clock signals are detected on said second clock signal input connection for a predetermined sampling period.

Whilst it will be appreciated that the clock signal input connections could take many forms, in line with current integrated circuit packaging technology, these clock signal input connections will typically be connection pins or connection pads.

In some embodiments of the invention, the variable speed portion of the integrated circuit may comprise the entire integrated circuit, whereby either the first or the second clock signals are used for the entire circuit. However, as described above, this invention is particularly useful for providing an upgrade path when new higher speed components are used in conjunction with the integrated circuit. In this circumstance, it is often the case that only some of the components used with the integrated circuit can be made to operate at a higher frequency than the first clock signal. In order to cope with this, in preferred embodiments of the invention a fixed speed portion of said integrated circuit is permanently operable under control of said first clock signal so as to match fixed speed components that are, in use, connected to said integrated circuit.Examples of such fixed speed components are a disc drive controller or a video display controller.

It will be appreciated that a particularly suitable portion for use as the variable speed portion of the integrated circuit is a central processor unit. The ability to operate a central processor unit at a higher clock frequency has a direct effect upon the processing capacity of the system within which it is used.

In a complementary manner to the fixed speed portion of the integrated circuit, said variable speed portion of said integrated circuit is operable under control of either said first clock signal or said second clock signal so as to match variable speed components that are, in use, connected to said integrated circuit. Examples of such variable speed components are a memory controller or a random access memory.

Viewed from another aspect this invention provides a method of operating an integrated circuit under control of an externally applied clock signal, said integrated circuit having a first clock signal input connection for receiving a first clock signal and a second clock signal input connection for receiving a second clock signal, said method comprising the steps of: detecting if said second clock signal is being applied to said second clock signal input connection; and in response to detection of said second clock signal, selecting said second clock signal to control a variable speed portion of said integrated circuit if said second clock signal is being applied to said second clock signal input connection, or selecting said first clock signal to control said variable speed portion of said integrated circuit if said second clock signal is not being applied to said second clock signal input connection, said second clock signal having a frequency different from said first clock signal as supplied to said variable speed portion.

An embodiment of the invention will now be described, by of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates an integrated circuit embodying an internal clock speed selection mechanism; and Figure 2 illustrates in more detail the clock speed selection mechanism of Figure 1.

Figure 1 shows an integrated circuit 2 having peripheral input and output connection pins 4. A first clock signal (Clock 1) is input through a first clock signal input connection pin 6. A second clock signal (Clock 2) is input through a second clock signal input connection pin 8.

Within the integrated circuit 2, the first clock signal is fed via a clock signal pre-scaling unit 10 to a clock signal selector (multiplexer) 12. The clock signal pre-scaling unit 10 derives a number of lower frequency clock signals from the first clock signal using standard clock division techniques. For example, if the first clock signal was 72MHz, then the pre-scaling unit may divide this to 36MHz and 24MHz clocks, the 36MHz signal being passed to the clock signal selector 12 and the 24MHz signal being used for fixed frequency portions of the integrated circuit 2. The second clock signal (e.g.

48MHz) is fed in parallel to a clock signal detector 14 and the clock signal selector 12. The output from the clock signal selector 12 is fed to a variable speed clock driven circuit 16 (e.g. a central processor unit) that forms a variable speed portion of the integrated circuit 2. The second clock signal as fed to the clock signal selector 12 is of a higher frequency than that fed to the clock signal selector 12 from first clock signal. The selection between the different frequency clock signals at the clock signal selector 12 yields the improved flexibility of the circuit as discussed above.

The action of the clock signal detector 14 is to control the clock signal selector 12 to pass the first clock signal to the clock driven circuit 16 when the second clock signal is not detected. If the clock signal detector 14 detects the second clock signal, then the clock signal detector 14 controls the clock signal selector 12 to pass the second clock signal to the clock driven circuit 16.

Figure 2 illustrates the clock signal detector 14 and the clock signal selector 12 in more detail. The illustration of Figure 2 shows an implementation in discrete bipolar logic. It will be appreciated by those in the art that in practice this logic in implemented as high speed CMOS structures as part of an integrated circuit.

The second clock signal is fed from the second clock signal input connection pin 8 to an asynchronous preset and clear D-type latch 18.

This latch can be of the type usually designated 74F74. A relatively high value resistor 20 (approximately lOOkOhm) is connected to the second clock signal line and acts to hold the second clock signal line to the positive rail voltage +V if no signal is applied to the second clock signal input connection pin 8. If the second clock signal is present, then the action of the resistor 20 is overridden and the preset input PR of the latch 18 will be driven by the second clock signal and will alternate between high and low values.

When the preset input PR goes low, the latch 18 will be preset and the output Q will go high. A sample clock signal is fed to the clock input of the latch 18. In the case that the second clock signal has a frequency of 48MHz, a sample clock signal of a frequency of about 2MHz may be used. If the preset input PR of the latch 18 has not been triggered by the presence of the second clock signal during one sample clock period, then the sample clock rising edge will cause the low value held at the input D of the latch 18 to be transferred to the output Q. The clear input is disabled by connection to the high signal level +V.

The output Q from the latch 18 is fed to the input D of another asynchronous preset and clear D-type latch 22. The signal level supplied to the input D of the latch 22 is transferred to the output Q of the latch 22 under control of the sample clock applied at its clock input. The sample clock serves to define a predetermined time interval over which, if the second clock signal is not present, the clock detector 14 decays to a state indicating this.

Thus, the overall operation of the clock signal detector 14 is that, if the second clock signal is present, then the preset input PR of the latch 18 is set and this is passed by the latch 22 to the clock signal selector 12. If the second clock signal is not present, then the low value at the input D of the latch 18 is passed via the latch 22 to the clock signal selector 12.

The clock signal selector 12 is a multiplexer of the 74F157 type receiving the first clock signal from the first clock signal input connection pin 6 at its input I1 and the second clock signal from the second clock signal input connection pin 8 at its input I2. If the signal at the input S of the clock signal selector 12 is high, then the second clock signal is supplied to the output Y from which it is passed to the clock driven circuit 16 of Figure 1. If the signal at the input S is low then, the first clock signal is fed to the output Y from which it is passed to the clock driven circuit 16 of Figure 1.

Claims (14)

1. An integrated circuit operable under control of an externally applied clock signal, said integrated circuit comprising: a first clock signal input connection for receiving a first clock signal; a second clock signal input connection for receiving a second clock signal; a clock signal detector for detecting if said second clock signal is being applied to said second clock signal input connection; and a clock signal selector responsive to said clock signal detector for selecting said second clock signal to control a variable speed portion of said integrated circuit if said second clock signal is being applied to said second clock signal input connection and for selecting said first clock signal to control said variable speed portion of said integrated circuit if said second clock signal is not being applied to said second clock signal input connection, said second clock signal having a frequency different from said first clock signal at said clock signal selector.

2. An integrated circuit as claimed in claim 1, wherein said second clock signal has a higher frequency than said first clock signal at said clock signal selector.

3. An integrated circuit as claimed in any one of claims 1 and 2, wherein said clock signal detector acts as a retriggerable monostable.

4. An integrated circuit as claimed in claim 3, wherein said clock signal detector is reset into a state indicative of a presence of clock signals applied to said second clock signal input connection if clock signals are detected on said second clock signal input connection and decays into a state indicative of an absence of clock signals applied to said second clock signal input connection if no clock signals are detected on said second clock signal input connection for a predetermined sampling period.

5. An integrated circuit as claimed in any one of the preceding claims, wherein said first clock signal input connection and said second clock signal input connection are connection pins.

6. An integrated circuit as claimed in any one of claims 1 to 4, wherein said first clock signal input connection and said second clock signal input connection are connection pads.

7. An integrated circuit as claimed in any one of the preceding claims, wherein a fixed speed portion of said integrated circuit is permanently operable under control of said first clock signal so as to match fixed speed components that are, in use, connected to said integrated circuit.

8. An integrated circuit as claimed in claim 7, wherein said fixed speed components include at least one of: a disk drive controller or a video display controller.

9. An integrated circuit as claimed in any one of the preceding claims, wherein said variable speed portion of said integrated circuit is a central processor unit.

10. An integrated circuit as claimed in any one of the preceding claims, wherein said variable speed portion of said integrated circuit is operable under control of either said first clock signal or said second clock signal so as to match variable speed components that are, in use, connected to said integrated circuit.

11. An integrated circuit as claimed in claim 9, wherein said variable speed components include at least one of: a memory controller or a random access memory.

12. A method of operating an integrated circuit under control of an externally applied clock signal, said integrated circuit having a first clock signal input connection for receiving a first clock signal and a second clock signal input connection for receiving a second clock signal, said method comprising the steps of: detecting if said second clock signal is being applied to said second clock signal input connection; and in response to detection of said second clock signal, selecting said second clock signal to control a variable speed portion of said integrated circuit if said second clock signal is being applied to said second clock signal input connection, or selecting said first clock signal to control said variable speed portion of said integrated circuit if said second clock signal is not being applied to said second clock signal input connection, said second clock signal having a frequency different from said first clock signal as supplied to said variable speed portion.

13. An integrated circuit substantially as hereinbefore described with reference to the accompanying drawings.

14. A method of operating an integrated circuit substantially as hereinbefore described with reference to the accompanying drawings.