KR100317932B1 - Circuit for selection a clock of phase locked loop - Google Patents

Abstract

The present invention relates to a clock selection circuit of a phase locked loop device for providing an internal clock to the phase locked loop device so that the system can operate stably even when the clock signal input from an external system or network is disconnected.

An aspect of the present invention provides a device for communicating with an external system and a network, the operation state of which is controlled according to a clock selection signal and outputs a predetermined logic value according to whether an external clock supplied from an external system and a network is supplied. A clock detector; An AND product for performing an AND operation on the logic value output from the clock sensing unit and the logic value of the clock selection signal output from the control means for controlling the system; An inverter for inverting the logic value output from the AND product; A first buffer controlling an output state of an internal clock supplied from a system according to a logic state of the AND product; A second buffer for controlling the output state of the external clock in accordance with the logic state of the inverted logic value inverted by the inverter; It comprises a phase-locked loop circuit for outputting a synchronous clock of the system itself synchronized with this clock from either an internal clock or an external clock output from the first buffer and the second buffer.

The present invention has the advantage of preventing the malfunction of the system because it can quickly cope with hardware even if the program is not executed for disconnection of the external clock.

Description

CIRCUIT FOR SELECTION A CLOCK OF PHASE LOCKED LOOP}

The present invention relates to a clock selection circuit of a phase locked loop device (PLL). More particularly, the present invention relates to an internal clock so that the system can operate stably even when a clock signal input from an external system or network is disconnected. A clock selection circuit of a phase synchronous loop device for providing a phase synchronous loop device.

In order to communicate with a network or an external system such as a communication device or a communication system, the clock signal must be synchronized between each communication device or the communication system. That is, a phase-locked loop device is generally configured inside a device in order to synchronize synchronization between an external clock provided for communication in an external system or a network and an internal clock for communication of its own system.

Referring to Fig. 1, a clock selection circuit of a conventional phase locked loop device will be described.

The conventional clock selection circuit includes an inverter 101 for inverting the clock selection signal, a first buffer 102 for controlling the output state of the internal clock according to the logic state of the clock selection signal, and an inverted by the inverter 101. From the second buffer 103 for controlling the output state of the external clock in accordance with the logic state of the inverted clock selection signal, and either the internal clock or the external clock output from the first and second buffers (102, 103) The phase synchronization loop circuit 104 outputs a synchronization clock of the system itself synchronized with this clock.

That is, in the conventional clock selection circuit, when the logic value of the clock selection signal is '0', the first buffer 102 is low-active, and the internal clock is supplied to the phase synchronization loop circuit 104 to synchronize the internal clock. The clock is output. At this time, the second buffer 103 is turned off by receiving an inverted clock selection signal having a logic value of '1' so that the external clock is not supplied to the phase-locked loop circuit 104.

If the logic value of the clock selection signal is '1', the first buffer 102 is turned off so that the internal clock is not supplied to the phase locked loop circuit 104. At this time, the second buffer 103 is low-active by receiving an inverted clock selection signal having a logic value of '0' and an external clock is supplied to the phase-locked loop circuit 104 to output a synchronous clock synchronized with the external clock. .

However, according to the clock selection circuit of the conventional phase-locked loop device, the following problem (s) occur.

That is, if the external clock is cut off because the clock selection circuit operates under the control of the program, the system malfunctions because there is no clock input to the phase-locked loop circuit until the program is executed.

In order to prevent such a malfunction, the cost of the product increases when a sophisticated phase locked loop circuit is constructed.

In addition, since the clock is selected by the program, a high priority task must be assigned, which makes the program complicated.

Accordingly, an object of the present invention is to solve such a problem (s), and an object of the present invention is to select an internal clock by a simple hardware configuration even before a program is executed in a state in which an external clock is disconnected. The present invention provides a clock selection circuit of a phase-locked loop device to prevent a malfunction of a system caused by the system.

1 is a clock selection circuit diagram of a conventional phase-locked loop device,

2 is a clock select circuit diagram of a phase locked loop device according to the present invention;

FIG. 3 is a diagram illustrating an example in which a clock sensing unit is configured as a multivibrator in the configuration of FIG. 2.

<Description of the code | symbol about the principal part of drawing>

201: clock detector 201a: multivibrator

202: logical multiplication device 203: inverter

204 and 205: buffer 206: phase locked loop circuit

A feature of the present invention for achieving such object (s) is, in an apparatus for communicating with an external system and a network: supplying an external clock supplied from an external system and network, the operation state being controlled according to a clock selection signal A clock detector for outputting a predetermined logic value depending on whether or not; An AND product for performing an AND operation on the logic value output from the clock sensing unit and the logic value of the clock selection signal output from the control means for controlling the system; An inverter for inverting the logic value output from the AND product; A first buffer controlling an output state of an internal clock supplied from a system according to a logic state of the AND product; A second buffer for controlling the output state of the external clock in accordance with the logic state of the inverted logic value inverted by the inverter; It comprises a phase-locked loop circuit for outputting a synchronous clock of the system itself synchronized with this clock from either an internal clock or an external clock output from the first buffer and the second buffer.

Here, the clock sensing unit may include a first input terminal for detecting a falling edge connected to ground, a second input terminal for connecting an external clock to detect the rising edge of the external clock, and an enable terminal for the clock selection signal. Connected to the input terminal, the output terminal is connected to the input terminal of the logical multiplication device, and the resistor terminal and the capacitor terminal have a resistor and a capacitor used to control the holding period of the output value derived by one rising edge of an external clock supplied to the input terminal. It can also be comprised by the multivibrator connected, respectively.

In this case, the multivibrator may output a logic value of logic '1' through the output terminal when the clock selection signal is logic '1' and an external clock is input.

Further, the first buffer and the second buffer are preferably low-active when the clock select signal is a logic '0' to supply the clock of either the external clock or the internal clock to the phase locked loop circuit.

Hereinafter, exemplary embodiment (s) of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the elements of each drawing, it should be noted that the same elements are denoted by the same reference numerals as much as possible even if they are displayed on different drawings. In addition, in the following description there are shown a number of specific details, such as components of the specific circuit, which are provided only to help a more general understanding of the present invention that the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 illustrates a clock selection circuit diagram of the phase-locked loop device according to the present invention, and FIG. 3 is a diagram illustrating an example in which the clock sensing unit is configured as a multivibrator.

First, referring to FIG. 2, the operation state is controlled according to the clock selection signal, and the clock detector 201 and the logic output from the clock detector 201 output a predetermined logic value according to whether the external clock is supplied. Logic element 202 for performing an AND operation on the value and a logic value of the clock selection signal, an inverter 203 for inverting the logic value output from the AND product 202, and a logical state of the AND product 202. A first buffer 204 for controlling the output state of the internal clock, a second buffer 205 for controlling the output state of the external clock according to the logic state of the inverted logic value inverted by the inverter 203, The phase synchronization loop circuit 206 outputs a synchronization clock of the system itself synchronized with this clock from either one of an internal clock or an external clock output from the first and second buffers 204 and 205.

Meanwhile, the clock detector 201 of FIG. 2 may be configured as a multi vibrator 201a. That is, as shown in FIG. 3, the first input terminal A of the multivibrator 201a is connected to ground, and the second input terminal B is connected so that an external clock is input. In addition, the enable terminal CD of the multivibrator 201a is connected so that a clock selection signal is input, and the output terminal Q is connected to the input terminal of the logical multiplication element 202. The resistor R and the capacitor C are connected to the resistor terminal Rx and the capacitor terminal Cx of the multivibrator 201a, respectively.

Referring to Figure 3 with respect to the operation of the present invention having such a configuration as follows.

Among the input terminals of the multivibrator 201a, the second input terminal B, that is, the positive edge input terminal, is connected to receive an external clock, and the first input terminal A, that is, the negative edge input terminal, is grounded. Since it is connected to the multivibrator 201a, the multivibrator 201a recognizes the normal input state only at the rising edge of the external clock. In addition, the resistor R and the capacitor C connected to the multivibrator 201a are used to control the sustain period of the output value Q derived by one rising edge of the external clock supplied to the input terminal. In addition, the clock selection signal input to the enable terminal CD of the multivibrator 201a is an input for controlling the operation of the multivibrator 201a. The logic value of the clock selection signal input to the multivibrator 201a is' At 0 ', the multivibrator 201a does not operate.

On the basis of such a state, when the logic value of the clock selection signal is '0', the logic value output from the logical product element 202 is '0'. Thus, the first buffer 204 is low-active so that the internal clock is supplied to the phase-locked loop circuit 206 to output a synchronous clock synchronized with the internal clock. At this time, the multivibrator 201a that receives the clock selection signal having the logic '0' does not operate. In addition, the second buffer 205 is supplied with an inverted logic value having a logic value of '1' and is turned off, so that the external clock is not supplied to the phase locked loop circuit 206.

If the logic value of the clock selection signal is '1' and the external clock is normally supplied, the multivibrator 201a that receives the clock selection signal having the logic status '1' operates according to whether the external clock is applied. Is controlled to recognize the rising edge of the external clock and output the corresponding logic value. That is, since it is assumed that the external clock is normally supplied, the output of the multivibrator 201a becomes a logic '1'.

Accordingly, since the clock selection signal of logic '1' and the output of the multivibrator 201a of logic '1' are simultaneously applied to the logical AND element 202, the output of the logical AND element 202 becomes logical '1'. Accordingly, the first buffer 204 is turned off so that the internal clock is not supplied to the phase locked loop circuit 206.

On the contrary, the second buffer 205 receives the inverted clock selection signal having a logic value of '0' and is low-active so that an external clock is supplied to the phase-locked loop circuit 206 to output a synchronous clock synchronized with the external clock. do.

On the other hand, when the logic value of the clock selection signal is '1' and the external clock is not normally supplied and is disconnected, the multivibrator 201a receiving the clock selection signal having the logic state '1' is applied depending on whether the external clock is applied. The operating state is controlled to recognize the rising edge of the external clock and output the corresponding logic value. That is, since it is assumed that the external clock is not normally supplied, the output of the multivibrator 201a becomes a logic '0'.

Accordingly, since the clock selection signal of logic '1' and the output of the multivibrator 201a of logic '0' are simultaneously applied to the logical multiplication element 202, the output of the logical multiplication element 202 becomes logic '0'. Accordingly, the second buffer 205 is supplied with an inverted logic value having a logic value of '1' and turned off so that the external clock is not supplied to the phase locked loop circuit 206.

In contrast, the first buffer 204 receives a clock selection signal having a logic value of '1' and is low-active so that an internal clock is supplied to the phase-locked loop circuit 206 to output a synchronous clock synchronized with an external clock. .

Therefore, even when the external clock is disconnected, the system can be stably operated by switching the internal clock to be supplied in hardware.

As described above, although the specific embodiment (s) have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. In particular, in the present invention, the clock detector is limited to the multivibrator, but may be replaced with another configuration capable of detecting whether the clock is input. Therefore, the scope of the present invention should not be limited to the described embodiment (s) but should be defined by the claims below and equivalents thereof.

As a result, according to the clock selection circuit of the phase locked loop device according to the present invention, the following advantage (s) occurs.

That is, even if a program is not executed for disconnection of an external clock, hardware can be quickly dealt with, thereby preventing malfunction of the system.

In addition, since the hardware switching is performed instead of a program control that allocates a high interrupt or requires a short real-time clock for fast response speed, the system can operate stably even at a low response speed, thereby reducing the load on the program. .

In addition, since the clock can be selected quickly, high reliability can be obtained even with low-cost components in the phase synchronization loop circuit design process.

Claims (4)

In a device that communicates with external systems and networks: A clock sensing unit controlling an operation state according to a clock selection signal and outputting a predetermined logic value according to whether an external clock supplied from the external system and the network is supplied; An AND product for performing an AND operation on the logic value output from the clock detection unit and the logic value of the clock selection signal output from a control means for controlling the system; An inverter for inverting the logic value output from the logical product; A first buffer controlling an output state of an internal clock supplied from a system according to a logic state of the logical product; A second buffer controlling an output state of the external clock according to a logic state of the inversion logic value inverted by the inverter; And And a phase synchronous loop circuit for outputting a synchronous clock of the system itself synchronized with the clock from any one of the internal clock and the external clock output from the first buffer and the second buffer. Clock selection circuit. The method of claim 1, wherein the clock detection unit, A first input terminal for detecting a falling edge is connected to ground, a second input terminal is connected for input of the external clock to detect a rising edge of the external clock, and an enable terminal is connected for input of the clock select signal. An output terminal is connected to an input terminal of the logical multiplication device, and a resistor terminal and a capacitor terminal include a resistor and a capacitor used to control a sustain period of an output value derived by one rising edge of the external clock supplied to the input terminal. A clock selection circuit of a phase locked loop device, characterized in that each is a multivibrator connected. The method of claim 2, wherein the multi-vibrator, And a logic value of logic '1' through the output terminal when the clock selection signal is logic '1' and the external clock is input. The method of claim 1, wherein the first buffer and the second buffer, And the clock select signal is low-active when the clock select signal is logic '0' to supply either one of the external clock and the internal clock to the phase-locked loop circuit.