GB2267615A

GB2267615A - Transmission gate with reduced charge injection

Info

Publication number: GB2267615A
Application number: GB9310296A
Authority: GB
Inventors: Yutaka Ikeda
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1992-06-03
Filing date: 1993-05-19
Publication date: 1993-12-08
Also published as: KR940001164A; GB9310296D0; JPH05335919A; DE4317922A1; KR960003527B1

Abstract

A transmission gate includes NMOS transistors 1, 2 and 3 in series between nodes A and B, and PMOS transistors 4, 5 and 6 in series between nodes A and B. NMOS transistors 1 and 3, and PMOS transistors 4 and 6 are always on, while transistors 2 and 5 are both turned on/off in response to signals phi and / phi . The capacitance between nodes A and B and the gate electrodes of transistors 2 and 5 is reduced. The circuit may be used to equalise potentials on bit lines in dynamic RAMs. <IMAGE>

Description

22676 15)

TITLE OF THE INVENTION

Semiconductor Integrated Circuit Device including Equalize Circuit BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to semiconductor integrated circuit devices, and particularly to the improvement of an equalize circuit equalizing potentials of two nodes.

Description of the Background Art

A semiconductor integrated circuit device, such as a microcomputer or a semiconductor memory device, comprises a multiplicity of equalize circuits. An equalize circuit is provided between a pair of signal lines which requires is a reference level in a semiconductor integrated circuit device, to equalize the potentials of the pair of signal lines to make them a logical threshold value.

Fig. 10 is a schematic diagram showing a conventional example of an equalize circuit. The equalize circuit shown in Fig. 10 includes an N channel type MOS transistor 2 (hereinafter referred to as an NMOS transistor) and a P channel type MOS transistor 5 (hereinafter referred to as a PMOS transistor).

NMOS transistor 2 has its gate electrode connected to receive an equalize activation signal (b, its drain electrode connected to a node A, and its source electrode connected to a node B. PMOS transistor 5 has its gate electrode connected to receive an equalize activation signal 1(5, its drain electrode connected tonode A, and its source electrode connected to node B. S1 and S2 are a pair of signal lines.

Fig. 11 shows waveform diagrams of signals appearing at respective nodes in the equalize circuit shown in Fig. 10. Fig. 11(a) shows waveforms of the equalize activation signals ( and /4), and (b) shows waveforms of signals appearing at nodes A and B. Referring to Figs. 10 and 11, the operation of the equalize circuit shown in Fig. 10 will be described.

First, in equalizing nodes A and B, the equalize activation signal 4) is brought into a high level, and the equalize activation signal /4) is brought into a low level. Correspondingly, NMOS transistor 2 and PMOS transistor 5 are turned on. Nodes A and B are thus connected, and the potentials of nodes A and B become 1/2 of a power supply voltage Vcc.

Next, in applying as data signals the power supply voltage Vcc to signal line S1, and a ground potential to signal line S2, the equalize activation signal 4) is brought into a low level and the equalize activation signal 1(b is brought into a high level. Correspondingly, NMOS transistor 2 and PMOS transistor 5 are turned off.

Nodes A and B are thus separated, and the potentials of nodes A and B attain the levels of the applied signals to signal line S1 and S2, respectively.

When the equalize activation signal d? changes from a low level to a high level, however, the potentials of nodes A and B are raised for an instant, causing the delay in attaining the levels of the signals.

This will hereinafter be described with reference to Figs. 12 to 15.

Fig. 12 is a cross sectional view showing the structure of PMOS transistor 5 shown in Fig. 10. Fig. 13 is a schematic diagram of an equivalent circuit concerning a capacitance of the MOS transistor shown in Fig. 10.

Fig. 14 is a cross sectional view showing a change of the capacitance of PMOS transistor 5. Fig. 15 is a graph showing the relation between the capacitances between the gate-source and between the gate-drain of the MOS transistor, and the equalize activation signal ( (gate electrode).

Referring to Fig. 12, PMOS transistor 5 includes an N type semiconductor substrate 20, a P type source region 21, a P type drain region 22, a channel region 23, and a gate electrode 24 formed on channel region 23 with an insulating layer, not shown, interposed therebetween.

Between gate electrode 24 and drain region 21 is a parasitic capacitance CDP. Between gate electrode 24 and source region 22 is a parasitic capacitance Csp. These capacitances exist similarly in NMOS transistor 2.

Considering these capacitances, the equalize circuit of Fig. 10 can be shown in the equivalent circuit of Fig. 13.

The change of the capacitance CDP and Csp will be described with reference to Fig. 14.

When the equalize activation signal /4) attains a low level, gate electrode 24 is negatively charged, so that channel region 23 has electrons repelled to be positively charged. Channel region 23 is thus made deeper, resulting in increase of positive charges stored in channel region 23. Consequently, the capacitances CDP and Csp increase as shown in Fig. 15.

As a result, when the equalize activation signal changes from a low level to a high level, the potentials of nodes A and B are raised for an instant, as shown in Fig. 11, under the effect of the capacitance Csp between the gate-source of PMOS transistor 5 and the capacitance CDP between the gate-drain of PMOS transistor 5. This causes the potentials of nodes A and B which has been equalized to be delayed in attaining the applied potentials to signal lines S1 and S2, after the equalize circuit is rendered inactive.

SUMMARY OF THE INVENTION one object of the present invention is to reduce time required for the potentials of nodes having been equalized to attain applied potentials on a equalize circuit being rendered inactive.

In one aspect of the present invention, a semiconductor integrated circuit device includes an equalize circuit equalizing the potentials of first and second signal lines for providing a logical signal. The equalize circuit includes at least first and second switching circuits, a first signal supply node and a second signal supply node. Each of the first and second switching circuits has a control terminal and first and second conductive terminals, and is connected in series between the first and second signal lines. The first signal supply nodeapplies an equalize activation signal to the control terminal of the first switching circuit.

The second signal supply node applies a voltage signal of a predetermined potential to the control terminal of the second switching circuit to produce a capacitance of a predetermined value between the control terminal and the first and second conductive terminals, of the second switching circuit.

In operation, the second switching circuit is turned on in response to a voltage signal of a predetermined potential to produce a capacitance of a predetermined value between the control terminal and the first and second conductive terminals, so that a capacitance can be connected in series between the control terminal of the first switching circuit and the first and second signal lines, resulting in reduction of the capacitance between the first and second signal lines and the control terminal of the first switching circuit. Accordingly, charges stored in the first switching circuit are decreased, preventing the potential of the first and second signal lines from being raised at the moment the first switching circuit is turned off. As a result, the first and second signal lines can attain the level of the applied logical signal with less time after the first switching circuit is turned off.

In another aspect of the present invention, an equalize circuit includes a first node provided on a first signal line, a second node provided on a second signal line, first and second switching elements, and first to fourth capacitance reducing elements. The first and second switching elements, each having a control terminal and first and second conductive terminals, are turned on in response to an applied equalize activation signal. The first capacitance reducing element is connected between the first node and the first conductive terminal of the switching element to reduce a capacitance between the first node and the control terminal of the first switching element. The second capacitance reducing element is connected between the first node and the first conductive terminal of the second switching element to reduce a capacitance between the first node and the control terminal of the second switching element. The third capacitance reducing element is connected between the second node and the second conductive terminal of the first switching element to reduce a capacitance between the second node and the control terminal of the first switching element. The fourth capacitance reducing element is connected between the second node and the second conductive terminal of the second switching element to reduce a capacitance between the second node and the control terminal of the second switching element.

In operation, the first capacitance reducing element and the second capacitance reducing element are provided between the first node and the first conductive terminals of the first and second switching elements, respectively, and the third and fourth capacitance reducing elements are provided between the second node and the second conductive terminals of the first and second switching elements, respectively. Therefore, the capacitance between the control terminals of the first and second switching elements and the first node, and the capacitance between the control terminals of the first and second switching elements and the second node can be reduced. Accordingly, charges stored in each of the first and second switching elements are decreased, avoiding raise of the potentials of the first and second nodes at the moment the first and second switching elements are turn off. As a result, the potentials of the first and second node can attain the level of the applied signal with less time after the first and second switching elements are turned off.

In still another aspect of the present invention, a semiconductor integrated circuit device includes first and second nodes, first and second switching elements, a first capacitance reducing element and a second capacitance is reducing element. The first capacitance reducing element is connected either between the first node and the first conductive terminal of the first switching element, or between the second node and the second conductive terminal of the first switching element, to reduce a capacitance between the first or second node and the control terminal of the first switching element. The second capacitance reducing element is connected either between the first node and the first conductive terminal of the second switching element, or between the second node and the second conductive terminal of the second switching element, to reduce a capacitance between the first or second node and the control terminal of the second switching element.

In operation, the first capacitance reducing element reduces the capacitance between the first or second node and the control terminal of the first switching element, and the second capacitance reducing elements reduces the capacitance between the first or the second node and the control terminal of the second switching element.

Consequently, generation of noise can be prevented at the moment the switching element is turned off.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic diagram of a circuit showing one embodiment of the present invention.

Fig. 2 is a cross sectional view showing the structure of the PMOS transistor of Fig. 1.

Fig. 3 is an equivalent circuit of the circuit shown in Fig. 1 concerning the capacitance.

Fig. 4 shows waveform diagrams of signals appearing at respective nodes in the equalize circuit shown in Fig. 1.

Fig. 5 is a schematic diagram of a circuit showing a second embodiment of the present invention.

Fig. 6 is an equivalent circuit of the equalize circuit of Fig. 5 concerning the capacitance.

Fig. 7 is a schematic diagram of a circuit showing a third embodiment of the present invention.

Fig. 8 is a schematic diagram of a circuit showing a fourth embodiment of the present invention.

Fig. 9 is a block diagram of a semiconductor memory device showing a fifth embodiment of the present invention.

Fig. 10 is a schematic diagram of a conventional equalize circuit.

Fig. 11 shows waveform diagrams of signals appearing at respective nodes in the equalize circuit shown in Fig.

10.

Fig. 12 is a cross sectional view of the PMOS transistor shown in Fig. 10.

Fig. 13 is an equivalent circuit of the equalize circuit shown in Fig. 19 concerning the capacitance.

Fig. 14 is a cross sectional view showing change of the capacitance of the PMOS transistor shown in Fig. 10.

Fig. 15 is a graph showing the relation between the gate electrode and the capacitances between gate-source and between gate-drain of the MOS transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Fig. 1 is a schematic diagram of a circuit showing one embodiment of the present invention. An equalize circuit shown in Fig. 1 is different from the one shown in Fig. 10, in that an NMOS transistor 1 is provided between a node A and the drain electrode of an NMOS transistor 2, that an NMOS transistor 3 is provided between a node B and the source electrode of NMOS transistor 2, that a PMOS transistor 4 is provided between node A and the drain electrode of a PMOS transistor 5, and that a PMOS transistor 6 is provided between node B and the source electrode of PMOS transistor 5.

NMOS transistor 1 has its gate electrode connected to a power supply voltage Vcc, its drain electrode connected is to node A, and its source electrode connected to the drain electrode of NMOS transistor 2. NMOS transistor 3 has its gate electrode connected to power supply voltage Vcc, its source electrode connected to the source electrode of NMOS transistor 2, and its drain electrode connected to node B. PMOS transistor 4 has its gate electrode connected to a ground terminal GND, its drain electrode connected to node A, and its source electrode connected to the drain electrode of PMOS transistor 5. PMOS transistor 6 has its gate electrode connected to ground potential GND, its source electrode connected to the source electrode of PMOS transistor 5, and its drain electrode connected to node B. NMOS transistors 1 and 3 and PMOS transistors 4 and 6 are always in the on-state. The equalize circuit, therefore, is activated when a equalize activation signal 4) is at a high level, and /4) is at a low level, as in the equalize circuit shown in Fig. 10.

Fig. 2 is a cross sectional view of PMOS transistors 4, 5 and 6 shown in Fig. 1. Referring to Fig. 2, PMOS transistor 4 includes a P type drain region 25, a gate electrode 26, a P type source region 21, and a channel region 27. Source region 21 is shared with PMOS transistor 5 as its drain region 21. PMOS transistor 6 includes a P type drain region 28, a P type source region 22, a gate electrode 29 and a channel region 30. Source region 22 is shared with PMOS transistor 5 as its source region 22. PMOS transistor 5 is the same as the one shown in Fig. 11.

PMOS transistors 4 and 6 have'gate electrodes 26 and 29 connected to ground terminal GND, and positive charges stored in channel regions 27 and 30, respectively.

Therefore, a capacitance CD1 is present between gate electrode 26 and drain region 25 of PMOS transistor 4, and a capacitance Cs, is present between gate electrode 26 and source region 21. A capacitance Cs7 is present between gate electrode 29 and source region 22 of PMOS transistor -12 6, and a capacitance CD2 'S present between gate electrode 29 and drain region 28. Since PMOS transistors 4 and 6 are always in the on-state, the capacitances CD1 1 CS1 1 CD2 and CS2 are in the maximum state.

Fig. 3 is an equivalent circuit of the equalize circuit shown in Fig. 1 concerning the above described capacitances. As described with reference to Fig. 2, parasitic capacitances are present in PMOS transistors 4, and 6, as well as in NMOS transistors 1, 2 and 3. NMOS transistor 1 has a capacitance CD3 between its gate and drain, and a capacitance CS3 between its gate-source. NMOS transistor 3 has a capacitance CS4 between its gate-source.

and a capacitance CD4 between its gate-drain. RON shown in Fig. 3 is a resistance value of each MOS transistor in the ON state.

As can be seen from the equivalent circuit of Fig. 3, the capacitance between node A and the gate electrode of NMOS transistor 2 and the capacitance between node B and the gate electrode of NMOS transistor 2 are smaller than CDN and CsN, respectively. It also can be seen that the capacitance between node A and the gate electrode of PMOS transistor 5 and the capacitance between node B and the gate electrode of PMOS transistor 5 are smaller than CDP and Csp, respectively. That is, the capacitance is small compared to that in Fig. 3. Therefore, positive charges stored in PMOS transistor 5 tend to flow to ground terminal GND, and negative charges stored in NMOS transistor 2 tend to flow to power supply potential Vcc. The amount of stored charges becomes smaller, whereby the potentials of nodes A and B can be prevented from being raised at the moment NMOS transistor 2 and PMOS transistor 5 are turned off. The potentials of nodes A and B can attain the level of the signal with less time after MOS transistors 2 and 5 are turned off.

Fig. 4 shows a waveform diagrams of signals appearing at respective nodes in the equalize circuit shown in Fig. 1. The waveform diagrams shown in Fig. 4 are different from those shown in Fig. 11, in that the capacitances CDNI CSN, CDp and Csp do not generate noise immediately after MOS transistors 2 and 5 are turned off. It is because the capacitance between node A and the gate electrode and the capacitance between node B and the gate electrode are reduced, as described above.

Fig. 5 is a schematic diagram of a circuit showing a second embodiment of the present invention. The equalize circuit shown in Fig. 5 is different from the one shown in Fig. 1 in that NMOS transistor 3 and PMOS transistor 6 are removed.

Fig. 6 is an equivalent circuit of Fig. 5 concerning the capacitance. Referring to Fig. 6, a filter comprised of an on-resistance RON and the capacitances CD3 and CS3 'S formed between node A and the capacitance CM. A filtering circuit comprised of an on-resistance RON, and the capacitances CD, and Cs, is formed between node A and the capacitance CDP. Accordingly, the capacitances between node A and the gate electrodes of MOS transistors 2 and 5 are reduced. As a result, stored charges tend to flow at the moment MOS transistors 2 and 5 are turned off, preventing the potentials of nodes A and B from being raised.

Fig. 7 is a schematic diagram of a circuit showing a third embodiment of the present invention. The equalize circuit shown in Fig. 7 is different from the one shown in Fig. 5 in that MOS transistors 1 and 4 on the side of node A of the equalize circuit shown in Fig. 1 are removed.

In this embodiment, the capacitance between node B and the gate electrode of NMOS transistor 2 and the capacitance between node B and the gate electrode of PMOS transistor 5 can be reduced. Therefore, as in the case of Fig. 5, the potentials of nodes A and B can be prevented from being raised at the moment MOS transistors 2 and 5 are turned on.

Fig. 8 is a schematic diagram of a circuit showing a fourth embodiment of the present invention. The equalize circuit shown in Fig. 8 is different from the one shown in Fig. 1 in that PMOS transistors 4, 5 and 6 in Fig. 1 are removed. The equivalent circuit concerning the capacitance of the equalize circuit is the one in which the circuit on the side of the P channel is removed from the equivalent circuit shown in Fig. 3. A filtering circuit comprised of the capacitances CD3, and CS3 and the on-resistance RON is formed between node A and NMOS transistor 2. A filtering circuit comprised of the capacitances CD4 and CS4 and the on-resistance RON is also formed between node B and NMOS transistor 2. Accordingly, the capacitances between node A and the gate electrode of NMOS transistor 2 and between node B and the gate electrode of NMOS transistor 2 are reduced. As a result, the potentials of nodes A and B can be prevented from being raised at the moment NMOS transistor 2 is turned off.

Fig. 9 is a block diagram of a part of a DRAM device showing a fifth embodiment of the present invention. A DRAM device 100 shown in Fig. 9 includes a pair of word lines WL, and WL, provided in a row direction, a pair of bit lines B and /B provided in a column direction, memory cells MC each provided at an intersection of the word line and the bit line, data input/output lines 1/00, 1/01, a sense amplifier 101, column selecting transistors TR1 and TR2 provided between sense amplifier 101 and data -16 input/output lines I/00, I/01, and being turned on/off in response to a column selecting signal, a preamplifier 103 amplifying read data, an equalize circuit 102 provided in the preceding stage of preamplifier 103, and a main amplifier 104 further amplifying the amplified signal by preamplifier 103 to provide the further amplified signal to a data output terminal Do.

Preamplifier 103 includes differential amplifying circuits 105, 106 and 107, and an equalize circuit 108 equalizing signal lines connected to the output terminals of differential amplifying circuits 105 and 106. The equalize circuit shown in Fig. 1 is used as equalize circuit 108.

Equalize circuit 102 also has the same configuration as the equalize circuit shown in Fig. 1.

The operation of the DRAM device shown in Fig. 9 will now be described. Before the reading operation, the equalize activation signal ( is brought into a high level, and the equalize activation signal /xb is brought into a low level. Correspondingly, equalize circuit 102 connects data input/output lines I/00 and I/01 together to equalize the potentials of the data input/output line pair. Also, equalize circuit 108 equalizes the output lines connected to the output terminals of differential amplifiers 105 and 106. Corresponding to inversion of the equalize activation signals (, /( after the equalization, data input/output lines I/00 and I/01 are separated, so that the potentials appearing at data input/output lines I/00, I/01 are transferred. The signal lines connected to the data input/output line pair and the output terminals of differential amplifying circuits 105 and 106 are thus equalized, enabling application of a reference level to the signal transferred to each signal line.

After the equalization, data is read as follows.

Word line pair WLO and WL, provided in a row direction and bit line pair B and /B provided in a column direction are activated, whereby desired memory cell MC is selected. A data signal read from the selected memory cell MC is amplified by sense amplifier 101, and then transferred to data input/output lines I/00, I/01 through column selecting transistors TR1 and TR2. The data signal transferred to data input/output lines I/00, I/01 is amplified by preamplifier 103, and applied to main amplifier 104. Main amplifier 104 amplifies the data signal up to a potential capable of driving an external load, and applies the amplified data signal to a data output terminal Do.

In the fifth embodiment described above, the potentials of the data input/output line pair can be prevented from being raised at the moment equalize circuits 102 and 108 come into the inactive state, 18- enhancing data reading speed.

Although the reading operation alone is described in the fifth embodiment, data writing speed can be enhanced as well, by equalizing the data input/output line pair.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

19-

Claims

WHAT IS CLAIMED IS:

1. A semiconductor integrated circuit device including an equalize circuit equalizing potentials of first and second signal lines (A, B) for applying a logical signal, said equalize circuit comprising:

first and second switching means (2, 5/1, 4) provided in series between said first and second signal lines, (A, B) each having a control terminal and first and second conductive terminals; first signal supply means for supplying the control terminal of said first switching means (2, 5) with an equalize activation signal (), /(); and second signal supply means for supplying the control terminal of said second switching means (1, 4) with a voltage signal (Vcc, GND) of a predetermined potential to produce a capacitance (CD3, CS31 CD11 Cs1) of a predetermined value between the control terminal of the second switching means (1, 4) and the first and second conductive terminals of the second switching means (1, 4).

2. The semiconductor integrated circuit device according to claim 1, wherein said second switching means (1, 4) is provided either between said first signal line (A) and the first conductive terminal of said first switching means (2, 5), or between said second signal line (B) and the second conductive terminal of said first switching means (2, 5).

3. The semiconductor integrated circuit device according to claim 2, wherein each of said first and second switching means (2, 5 /1, 4) includes transistors of the different conductivity type.

4. The semiconductor integrated circuit device according to claim 2, wherein said equalize activation signal ((5, /() includes first and second signals in the complementary relation, said voltage signal (Vcc, GND) of a predetermined potential includes a power supply voltage (Vcc) and a ground voltage (GND), said first switching means (2, 5) includes a first transistor (2) of N type being turned on in response to said first signal (4)), and a second transistor (5) of P type being turned on in response to said second signal (M01 said second switching means (1, 4) includes a third transistor (1) of N type being continuously in the on- state in response to said power supply voltage (Vcc), and a fourth transistor (4) of P type being continuously in the on-state in response to said ground voltage (GND), said first and third transistors (2, 1) are connected in series between said first signal line (A) and said second signal line (B), and said second and fourth transistors (5, 4) are connected in series between said first signal line (A) and said second signal line (B).

5. A semiconductor integrated circuit device including an equalize circuit equalizing potentials of first and second signal lines for applying a logical signal, said equalize circuit comprising: a first node (A) provided on said first signal line; is a second node (B) provided on said second signal line; first and second switching means (2, 5) being turned on in response to an applied equalize activation signal ((h, /4)), each having a control terminal and first and second conductive terminals; first capacitance reducing means (1) connected between said first node (A) and the first conductive terminal of said first switching means (2) for reducing a capacitance between said first node and the control terminal of said first switching means (2); second capacitance reducing means (4) connected between said first node (A) and the first conductive terminal of said second switching means (5) for reducing a capacitance between said first node (A) and the control terminal of said second switching means (5); third capacitance reducing means (3) connected between said second node (B) and the second conductive terminal of said first switching means (5) for reducing a capacitance between said second node and the control terminal of said second switching means (5); and fourthcapacitance reducing means (6) connected between said second node (B) and the second conductive terminal of said second switching means (5) for reducing a capacitance between said second node (B) and the control terminal of said second switching means (5).

6. The semiconductor integrated circuit device according to claim 5, wherein said equalize circuit further includes a power supply node (Vcc) and a ground node (GND), said equalize activation signal ((5, /(h) includes first and second signals in the complementary relation, each of said first switching means (2) and said first and third capacitance reducing means (1, 3) includes an N type transistor, each of said second switching means (5) and said second and fourth capacitance reducing means (4, 6) includes a P type transistor, the N type transistor included in said first switching means (2) has its control terminal connected to receive said first signal ((h), the P type transistor included in said second switching means (5) has its control terminal connected to receive said second signal (/(), the N type transistors included in said first and third capacitance reducing means (1, 4) have their control terminals connected to the power supply node (Vcc), and the P type transistors included in said second and fourth capacitance reducing means (3, 6) have their control terminals connected to the ground node (GND).

7. A semiconductor integrated circuit device including an equalize circuit for equalizing potentials of first and second signal lines for applying a logical signal, said equalize circuit comprising:

a first node (A) provided on said first signal line; a second node (B) provided on said second signal line; first and second switching means (2, 5) being turned on in response to an input equalize activation signal ((, each having a control terminal and first and second conductive terminals; first capacitance reducing means (1) connected either between said first node (A) and the first conductive terminal of said first switching means (2), or between said second node (B) and the second conductive terminal of said first switching means (2) for reducing a capacitance between said first or second node (A, B) and the control terminal of said first switching means (2); and second capacitance reducing means (4) connected either between said first node (A) and the first conductive terminal of said second switching means (4), or between said second node (B) and the second conductive terminal of said second switching means (5) for reducing a capacitance between said first or second node (A, B) and the control terminal of said second switching means (5).

8. The semiconductor integrated circuit device according to claim 7, wherein said equalize circuit includes a power supply node (Vcc) and a ground node (GND), said equalize activation signal includes first and second signals in the complementary relation, each of said first switching means (2) and said first capacitance reducing means (1) includes an N type transistor, 1 each of said second switching means (5) and said second capacitance reducing means (4) has a P type transistor, and the N type transistor included in said first switching means (2) has its control terminal connected to receive said first signal (4)), the P type transistor included in said second switching means (5) has its control terminal connected to receive said second signal (/4)), the N type transistor included in said first capacitance reducing means (1) has its control terminal connected to the power supply node (Vcc), and the P type transistor included in said second capacitance reducing means (4) has its control terminal connected to the ground node (GND).

9. A semiconductor integrated circuit device including an equalize circuit equalizing potentials of first and second signal lines for applying a logical signal, said equalize circuit comprising:

a first node (A) provided on said first signal line; a second node (B) provided on said second signal line; switching means (2) having a control terminal and first and second conductive terminals, and being turned on in response to an input equalize activation signal (d?); -26 first capacitance reducing means (1) connected between said first node (A) and the first conductive terminal of said switching means (2) for reducing a capacitance between said first node (A) and the control terminal of said switching means (2); and second capacitance reducing means (3) connected between said second node (B) and the second conductive terminal of said switching means (2) for reducing a capacitance between said second node (B) and the control terminal of said switching means (2).

10. The semiconductor integrated circuit device according to claim 9, wherein each of said switching means (2) and said first and is second capacitance reducing means (1, 3) includes a transistor of the same conductivity type.

11. A semiconductor integrated circuit device constructed, adapted and arranged to operate substantially as described hereinbefore with reference to and as shown in figures 1 to 4, 5 and 6, 7, 8 or 9 of the accompanying drawings.