KR960003527B1 - Semiconductor integrated circuit device including equalizing circuit - Google Patents

Abstract

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Description

Semiconductor integrated circuit device including equalization circuit

1 is a circuit diagram showing one embodiment of the present invention.

2 is a cross-sectional structure diagram of the PMOS transistor shown in FIG.

3 is an equivalent circuit diagram of FIG. 1 focusing on capacitance.

4 is a waveform diagram of each node of the equalization circuit shown in FIG.

5 is a circuit diagram showing a second embodiment of the present invention.

6 is an equivalent circuit diagram of the equalization circuit of FIG. 5 focused on capacitance.

7 is a circuit diagram showing a fourth embodiment of the present invention.

8 is a circuit diagram showing a fifth embodiment of the present invention.

9 is a block diagram of a semiconductor memory device, showing a fifth embodiment of the present invention.

10 is a circuit diagram of a conventional equalization circuit.

FIG. 11 is a waveform diagram of each node of the equalization circuit shown in FIG.

FIG. 12 is a cross-sectional structure diagram of the PMOS transistor shown in FIG.

FIG. 13 is an equivalent circuit diagram of the equalizing circuit of FIG. 10 focused on capacitance. FIG.

FIG. 14 is a cross-sectional structure diagram for explaining a change in capacitance of the PMOS transistor shown in FIG.

FIG. 15 is a graph showing the relationship between the capacitance between the gates and the gate drains of a MOS transistor and the gate electrode; FIG.

TECHNICAL FIELD The present invention relates to a semiconductor static circuit device, and more particularly, to an improvement in an equalization circuit for equalizing a potential between two nodes.

BACKGROUND OF THE INVENTION Semiconductor integrated circuit devices such as microcomputers and semiconductor storage devices are equipped with many equalizing circuits.

An equalization circuit is provided between a pair of signal lines requiring a reference level in a semiconductor integrated circuit device, and sets the pair of signal lines as logical limits by setting the potential of the pair of signal lines to the same potential.

10 is a circuit diagram showing a conventional example of such an equalization circuit.

The equalizing circuit shown in FIG. 10 includes an N-channel MOS transistor 2 (hereinafter referred to as an NMOS transistor) and a P-channel MOS transistor 5 (hereinafter referred to as a PMOS transistor).

The NMOS transistor 2 is connected so that its gate electrode receives the equalization activation signal ψ, its drain electrode is connected to the node A, and its source electrode is connected to the node B.

The PMOS transistor 5 is connected so that its gate electrode receives the equalization activation signal / ψ, its drain electrode is connected to the node A, and its source electrode is connected to the node B.

Further, S1 and S2 are a pair of signal lines.

FIG. 11 is a waveform diagram of each node of the equalization circuit shown in FIG.

FIG. 11A shows waveforms of the equalization activation signals ψ and / ψ, and (b) is the waveforms of the nodes A and B. FIG.

10 and 11, the operation of the equalizing circuit shown in FIG. 10 will be described.

First, when the node A and the node B are at the same potential, the equalization activation signal? Is at a high level, and the equalization activation signal / is at a low level.

In response, the NMOS transistor 2 and the PMOS transistor 5 are turned on. Node A and node B are connected so that the potentials of node A and node B are 1 / 2Vcc.

Next, when the power supply voltage Vcc is provided to the signal line S1 and the ground potential is provided to the signal line S2 as the data signal, the equalization activation signal?

In response, the NMOS transistor 2 and the PMOS transistor 5 are turned off. In this way, the node A and the node B are separated, and the potentials of the nodes A and B converge on the levels of the signals provided to the signal lines S1 and S2. However, when the equalization activation signal ψ transitions from low level to high level, the potentials of nodes A and B rise once.

For this reason, it is late for the potential of the nodes A and B to converge on the signal level.

This will be described in detail with reference to FIGS. 12 to 15.

FIG. 12 is a cross-sectional structure diagram of the PMOS transistor 5 shown in FIG.

FIG. 13 is an equivalent circuit diagram focusing on the capacitance of the MOS transistors shown in FIG.

14 is a cross-sectional structure diagram for explaining the change in capacitance of the PMOS transistor 5.

FIG. 15 is a graph showing the relationship between the capacitance between the gate sources and the gate drains of the MOS transistors and the equalization activation signal ψ (gate electrode).

Referring to FIG. 12, a PMOS transistor 5 is formed on an N-type semiconductor substrate 20, a P-type source region 21, a P-type drain region 22 and a channel region 23. As shown in FIG. A gate electrode 24 is provided.

A parasitic capacitance C _DP exists between the gate electrode 24 and the drain region 21.

There is a parasitic capacitance C _SP between the gate electrode 24 and the source region 22.

Such capacitance is similarly present with respect to the NMOS transistor 2.

Focusing on these capacitances, the equalization circuit shown in FIG. 10 can be represented by the equivalent circuit of FIG.

The following describes the change in capacitance C _DP and C _SP with reference to FIG. 14.

When the equalization activation signal / ψ is at a low level, the gate electrode 24 charges negatively, and electrons in the channel region 23 are chased away, and the charge in the flask appears.

In this manner, the channel region 24 is deepened, so that the charge of the flask accumulated in the channel 24 increases.

Therefore, the capacitances C _DP and C _SP become large as shown in FIG.

As a result, when the equalization activation signal / ψ transitions from low level to high level, it is influenced by the capacitance C _SP between the gate sources of the PMOS transistor 5 and the capacitance C _DP between the gate drains, as shown in FIG. , The potentials of nodes A and B rise once.

Therefore, the equalization circuit becomes inactive and it is late to converge the potentials of the nodes A and B that have been equalized to the potentials provided to the signals S1 and S2.

An object of the present invention is to shorten the time until the equalization circuit becomes inactive and the equalization circuit becomes inactive and the potential of the node that has been equalized converges.

In one aspect of the invention, a semiconductor integrated circuit device includes an equalization circuit for equalizing the potentials of the first and second signal lines providing a logic circuit.

The equalizing circuit includes at least a first and a second switching circuit, a first signal supply node and a second signal supply node.

Each of the first and second switching circuits has a control terminal and first and second conductive terminals, and is connected in series between the first and second signal lines.

The first signal supply node applies the equalization enable signal to the control terminal of the first switching circuit.

The second signal supply node applies a voltage signal of a predetermined potential to the control terminal of the second switching circuit so that a capacitance of a predetermined value between the control terminal and the first and second conductive terminals of the second switching circuit is applied. Occurs.

In operation, the second switch circuit is turned on in response to a voltage signal of a predetermined potential to generate a predetermined value of capacitance between the control terminal and the first and second conductive terminals, the capacitance being switched on the first switching. It can be connected in series between the control terminal of the circuit and the first and second signal lines, resulting in a reduction in capacitance between the first and second signal lines and the control terminal of the first switching circuit.

Therefore, the electric charge accumulated in the first switching circuit is reduced to prevent the potentials of the first and second signal lines from rising at the moment when the first switching circuit is turned off.

As a result, the first and second signal lines can obtain the level of the applied logic signal in a shorter time after the first switching circuit is turned off.

In another aspect of the invention, an equalization circuit comprises a first node provided on a first signal line, a second node provided on a second signal line, first and second switching means, and a first node. And a fourth capacitance reducing means.

The first and second switches, having control terminals and first and second conductive terminals, are turned on in response to the applied equalization activation signal.

The first capacitance reducing means is connected between the first node and the first conducting terminal of the switching means to reduce the capacitance between the first node and the control terminal of the first switching means.

The second capacitance reducing means is connected between the first node and the first conducting terminal of the second switching means to reduce the capacitance between the first node and the control terminal of the second switching means.

The third capacitance reducing means is connected between the second node and the second conducting terminal of the first switching means to reduce the capacitance between the second node and the control terminal of the first switching means.

The fourth capacitance reducing means is connected between the second node and the second conducting terminal of the second switching means to reduce the capacitance between the second node and the control terminal of the second switching means.

In operation, the first capacitance reducing means and the second capacitance reducing means are provided between the first node and the first conducting terminal of the first and second switching means, respectively, and the third and fourth capacitance reducing means. Means are provided between the second node and the second conductive terminals of the first and second switching means, respectively.

Therefore, the capacitance between the first node and the control terminals of the first and second switching means, and the capacitance between the second node and the control terminals of the first and second switching means can be reduced.

Thus, the charge accumulated in each of the means of the first and second switches is reduced, so that the rise of the potentials of the first and second nodes can be suppressed at the moment when the first and second switching means are turned off.

As a result, the potentials of the first and second nodes can obtain the level of the provided signal in a shorter time after the first and second switching elements are turned off.

In yet another aspect of the present invention, a semiconductor integrated circuit device includes first and second nodes, first and second switching means, first capacitance reducing means, and second capacitance reducing means. Include.

The first capacitance reducing means is connected between the first conducting terminal of the first switching means and the first node, or between the second conducting terminal of the first switching means and the second node, and the first switching is performed. The capacitance between the control terminal of the device and the first or second node is reduced.

The second capacitance reducing means is connected between the first conducting terminal of the second switching means and the first node, or between the second conducting terminal of the second switching means and the second node, The capacitance between the control terminal of the switching means and the first or second node is reduced.

In operation, the first capacitance reducing means reduces the capacitance between the control terminal of the first switching means and the first or second node, and the second capacitance reducing means is connected with the control terminal of the second switching means. Reduce capacitance between the first or second node.

Thus, generation of noise can be prevented when the switching means are turned off.

EXAMPLE

1 is a circuit diagram showing one embodiment of this invention.

What is different from the equalizing circuit shown in FIG. 1 and the equalizing circuit shown in FIG. 10 is that the NMOS transistor 1 is provided between the node A and the drain electrode of the NMOS transistor 2, and the node B and the NMOS transistor ( The NMOS transistor 3 is provided between the source electrode of 2) and the PMOS transistor 6 is provided between the node A and the source electrode of the PMOS transistor 5.

The NMOS transistor 1 has its gate electrode connected to the power supply voltage Vcc, its drain electrode connected to the node A, and its source electrode connected to the drain electrode of the NMOS transistor 2.

The NMOS transistor 3 has its gate electrode connected to the power supply voltage Vcc, its source electrode connected to the source electrode of the NMOS transistor 2, and its drain electrode connected to the node B.

The PMOS transistor 4 has its gate electrode connected to the ground terminal GND, its drain electrode connected to the node A, and its source electrode connected to the drain electrode of the PMOS transistor 5.

The PMOS transistor 6 has its gate electrode connected to the ground terminal GND, its source electrode connected to the source electrode of the PMOS transistor 5, and its drain electrode connected to the node B.

The NMOS transistors 1 and 3 and the PMOS transistors 4 and 6 are always in the ON state.

Therefore, this equalizing circuit is activated when the equalizing activation signal ψ is high level and / psi is low level similarly to the equalizing circuit shown in FIG.

FIG. 2 is a cross-sectional structural view of the PMOS transistors 4, 5 and 6 shown in FIG.

Referring to FIG. 2, the PMOS transistor 4 includes a P-type drain region 25, a gate electrode 26, a P-type drain region 21, and a channel region 27. As shown in FIG.

The drain region 21 is shared with the source region 21 of the PMOS transistor 5.

The PMOS transistor 6 includes a P-type drain region 28, a P-type source region 22, and a gate electrode 29.

The source region 22 shares the source region 21 of the PMOS transistor 5.

The PMOS transistor 5 is the same as that shown in FIG.

In the PMOS transistors 4 and 6, the gate electrodes 26 and 29 are connected to the ground terminal GND, and in the channel regions 27 and 32, the charge of the flask is stored.

As a result, capacitance C _D1 exists between the gate electrode 26 and the drain region 25 of the PMOS transistor 4, and C _S1 exists between the gate electrode 26 and the source region 21. .

Capacitance C _S2 is present between the gate electrode 29 and the source region 22 of the PMOS transistor 6, and capacitance C _D2 is present between the gate electrode 29 and the drain region 28.

Since the PMOS transistors 4 and 6 are always ON, the capacitances C _D1 , C _S1 , C _D2 and C _S2 are the largest.

3 is an equivalent circuit of the equalization circuit of FIG. 1 focusing on the capacitance.

As described in FIG. 2, parasitic capacitances exist in the PMOS transistors 4, 5 and 6, and parasitic capacitances exist in the NMOS transistors 1, 2 and 3 in the same manner. do.

The NMOS transistor 1 has a capacitance C _D3 between its gate drain and a capacitance C _S3 between its gate and source.

The NMOS transistor 6 has a capacitance C _S4 between its gate and a source, and has a capacitance C _D4 between its gate and a drain.

In addition, the R _ON shown in FIG. 3 is a resistance value at the time of ON state of each MOS transistor.

By the equivalent circuit of FIG. 3, the capacitance between the node A and the gate electrode of the NMOS transistor 2 and the capacitance between the node B and the gate electrode of the NMOS transistor 2 are higher than C _DN and C _SN , respectively. small.

In addition, the capacitance between the node A and the gate electrode of the PMOS transistor 5 and the capacitance between the node B and the gate electrode of the NMOS transistor 5 are smaller than C _DP and C _SP .

Therefore, the charge of the flask accumulated in the PMOS transistor 5 easily flows to the ground terminal C _ND , and the negative charge accumulated in the NMOS transistor 2 easily flows to the power supply terminal Vcc.

For this reason, it is possible to suppress that the potentials of the nodes A and B rise when the NMOS transistor 2 and the PMOS 5 are turned off.

In this manner, when the MOS transistors 2 and 5 are OFF, the time for which the potentials of the nodes A and B converge to the signal level can be shortened.

4 is a waveform diagram of each node of the equalization circuit shown in FIG.

The waveform diagram shown in FIG. 4 differs from the waveform diagram shown in FIG. 11 in the capacitances C _DN , C _SN , C _DP and C _SP immediately after the MOS transistors 2 and 5 are turned off. Noise has not occurred.

This is because, as described above, the capacitance between the node A and the gate electrode and the capacitance between the node B and the gate electrode are reduced.

5 is a circuit diagram showing a second embodiment of this invention.

Where the equalizing circuit shown in FIG. 5 differs from the equalizing circuit shown in FIG. 1, the NMOS transistor 3 and the PMOS transistor 6 are excluded.

FIG. 6 is an equivalent circuit of FIG. 5 focusing on capacitance.

With reference to FIG. 6, the filter which consists of ON resistance R _ON , capacitance C _D3, and C _S3 is formed between node A and capacitance C _DN .

In addition, a filter circuit including capacitances C _D1 and C _S1 is formed between the node A and the capacitance C _DP .

As a result, the capacitance between the node A and the gate electrodes of the MOS transistors 2 and 5 is reduced.

As a result, the accumulated charge easily flows when the MOS transistors 2 and 5 are turned off, and the potentials of the nodes A and B can be suppressed from rising.

7 is a circuit diagram showing a third embodiment of this invention.

Where the equalizing circuit shown in FIG. 7 differs from the equalizing circuit shown in FIG. 5, the MOS transistors 1 and 4 on the node A side of the equalizing circuit shown in FIG. 1 are removed. .

In this embodiment, the capacitance between the node B and the gate electrode of the NMOS transistor 2 and the capacitance between the node B and the gate electrode of the PMOS transistor 5 can be reduced.

As in the case of FIG. 5, when the MOS transistors 2 and 5 are on, the potential of the nodes A and B can be suppressed from rising.

8 is a circuit diagram showing a fourth embodiment of this invention.

In FIG. 8, where the equalizing circuit shown in FIG. 8 differs from the equalizing circuit shown in FIG. 1, the PMOS transistors 4, 5 and 6 are removed.

The equivalent circuit focusing on the capacitance of this equalization circuit removes the P-channel side circuit from the equivalent circuit shown in FIG.

Therefore, a filter circuit having capacitances C _D3 and C _S3 and an on resistance R _ON is formed between the node A and the NMOS transistor 2.

Further, a filter circuit having capacitances C _D4 and C _S4 and an on resistance R _ON is formed between the node B and the NMOS transistor 2.

Therefore, the capacitance between the node A and the gate electrode of the NMOS transistor 2 and the node B and the gate electrode of the NMOS transistor 2 are reduced.

As a result, it is possible to suppress that the potentials of the nodes A and B rise when the NMOS transistor 2 is turned off.

9 is a block diagram of a part of a semiconductor integrated circuit device which shows a fifth embodiment of this invention.

The semiconductor integrated circuit device 100 shown in FIG. 9 includes word lines WL ₀ and WL ₁ provided in the row direction, bit line pairs B and / B provided in the column direction, and a memory provided at the intersection of the word line and the bit line. It is provided between the cell MC, the data input / output line I / O ₀ , I / O ₁ , the sense amplifier 101, the sense amplifier 101 and the data input / output line I / O ₀ , I / O ₁ , and selects a column. The column selection transistors TR ₁ and TR ₂ that respond to the signal Y and are turned on and off; an equalization circuit 102 provided in front of the preamplifier 103 and the preamplifier 103 for amplifying the read data; The main amplifier 104 further amplifies the signal amplified by the preamplifier 103 and outputs the amplified signal to the data output terminal D ₀ .

The preamplifier 103 is provided with differential amplifier circuits 105, 106 and 107, and an equalization circuit 108 for equalizing signal lines connected to the output terminals of the differential amplifier circuits 105 and 106. It is.

As the equalization circuit 108, the equalization circuit shown in FIG. 1 is used.

The equalization circuit 102 also has the same configuration as the equalization circuit shown in FIG.

Next, the reading operation of the semiconductor memory device shown in FIG. 9 will be described.

Before the read operation, the equalization activation signal? Is at a high level, and the equalization activation signal / is at a low level.

In response, the equalizing circuit 102 connects the data input / output I / O ₀ and I / O ₁ to a potential equal to that of the data output line pair.

Similarly, the equalization circuit 108 equalizes the output lines connected to the output terminals of the differential amplifiers 105 and 106.

After the equalization, when the equalization enable signals ψ and / ψ are reversed, they respond, and the data input / output I / O ₀ and I / O ₁ are separated, and the potential shown on the data output lines I / O ₀ and I / O ₁ is obtained. To pass.

In this way, by equalizing the signal lines connected to the data input / output line pairs and the output terminals of the differential amplifier circuits 105 and 106, a reference level can be provided for the signals transmitted to the respective signal lines.

After equalizing in this way, the data is read as follows.

That is, the memory cells MC for fire fighting are selected by activating the word lines WL ₀ and WL _{1 provided} in the row direction and the bit line pairs B and / B provided in the column direction.

The data signal read from the selected memory cell MC is amplified by the sense amplifier 101 and then transferred to the data input / output lines I / O ₀ and I / O ₁ through the column selection transistors TR ₁ and TR ₂ .

The data signals transmitted to the data input / output lines I / O ₀ and I / O ₁ are amplified by the preamplifier 103 and then provided to the main amplifier 104.

The main amplifier 104 amplifies the data signal to a potential capable of driving an external load and provides the amplified data signal to the data output terminal D ₀ .

In the fifth embodiment described above, when the equalization circuits 102 and 108 transition to an inactive state, the potential of the data output line pair can be suppressed from rising, so that the data reading speed can be improved. have.

Further, in the fifth embodiment, only the reading has been described. However, since the data input / output line pairs can be equalized, the data recording speed can be similarly improved.

Although the invention has been described in detail, it is clearly understood that the examples and description are the same and are not limiting, the spirit and scope of the invention being limited only by the appended claims.

Claims (10)

A semiconductor integrated circuit device comprising an equalization circuit for equalizing the potentials of the first and second signal lines A and B to which a logic signal is applied, wherein the equalizing circuit includes the first and second signal lines ( A first and second switching means 2, 5/1, 4 provided in series between A and B, having a control terminal, first and second conductive terminals, and an equalization activation signal? , / ψ) the first mutual supply means for supplying the control terminals of the first switching means (2, 5), the control terminal of the second switching means (1, 4) and the second switching means ( The second voltage is generated by the voltage signal Vcc GND of a predetermined potential to generate a predetermined capacitance C _D3 , C _S3 , C _D1 , C _S1 between the first and second conductive terminals 1 and 4). And a second signal supply means for supplying a control terminal of the switching means (1, 4). 2. The second switching means (1, 4) according to claim 1, wherein the second switching means (1, 4) is connected between the first signal line (A) and the first conducting terminal of the first switching means (2, 5) or the second switching means (1). A semiconductor integrated circuit device provided between a signal line (B) and a second conductive terminal of said first switching means (2, 5). 3. A semiconductor integrated circuit device according to claim 2, wherein each of said first and second switching means (2, 5/1, 4) comprises different conducting transistors. 3. The method according to claim 2, wherein the equalization activation signals (ψ, / ψ) comprise first and second signals of correlation, and the voltage signals (Vcc, GND) of a predetermined potential are the power supply voltage (Vcc). The first switching means (2, 5) comprises a ground voltage (GND), the first transistor (2) of the N-type and the second signal is turned on in response to the first signal (ψ) a second P-type transistor 5 which is turned on in response to (/?), and the second switching means 1, 4 are N in response to the power supply voltage Vcc and remain in an on state. A third transistor (1) of the type and a fourth transistor (4) of the P type that is in an on state in response to the ground voltage (GND), wherein the first and third transistors (2, 1) is connected in series between the first signal line A and the second signal line B, and the second and fourth transistors 5, 4 are connected to the first signal line A and the Directly between the second signal lines B A semiconductor integrated circuit device connected in series. A semiconductor integrated circuit device comprising an equalization circuit for equalizing potentials of first and second signal lines to which a logic signal is applied, wherein the equalizing circuit includes a first node A provided to the first signal line. ), A second node B provided to the second signal line, and turned on in response to the applied equalization activation signals ψ and / ψ, and having a control terminal and first and second conductive terminals. First and second switching means (2, 5) and the first switching means (2) of the first switching means (2) to reduce capacitance between the first node and the control terminal of the first switching means (2) A first capacitance reducing means connected between the first conducting terminal and the first node A, and a second connected between the first node A and the second switching means 5; The capacitance between the capacitance means and the control terminal of the second node and the second switching means 5 Third capacitance reducing means 3 connected between the second node B and the second conducting terminal of the first switching means 5, and the second node B for reducing. And a fourth connected between the second node B and the second conducting terminal of the second switching means 5 to reduce the capacitance between the control terminal of the second switching means 5 and the second switching means 5. And a capacitance reduction means (6) of the semiconductor integrated circuit device. 6. The method of claim 5, wherein the equalizing circuit includes a power supply node (Vcc) and a ground node (GND), and the equalizing enable signals (ψ, / ψ) include first and second signals having a complementary relationship. Each of the first switching means 2 and the first and third capacitance reducing means 1, 3 includes an N-type transistor, and each of the second switching means 5 and the second And the fourth capacitance reducing means (4, 6) comprise a P-type transistor, and the N-type transistor included in the first switching means (2) is connected to receive the first signal (ψ). P-type transistor having a control terminal, and included in the second switching means 5, has its control terminal connected to receive the second signal (/ ψ), and reduces the first and third capacitances. The N-type transistors included in the means 1, 4 have their control terminals connected to the power supply node Vcc, A P-type transistor included in the second and fourth capacitance reducing means (3, 6) has their control terminal connected to a ground node (GND). A semiconductor integrated circuit device comprising an equalization circuit that equalizes potentials of first and second signal lines to which a logic signal is applied, wherein the equalizing circuit includes a first node A provided to the first signal line. ), A second node B provided to the second signal line, and turn on in response to an input equalization activation signal ψ, / ψ, and control terminals and first and second conductive terminals. To reduce the capacitance between the first and second switching means (2, 5), the first or second node (A, B) and the control terminal of the first second switching means (2). Between the first node A and the first conducting terminal of the first switching means 2 or a second conduction of the second node B and the first switching means 2. Between the first capacitance reducing means 1 connected between the terminals and the control terminal of the first or second node A, B and the second switching means 5; Second capacitance reducing means connected between the first node A and the second node B and the second conducting terminal of the second switching means 5 to reduce the capacitance of A semiconductor integrated circuit device comprising 4). 8. The method of claim 7, wherein the equalizing circuit comprises a power supply node (Vcc) and a ground node (GND), and the equalizing enable signals (ψ, / ψ) include first and second signals in a complementary relationship. Each of the first switching means 2 and the first capacitance reducing means 1 includes an N-type transistor, and each of the second switching means 5 and the second capacitance reducing means ( 4) has a P-type transistor, the N-type transistor included in the first switching means 2 has its control terminal connected to receive the first signal ψ, and the second switching The P-type transistor included in the means 5 has its control terminal connected to receive the second signal /, and the N-type transistor included in the first capacitance reducing means 1 is a power supply node. The second capacitance reduction number has its control terminal connected to (Vcc) (4) P-type transistor has a semiconductor integrated circuit device having its control terminal connected to the ground node (GND) it included in the. A semiconductor integrated circuit device comprising an equalization circuit that equalizes potentials of first and second signal lines to which a logic signal is applied, wherein the equalizing circuit includes a first node A provided to the first signal line. And switching means having a second node B provided to the second signal line, a control terminal and first and second conducting terminals, which are turned on in response to an input equalization activation signal ψ ( A first capacitance reducing means (1) connected between the first node (A) and a first conducting terminal of the switching means (2) and the second node in order to reduce the capacitance therebetween; A second capacitance reduction connected between the second node B and the second conducting terminal of the switching means 2 to reduce the capacitance between (B) and the control terminal of the switching means 2. A semiconductor integrated circuit device comprising means (3). 10. The semiconductor integrated circuit device according to claim 9, wherein said switching means (2) and said capacitance reducing means (1, 3) of said first and second comprise transistors of the same conductivity type.