JPH05335919A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the level fluctuation in a signal line pair to be equalized when an equalization circuit transits from an active state to an inactive state. CONSTITUTION:This device is provided with NMOS transistors(TRs) 1, 2, 3 provided in series between nodes A, B and PMOS TRs 4, 5, 6 provided in series between the nodes A, B. The NMOS TRs 1, 3 and the PMOS TRs 4, 6 are usually active and the NMOS TR 2 and the PMOS TR 5 are turned ON/OFF in response to equalize active signals phi and the inverse of phi. Thus, the capacitance among the node A, the NMOS TR 2 and the gate electrode of the PMOS TR 5 is reduced and the capacitance among the node B, the NMOS TR2 and the gate electrode of the PMOS TR 5 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of an equalize circuit for equalizing potentials between two nodes.

[0002]

2. Description of the Related Art Semiconductor integrated circuit devices such as microcomputers and semiconductor memory devices are provided with many equalizing circuits. The equalizing circuit is provided between a pair of signal lines requiring a reference level in the semiconductor integrated circuit device, and sets the potentials of the pair of signal lines to the same potential, thereby logically thresholding the pair of signal lines. Value.

FIG. 10 is a circuit diagram showing a conventional example of such an equalizing circuit. The equalizing circuit shown in FIG. 10 is an N-channel MOS transistor 2 (hereinafter referred to as NMO).
S-transistor) and P-channel MOS
The transistor 5 (hereinafter referred to as a PMOS transistor) is included.

The NMOS transistor 9 has its gate electrode connected to receive the equalize activation signal φ,
Its drain electrode is connected to node A and its source electrode is connected to node B. PMOS transistor 5
Has its gate electrode connected to receive equalize activation signal / φ, its drain electrode connected to node A, and its source electrode connected to node B. In addition,
S1 and S2 are a pair of signal lines.

FIG. 11 is a waveform diagram of each node of the equalize circuit shown in FIG. FIG. 11A shows the waveforms of the equalize activation signals φ and / φ, and FIG. 11B shows the waveforms of the nodes A and B.

The operation of the equalize circuit shown in FIG. 10 will be described with reference to FIGS. 10 and 11.

First, when the potentials of the node A and the node B are made equal, the equalize activation signal φ is set to the high level and the equalize activation signal / φ is set to the low level.
In response, the NMOS transistor 2 and the PMOS transistor 5 are turned on. The node A and the node B are connected and the potentials of the node A and the node B become 1/2 Vcc.

When the power supply voltage Vcc is applied to the signal line S1 and the ground potential is applied to the signal line S2 as data signals, the equalize activation signal φ is set to low level and the equalize activation signal / φ is set high. To level. In response, N
The MOS transistor 2 and the PMOS transistor 5 are turned off. In this way, the node A and the node B are separated, and the potentials of the nodes A and B converge on the level of the signal applied to the signal lines S1 and S2.

[0009]

However, when the equalize activation signal φ transits from the low level to the high level,
The potentials of the nodes A and B rise for a moment. For this reason,
The potentials of the nodes A and B slow to converge to the signal level.

This will be described in detail with reference to FIGS. 12 to 15.

FIG. 12 is a sectional structural view of the PMOS transistor 5 shown in FIG. FIG. 13 is an equivalent circuit diagram focusing on the capacitance of the MOS transistor shown in FIG. FIG. 14 is a sectional structural view for explaining the change in capacitance of the PMOS transistor 5. FIG. 15 is a graph showing the relationship between the gate-source and gate-drain capacitances of the MOS transistor and the equalize activation signal φ (gate voltage).

Referring to FIG. 12, the PMOS transistor 5 includes an N type semiconductor substrate 20 and a P type source region 21.
A P-type drain region 22, a channel region 23,
The gate electrode 24 is formed on the channel region 23 with an insulating layer (not shown) interposed. A capacitance C _DP exists parasitically between the gate electrode 24 and the drain region 21. A capacitance C _SP parasitically exists between the gate electrode 24 and the source region 22. Such capacitance exists in the NMOS transistor 2 as well. Focusing on these capacitances, the equalizing circuit shown in FIG. 10 can be represented by an equivalent circuit shown in FIG.

Next, referring to FIG. 14, the capacitance C _DP
And the changes in C _SP are explained.

First, when the equalize activation signal / φ becomes low level, the gate electrode 24 is negatively charged, the electrons in the channel region 24 are driven away, and a positive charge appears. In this way, the channel region 24 becomes deep, and the amount of positive charges accumulated in the channel 24 increases. Therefore, the capacitances C _DP and C _SP become large as shown in FIG.

As a result, when the equalize activation signal / φ transits from the low level to the high level, it is affected by the gate-source capacitance C _SP and the gate-drain capacitance C _DP of the PMOS transistor 5, and As shown in 11, the potentials of the nodes A and B are momentarily raised. Therefore, after the equalizing circuit is inactivated, the potentials of the equalized nodes A and B are slowed to converge to the potentials given to the signals S1 and S2.

Therefore, an object of the present invention is to shorten the time from the inactivation of the equalizing circuit to the convergence of the potential of the equalized node.

[0017]

A semiconductor integrated circuit device according to a first aspect of the present invention includes first and second nodes, first and second switch means, which are required to have the same potential, and first and second switch means.
To fourth capacitance reducing means.

The first and second switch means each have a control terminal and first and second conduction terminals, and are turned on / off in response to an equalize activation signal inputted.

The first capacitance reducing means is connected between the first node and the first conductive terminal of the first switch means, and is connected between the first node and the control terminal of the first switch means. Reduce the capacitance of.

The second capacitance reducing means is connected between the first node and the first conducting terminal of the second switch means, and between the first node and the control terminal of the second switch means. Reduce the capacitance of.

The third capacitance reducing means is connected between the second node and the second conducting terminal of the first switch means, and between the second node and the control terminal of the first switch means. Reduce the capacitance of.

The fourth capacitance reducing means is connected between the second node and the second conductive terminal of the second switch means, and is connected between the second node and the control terminal of the second switch means. Reduce capacitance.

A semiconductor integrated circuit device according to a second aspect of the present invention, like the semiconductor integrated circuit device of the first aspect, includes first and second nodes, first and second switch means, and A first capacitance reducing means and a second capacitance reducing means are included.

The first capacitance reducing means is between the first node and the first conducting means of the first switch means and between the second node and the second conducting terminal of the first switch means. It is connected to either one and reduces the capacitance between the first or second node and the control means of the first switch means.

The second capacitance reducing means is between the first node and the first conductive terminal of the second switch means and between the second node and the second conductive terminal of the second switch means. To reduce the capacitance between the first or second node and the control terminal of the second switch means.

A semiconductor integrated circuit device according to a third aspect of the present invention comprises first and second nodes that need to be at the same potential, switch means, and first and second capacitance reducing means.

The switch means has a control terminal and first and second conduction terminals, and is turned on / off in response to an input equalize activation signal.

The first capacitance reducing means is connected between the first node and the first conductive terminal of the first switch means and reduces the capacitance between the first node and the control terminal of the switch means. To do.

The second capacitance reducing means is connected between the second node and the second conductive terminal of the switch means, and reduces the capacitance between the second node and the control terminal of the switch means.

According to another aspect of the semiconductor integrated circuit device of the present invention, the first and second nodes which need to have the same potential, the first to third N-channel MOS transistors, and the first to third nodes. P channel type MOS transistor.

The first N-channel MOS transistor is turned on in response to the input equalize activation signal.
/ OFF.

The first P-channel type MOS transistor is turned on / off in response to the input equalize activation signal.
Turn off.

In the second N-channel MOS transistor, the drain electrode is connected to the first node and the first N-channel MOS transistor is connected.
The source is connected to the drain electrode of the channel type MOS transistor, and the gate electrode is connected to receive the power supply voltage.

In the second P-channel MOS transistor, the drain electrode is connected to the first node and the first P-channel MOS transistor is connected.
The source electrode is connected to the drain electrode of the channel type MOS transistor, and the gate electrode is connected to the ground terminal.

In the third N-channel MOS transistor, the source electrode is connected to the second node, the source electrode is connected to the source electrode of the first N-channel MOS transistor, and the gate electrode receives the power supply voltage. Connected to.

In the third P-channel MOS transistor, the drain electrode is connected to the second node and the first P-channel MOS transistor is connected.
The source electrode of the channel MOS transistor is connected to the source electrode, and the gate electrode is connected to the ground terminal.

[0037]

According to the invention of claim 1, a first capacitance reducing means and a second capacitance reducing means are provided between the first node and the first conducting terminals of the first and second switch means, respectively. And the third and fourth capacitance reducing means are provided between the second node and the second conducting terminals of the first and second switch means. Therefore, the capacitance between the control terminals of the first and second switch means and the first node,
And the capacitance between the control terminal of the second switch means and the second node can be reduced. As a result, the electric charge accumulated in each of the first and second switch means becomes small, and the first and second switch means become O.
It is possible to prevent the potentials of the first and second nodes from rising at the time of FF. As a result, the first and second
The time from when the switch means of (1) is turned off until the potentials of the first and second nodes reach the level of the applied signal is shortened.

In the invention of claim 2, the capacitance between the first or second node and the control terminal of the first switch means is reduced by the first capacitance reducing means, and the second capacitance reducing means is used. , Reducing the capacitance between the first or second node and the control terminal of the second switch means. This makes it possible to suppress the noise generated when the switch means is turned off. Further, the number of capacitance reducing means is smaller than that of the invention according to claim 1, and the configuration of the semiconductor integrated circuit device can be simplified.

In the invention according to claim 4, the N-channel MOS transistor is arranged between the first node and the second node in the order of the second NMOS transistor, the first NMOS transistor, and the third NMOS transistor. Connected to. Also, between the first node and the second node, P
The channel type MOS transistor is connected in the order of the second P channel type MOS transistor, the first P channel type MOS transistor, and the third P channel type MOS transistor. Since the second and third N-channel MOS transistors and the second and third P-channel MOS transistors are always in the ON state, these O
The capacitances of the first P-channel type MOS transistor and the first N-channel type MOS transistor can be reduced by the gate-source and gate-drain capacitances generated by the MOS transistor in the N state. ..

As a result, it is possible to prevent the potentials of the first and second nodes from rising at the time when the first P-channel type MOS transistor and the first N-channel type MOS transistor are turned off.

[0041]

1 is a circuit diagram showing an embodiment of the present invention. The difference between the equalizing circuit shown in FIG. 1 and the equalizing circuit shown in FIG. 10 is that the NMOS transistor 1 is provided between the node A and the drain electrode of the NMOS transistor 2, and the node B and the source electrode of the NMOS transistor 2 are connected. An NMOS transistor 3 is provided therebetween, a PMOS transistor 4 is provided between the node A and the drain electrode of the PMOS transistor 5, and a node B is provided.
And the source electrode of the PMOS transistor 5 between the PMO
That is, the S transistor 6 is provided.

The NMOS transistor 1 has its gate electrode connected to the power supply voltage Vcc, its drain electrode connected to the node A, and its source electrode connected to the drain electrode of the NMOS transistor 2. The NMOS transistor 3 has its gate electrode connected to the power supply voltage Vcc, its source electrode connected to the source electrode of the NMOS transistor 2, and its drain electrode connected to the node B. The PMOS transistor 4 has its gate electrode connected to the ground terminal GND, its drain electrode connected to the node A, and its source electrode connected to the drain electrode of the PMOS transistor 5. The PMOS transistor 6 has its gate electrode connected to the ground terminal GND, its source electrode connected to the source electrode of the PMOS transistor 5, and its drain electrode connected to the node B. NMOS transistors 1 and 3 and PMO
S transistors 4 and 6 are always on. Therefore, like the equalize circuit shown in FIG. 10, this equalize circuit is activated when equalize activation signal φ is at a high level and / φ is at a low level.

FIG. 2 is a sectional structural view of the PMOS transistors 4, 5 and 6 shown in FIG. Referring to FIG. 2, the PMOS transistor 4 has a P-type drain region 2
5, the gate electrode 26, the P-type drain region 21,
And a channel region 27. The drain region 21 is PM
It is shared with the source region 21 of the OS transistor 5. P
The MOS transistor 6 includes a P-type drain region 28,
The P-type source region 22 and the gate electrode 29 are provided.
The source region 22 shares the source region 21 of the PMOS transistor 5. The PMOS transistor 5 is
It is similar to that shown in FIG.

The PMOS transistors 4 and 6 are
The gate electrodes 26 and 29 are connected to the ground terminal GND
And channel regions 27 and 32 have a positive charge.
Is accumulated. Thereby, the PMOS transistor 4
Capacitance is provided between the gate electrode 26 and the drain region 25.
Closet C_D1Exists, and the gate electrode 26 and the source region 21
C between_S1Exists. Of the PMOS transistor 6
A capacitor is provided between the gate electrode 29 and the source region 22.
C_S2Exist, and the gate electrode 29 and the drain region 28
Capacitance C between_D2Exists. PMOS
Since the transistors 4 and 6 are always on,
Capacity C_D1, C_S1, C_D2And C _S2Is the largest
It is in a state.

FIG. 3 is an equivalent circuit of the equalize circuit of FIG. 1 focusing on the capacitance described above. As described in FIG. 2, the PMOS transistors 4, 5 and 6 have a parasitic capacitance, and similarly, the NMOS transistors 1, 2 and 3 also have a parasitic capacitance. The NMOS transistor 1 has a capacitance C _D3 between its gate and drain and a capacitance C _S3 between its gate and source.
The NMOS transistor 6 has a capacitance C _S4 between its gate and source and a capacitance C _D4 between its gate and drain. In addition, R _ON shown in FIG.
Is the resistance value of each MOS transistor in the ON state.

According to the equivalent circuit of FIG. 3, the node A and the NMO are
The capacitance between the gate electrode of the S transistor 2 and the capacitance between the node B and the gate electrode of the NMOS transistor 2 are smaller than C _DN and C _SN , respectively. Also, the node A and the PMOS transistor 5
Of the gate electrode of the NMOS transistor 5 and the capacitance between the node B and the gate electrode of the NMOS transistor 5 are smaller than C _DP and C _SP . Therefore,
The positive charges accumulated in the PMOS transistor 5 easily flow to the ground terminal GND, and the negative charges accumulated in the NMOS transistor 2 easily flow to the power supply terminal Vcc. Therefore, the NMOS transistor 2 and PM
It is possible to prevent the potentials of the nodes A and B from rising when the OS5 is turned off. In this way, when the MOS transistors 2 and 5 are turned off, the time required for the potentials of the nodes A and B to converge to the signal level can be shortened.

FIG. 4 is a waveform diagram of each node of the equalize circuit shown in FIG. The difference between the waveform diagram shown in FIG. 4 and the waveform diagram shown in FIG. 11 is that the capacitance C _DN , immediately after the MOS transistors 2 and 5 are turned off,
That is, noise due to C _SN , C _DP and C _SP does not occur. This is because the capacitance between the node A and the gate electrode and the capacitance between the node B and the gate electrode are reduced as described above.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. The equalizing circuit shown in FIG. 5 differs from the equalizing circuit shown in FIG. 1 in that the NMOS transistor 3 and the PMOS transistor 6 are removed.

FIG. 6 is an equivalent circuit of FIG. 5 focusing on the capacitance. Referring to FIG. 6, an ON resistance R _ON and a capacitance C _ON are provided between the node A and the capacitance C _DN.
A filter formed of _D3 and C _S3 is formed. Further, a filter circuit composed of the capacitances C _D1 and C _S1 is formed between the node A and the capacitance C _DP . Thereby, the capacitance between node A and the gate electrodes of MOS transistors 2 and 5 is reduced. As a result, MOS transistors 2 and 5
When the switch is turned off, the accumulated charge easily flows, and the potentials of the node A and the node B can be suppressed from rising.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention. The equalizing circuit shown in FIG. 7 differs from the equalizing circuit shown in FIG. 5 in that MOS transistors 1 and 4 on the node A side of the equalizing circuit shown in FIG. 1 are removed.

In this embodiment, the capacitance between the node B and the gate electrode of the NMOS transistor 2 and the capacitance between the node B and the gate electrode of the PMOS transistor 5 can be reduced. Therefore, as in the case of FIG. 5, when MOS transistors 2 and 5 are turned on, it is possible to prevent the potentials of nodes A and B from rising.

FIG. 8 is a circuit diagram showing a fourth embodiment of the present invention. The equalizing circuit shown in FIG. 8 differs from the equalizing circuit shown in FIG. 1 in that PMOS transistors 4, 5 and 6 are removed. An equivalent circuit focusing on the capacitance of the equalizer circuit is obtained by removing the P-channel side circuit from the equivalent circuit shown in FIG. Therefore, a filter circuit including the capacitances C _D3 and C _S3 and the on-resistance R _ON is formed between the node A and the NMOS transistor 2. Further, a filter circuit including capacitances C _D4 and C _S4 and an on resistance R _ON is formed between the node B and the NMOS transistor 2. Therefore, the capacitance between the node A and the gate electrode of the NMOS transistor 2 and between the node B and the gate electrode of the NMOS transistor 2 are reduced. As a result, it is possible to prevent the potentials of the nodes A and B from rising when the NMOS transistor 2 is turned off.

FIG. 9 shows a fifth embodiment of the present invention.
It is a block diagram of a part of conductor integrated circuit device. Shown in Figure 9
The semiconductor integrated circuit device 100 is provided in a row direction.
Wire line WL₀, WL₁And bit lines provided in the column direction
Provided at the intersection of the pair B, / B and the word line and bit line
Memory cell MC and data input / output line I / O₀, I / O ₁
, Sense amplifier 101, sense amplifier 101 and data
Input / output line I / O₀, I / O₁It is provided between the and
Column selection transistor that turns ON / OFF in response to the selection signal Y
Amplifies read data with transistors TR1 and TR2
Pre-amplifier 103 and the pre-amplifier 103
The equalizing circuit 102 and the preamplifier 103
Data output terminal D by further amplifying the amplified signal
and a main amplifier 104 that outputs the signal to the o.

The preamplifier 103 is a differential amplifier circuit 10.
5, 106 and 107 and an equalizing circuit 108 for equalizing the signal lines connected to the output terminals of the differential amplifier circuits 105 and 106 are provided. As the equalizer circuit 108, the equalizer circuit shown in FIG. 1 is used.

The equalizing circuit 102 has the same structure as the equalizing circuit shown in FIG.

Next, the read operation of the semiconductor memory device shown in FIG. 9 will be described. Before the read operation, the equalize activation signal φ is set to the high level, and the equalize activation signal /
φ goes low. In response, the equalizing circuit 102
Connects the data input / output I / O ₀ and I / O ₁ to make the potentials of the data output line pairs equal. Also equalize circuit 1
Similarly, 08 also equalizes the output lines connected to the output terminals of the differential amplifiers 105 and 106. When the equalize activation signals φ and / φ are inverted after this equalization, in response, the data input / output I / O ₀ and I / O ₁ are separated and the data output lines I / O ₀ and I / O ₁ are separated. The electric potential that appears in is transmitted. In this way, by equalizing the signal lines connected to the data input / output line pair and the output terminals of the differential amplifier circuits 105 and 106, a reference level can be given to the signal transmitted to each signal line. it can.

After being equalized in this way, the
The data is read as follows. That is, in the row direction
Provided word line WL₀, WL₁And provided in the column direction
By activating the pair of bit lines B and / B
Memory cell MC of is selected. Selected memory cell
The data signal read from the MC is the sense amplifier 101.
After being amplified by the column selection transistor TR1 and
And data input / output line I / O through TR2₀, I / O₁To
Transmitted. Data input / output line I / O₀, I / O ₁Communicate to
The generated data signal is amplified by the preamplifier 103.
Then, it is given to the main amplifier 104. Main amplifier
104 is a data signal up to a potential capable of driving an external load
And output the amplified data signal to the data output terminal D
give to o.

In the fifth embodiment described above, it is possible to prevent the potential of the data output line pair from rising when the equalize circuits 102 and 108 transit to the inactive state, so that the data read operation is performed. The speed can be improved.

In the fifth embodiment, only reading has been described, but since the data input / output line pair can be equalized, the data writing speed can be similarly improved.

[0060]

According to the present invention described above, it is possible to reduce the capacitance between the first node and the control terminal of the switch means and between the second node and the control terminal of the switch means. From the ON state of the switch means O
It is possible to prevent the potentials of the first node and the second node from rising when transitioning to the FF state. As a result, the signal transmission speed can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a sectional structural view of the PMOS transistor shown in FIG.

FIG. 3 is an equivalent circuit of FIG. 1 focusing on capacitance.

FIG. 4 is a waveform diagram of each node of the equalize circuit shown in FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is an equivalent circuit of the equalize circuit of FIG. 5 focusing on capacitance.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 9 is a block diagram of a semiconductor memory device showing a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of a conventional equalizing circuit.

11 is a waveform chart of each node of the equalize circuit shown in FIG.

12 is a sectional structural view of the PMOS transistor shown in FIG.

13 is an equivalent circuit of the equalize circuit of FIG. 10 focusing on capacitance.

14 is a cross-sectional structure diagram for explaining a change in capacitance of the PMOS transistor shown in FIG.

FIG. 15 is a graph showing a relationship between gate-source capacitance and gate-drain capacitance of a MOS transistor and a gate voltage.

[Explanation of symbols]

1,2,3 NMOS transistor 4,5,6 PMOS transistor φ, / φ Equalize activation signal C _{D1 to} C _D4 Gate-drain capacitance C _DN Gate-drain capacitance C _{S1 to} C _S4 Gate-source capacitance C _SN , C _SP Gate-source capacitance

Claims (4)

[Claims] 1. A first node and a second node which are required to have the same potential, and a control terminal and a first conduction terminal and a second conduction terminal, respectively.
ON / O in response to the input equalize activation signal
It is connected between the first and second switch means that perform FF, and the first node and the first conduction terminal of the first switch means, and the first node and the first switch terminal are connected to each other.
First capacitance reducing means for reducing capacitance between the first switching means and the control terminal of the second switching means, and the first capacitance reducing means connected between the first node and the first conduction terminal of the second switching means. Node and the second
Second capacitance reducing means for reducing the capacitance between the second switching means and the control terminal of the second switching means, and the second capacitance reducing means connected between the second node and the second conducting terminal of the first switching means. Node and the second
A third capacitance reducing means for reducing a capacitance between the second switch means and a control terminal of the second switch means, and the second capacitance reducing means connected between the second node and the second conductive terminal of the second switch means. Node and the second
And a fourth capacitance reducing means for reducing the capacitance between the control means and the control terminal of the switching means. 2. A first node and a second node which are required to have the same potential, and a control terminal and a first and a second conduction terminal, respectively,
ON / O in response to the input equalize activation signal
Between the first and second switch means for FF, between the first node and the first conduction terminal of the first switch means, and between the second node and the second switch means of the first switch means. First capacitance reducing means connected to either one of a conduction terminal and reducing capacitance between the first or second node and a control terminal of the first switch means; Node and a first conductive terminal of the second switch means, and between the second node and a second conductive terminal of the second switch means, and A semiconductor integrated circuit device including second capacitance reducing means for reducing capacitance between the first or second node and a control terminal of the second switch means. 3. A first and a second node, which are required to have the same potential, a control terminal and a first and a second conduction terminal, and are turned on / off in response to an input equalize activation signal. And a first switching element connected between the first node and a first conductive terminal of the switching means to reduce a capacitance between the first node and a control terminal of the switching means. A second capacitance connected between the second node and the second conduction terminal of the switch means for reducing the capacitance between the second node and the control means of the switch means. A semiconductor integrated circuit device including a capacitance reducing means. 4. A first node and a second node which are required to have the same potential, and an ON / O switch in response to an equalize activation signal inputted.
In response to the equalizing activation signal that is input, the first N-channel MOS transistor that performs FF and ON / O
A first P-channel MOS transistor that performs FF, and a drain electrode connected to the first node,
A source electrode is connected to the drain electrode of the N-channel MOS transistor, and a drain electrode is connected to the second node, the second N-channel MOS transistor having a gate electrode connected to receive a power supply voltage; The first
A source electrode of the N-channel MOS transistor is connected to the source electrode, the gate electrode is connected to receive the power supply voltage, and a drain electrode is connected to the first node, The first
A second P-channel MOS transistor having a source electrode connected to the drain electrode of the P-channel MOS transistor and a gate electrode connected to a ground terminal; and a drain electrode connected to the second node,
A semiconductor integrated circuit device including a third P-channel type MOS transistor having a source electrode connected to the source electrode of the P-channel type MOS transistor and a gate electrode connected to a ground terminal.