GB2261338A - CMOS IF limiter amplifier - Google Patents
CMOS IF limiter amplifier Download PDFInfo
- Publication number
- GB2261338A GB2261338A GB9222906A GB9222906A GB2261338A GB 2261338 A GB2261338 A GB 2261338A GB 9222906 A GB9222906 A GB 9222906A GB 9222906 A GB9222906 A GB 9222906A GB 2261338 A GB2261338 A GB 2261338A
- Authority
- GB
- United Kingdom
- Prior art keywords
- amplifier
- signal
- emitting
- operating current
- amplitude limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/002—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general without controlling loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
A CMOS type IF limiter amplifier allows the operating current to be reduced while maintaining good limiting performance. Transistors M1 and M2 comprise a differential amplifier driven by constant current source Io with the IF signal (voltage VIF) taken as the input. CMOS transistor pairs M3 and M4, M5 and M6, and M7 and M8 comprise current mirror circuits, and are connected to generate the difference between the currents in M1 and M2 to drive an inverter circuit comprised of transistors M9 and M10. Transistors M11 and M12 comprise a second stage inverter, from which a sufficiently limited amplitude IF signal (voltage VOUT) is output. <IMAGE>
Description
AMPLITUDE LIMITING AMPLIFIER
AND METHOD OF AMPLITUDE LIMITING
The present invention relates to an amplitude limiting amplifier formed on a CMOS integrated circuit and to a method of amplitude limiting. The invention is particularly suitable for intermediate frequency (IF) applications.
A conventional IF amplitude limiting amplifier using MOS transistors has an arrangement having a differential amplifier cascaded in multiple stages, as in an IF limiting amplifier using bipolar transistors.
In the above IF amplitude limiting amplifier comprised of CMOS transistors, when a resistance is used as the load of the differential amplifier, it is necessary to increase the value of the constant current source to drive the amplifier, since the CMOS transistors are low in mutal conductance and in driving capability compared with bipolar transistors.
Further, when the load of the differential amplifier is active, the operating current of the amplifier can be reduced since the load value is small. However, since the output amplitude varies substantially in range from the power supply voltage to the voltage of the common source of the differential pair, it is difficult to fix the voltage of the common source, thus making it impossible to achieve good limiting performance. This is another disadvantage of the IF limiting amplifier comprising CMOS transistors.
An object of the present invention is to provide a CMOS type IF amplitude limiting amplifier which allows the operating current to be reduced and good limiting performance to be achieved.
Another object of the present invention is to provide a method of limiting the amplitude which requires a small operating current in an
IF amplitude limiting amplifier formed within a CMOS integrated circuit and which provides good limiting performance.
The present invention provides an amplitude limiting amplifier formed in a CMOS integrated circuit, characterised by comprising means for, when an input signal is entered, emitting an operating current corresponding to said entered signal and means driven by said operating current for emitting a clipped waveform signal which is limited between a predetermined voltage and the ground voltage.
In a preferred embodiment, an amplitude limiting amplifier according to the present invention comprises means for, when an IF signal is entered, emitting an operating current corresponding to the input signal and means driven by the operating current for emitting a rectangular wave signal which is limited between a predetermined voltage and the ground voltage.
Further, the present invention also includes an IF limiting amplifier whose means for emitting the operating current comprises a differential amplifier and a current mirror circuit for generating the difference between the differential currents of the differential amplifiers and whose means driven by the operating current for emitting a rectangular wave signal which is limited between a predetermined voltage and the ground voltage comprises at least one inverter.
The invention also provides a method of limiting the output amplitude of an amplifier formed in a CMOS integrated circuit, characterized in comprising the step of, when an input signal is entered, emitting an operating current corresponding to said input signal, and the step of emitting a clipped waveform signal which is limited between a predetermined voltage and the ground voltage by said operating current.
In a preferred form the invention provides a method of limiting the amplitude of an IF amplitude limiting amplifier comprises the step of, when an IF signal is entered, emitting an operating current corresponding to the input signal, and the step of emitting a rectangular wave signal which is limited between a predetermined voltage and the ground voltage by the operating current.
A specific embodiment of the present invention is described below by way of example only with reference to the accompanying drawing which shows a circuit diagram of a IF amplitude limiting amplifier according to the present invention.
This limiting amplifier comprises CMOS transistors M1 through
M12. CMOS transistors M1 and M2 comprise a differential amplifier driven by constant current source I to which IF signal
0 (voltage VIF) is inputted. Each pair of CMOS transistors M3 and M4,
M5 and M6 and M7 and M8 forms a current mirror circuit to generate a difference between the differential currents of the differential amplifiers comprised of CMOS transistors M1 and M2 to drive an inverter comprised of CMOS transistors M9 and M10. CMOS transistors Mli and M12 comprise a second stage inverter, from which a sufficiently limited IF signal (voltage V0UT) is obtained.
If an equal ratio between gate width W and gate length L is given, drain currents Idl, and Id2 of CMOS transistors M1 and M2 are calculated according to formulae (1) and (2) respectively, constant current source I is calculated according to formula (3),
0 and input voltage (VIF) is calculated according to formula (4).
in formulae (1) and (2) is calculated according to formula (5), where m is electron mobility and Cox is oxidized film capacity per unit gate.
Idl = P(Vcs1 - VT)2 (1) Id2 = ss(VGs2 = VT)2 (2)
Idl + Id2 = 1o (3)
VGS1 - VGS2 = TIF (4) Cox p = n 2 (w/L) (5)
where: VT denotes the threshold voltage, and
VGS1 and VGS2 are the voltage between the source and the gate. In addition, differential current #Id between both drain currents is evaluated according to formula (6).
Therefore, based on formulae (3) and (6) drain current Idl is calculated according to formula (7) and drain current Id2 is calculated according to formula (8).
In short, although difference hId between differential current Idl and Id2 of the differential amplifier comprising CMOS transistors M1 and M2 is generated through the current mirror circuits comprised of CMOS transistors M3 and M4, M5 and M6 and M7 and M8 differential current Aid serves as a common drain current for CMOS transistors M4 and M8, which common drain current drives the inverter comprising CMOS transistors M9 and M10.
Therefore, according to formula (6), when input voltage VIF is positive, then hId is also positive. Accordingly, a current is emitted to the common gate of the first inverter comprised of CMOS transistors M9 and M10, causing the common gate to turn to the high level, so that the output of the first inverter turns to the low level. Consequently, since the common gate is at the low level, output (VOUT) of the second inverter turns to the high level. In other words, it turns to the level of the power supply voltage.
Next, in the opposite case, when input voltage VIF is negative, then AId is also negative.
Accordingly, a current flows from the common gate of the first inverter, causing the common gate to turn the low level, so that the output of the first inverter turns to the high level. Consequently, since the common gate is at the high level, the output (VOUT) of the second inverter turns to the low level. In other words, it turns to the level of the ground voltage.
Since the current gain of each inverter is high, when input voltage VIF is changed and differential current hId is turned from the positive to the negative, or vice versa, output VOUT of the inverter immediately turns from the power supply voltage to the ground voltage, or from the ground voltage to the power supply voltage. In other words, if the driving capability of the second inverter increases in advance, or if the load of the second inverter is small, then it is possible to make the amplitude of the output of the second inverter a rectangular waveform which is limited by the power supply voltage and the ground voltage.
As a result, even if the gate length of the
CMOS transistor or the value of constant current source 10 varies during production, since the limiting operation is decided by the power supply voltage, the performance of the IF amplitude limiting amplifier cannot actually be changed.
In addition, changes in performance are also small even under temperature fluctuations. Further since the CMOS transistors naturally complement as their loads each other, the load of the differential amplifier is also reduced. Still further, since the downstream stage of the amplitude limiting amplifier is the inverter operating at the IF frequency, the circuit current is also reduced.
As many apparently widely different embodiments of this invention may be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.
Claims (9)
1. An amplitude limiting amplifier formed in a CMOS integrated circuit, characterised by comprising means for, when an input signal is entered, emitting an operating current corresponding to said entered signal and means driven by said operating current for emitting a clipped waveform signal which is limited between a predetermined voltage and the ground voltage.
2. An amplitude limiting amplifier as set forth in Claim 1, wherein said means for emitting said operating current comprises a differential amplifier and at least one current mirror circuit for generating the difference between the differential currents of said differential amplifier, and wherein said means driven by said operating current for emitting said rectangular wave signal comprises an inverter circuit.
3. An amplitude limiting amplifier as set forth in Claim 2, wherein the number of said inverter circuits is at least two.
4. An amplitude limiting amplifier as set forth in any preceding claim, being an IF amplifier, adapted to receive an IF input signal.
5. An amplitude limiting amplifier as set forth in any preceding claim adapted to emit a clipped waveform signal having a substantially rectangular waveform.
6. A method of limiting the output amplitude of an amplifier formed in a CMOS integrated circuit, characterized in comprising the steps of, when an input signal is entered, emitting an operating current corresponding to said input signal, and the step of emitting a clipped waveform signal which is limited between a predetermined voltage and the ground voltage by said operating current.
7. A method as set forth in claim 6 wherein the amplifier is an IF amplifier and the input signal is an IF signal.
8. A method as set forth in claim 6 or claim 7 wherein the clipped waveform is a substantially rectangular waveform.
9. An amplitude limiting amplifier or a method of amplitude limiting substantially as herein described with reference to the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3311841A JPH05129849A (en) | 1991-10-30 | 1991-10-30 | If limiter amplifier circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9222906D0 GB9222906D0 (en) | 1992-12-16 |
| GB2261338A true GB2261338A (en) | 1993-05-12 |
| GB2261338B GB2261338B (en) | 1995-07-05 |
Family
ID=18022051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9222906A Expired - Fee Related GB2261338B (en) | 1991-10-30 | 1992-10-30 | Amplitude limiting amplifier and method of amplitude limiting |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH05129849A (en) |
| GB (1) | GB2261338B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3626043B2 (en) | 1999-08-10 | 2005-03-02 | 沖電気工業株式会社 | Operational amplifier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0111230A1 (en) * | 1982-11-26 | 1984-06-20 | Nec Corporation | Voltage comparator circuit |
| US4598215A (en) * | 1983-11-03 | 1986-07-01 | Motorola, Inc. | Wide common mode range analog CMOS voltage comparator |
| EP0240114A1 (en) * | 1986-02-19 | 1987-10-07 | Advanced Micro Devices, Inc. | A comparator for comparing differential input signals and method therefor |
| US4937476A (en) * | 1988-06-16 | 1990-06-26 | Intel Corporation | Self-biased, high-gain differential amplifier with feedback |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61281715A (en) * | 1985-06-07 | 1986-12-12 | Matsushita Electric Ind Co Ltd | Inverter circuit |
| JP2739905B2 (en) * | 1986-05-06 | 1998-04-15 | ローム 株式会社 | Interface circuit |
| JPS6465921A (en) * | 1987-09-04 | 1989-03-13 | Nec Corp | Waveform shaping circuit |
| JPH0529847A (en) * | 1991-07-10 | 1993-02-05 | Fujitsu Ltd | Active load circuit and differential amplifier circuit using the same |
-
1991
- 1991-10-30 JP JP3311841A patent/JPH05129849A/en active Pending
-
1992
- 1992-10-30 GB GB9222906A patent/GB2261338B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0111230A1 (en) * | 1982-11-26 | 1984-06-20 | Nec Corporation | Voltage comparator circuit |
| US4598215A (en) * | 1983-11-03 | 1986-07-01 | Motorola, Inc. | Wide common mode range analog CMOS voltage comparator |
| EP0240114A1 (en) * | 1986-02-19 | 1987-10-07 | Advanced Micro Devices, Inc. | A comparator for comparing differential input signals and method therefor |
| US4937476A (en) * | 1988-06-16 | 1990-06-26 | Intel Corporation | Self-biased, high-gain differential amplifier with feedback |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05129849A (en) | 1993-05-25 |
| GB2261338B (en) | 1995-07-05 |
| GB9222906D0 (en) | 1992-12-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20001030 |