GB2260650A - Insulating substrate for mounting semiconductor devices - Google Patents

Insulating substrate for mounting semiconductor devices Download PDF

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Publication number
GB2260650A
GB2260650A GB9220725A GB9220725A GB2260650A GB 2260650 A GB2260650 A GB 2260650A GB 9220725 A GB9220725 A GB 9220725A GB 9220725 A GB9220725 A GB 9220725A GB 2260650 A GB2260650 A GB 2260650A
Authority
GB
United Kingdom
Prior art keywords
substrate
end surface
metallic foil
foil
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9220725A
Other versions
GB9220725D0 (en
GB2260650B (en
Inventor
Masahide Miyagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of GB9220725D0 publication Critical patent/GB9220725D0/en
Publication of GB2260650A publication Critical patent/GB2260650A/en
Application granted granted Critical
Publication of GB2260650B publication Critical patent/GB2260650B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839Assembly of a flat lead with an insulating support, e.g. for TAB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides

Abstract

An insulating substrate for mounting semiconductor devices thereon comprises: an alumina (Al2O3) insulating member (1) having first and second opposite flat surfaces (5, 6) terminating at an end surface (4) of the member (1), a first sheet (2) of metallic foil disposed on the first surface (5) having edges terminating first predetermined distances (A) inwardly of said end surface (4), a second sheet (3) of metallic foil disposed on the second surface (6) having edges terminating second predetermined distances (B) inwardly of the end surface (4), said first and second predetermined distance increasing the distance between the edges of the first and second sheets (2, 3) of metallic foil by an amount greater than the thickness of the insulating member (1) and the difference between the first and second predetermined distances being substantially no greater than 0.5 mm to balance thermal stress on the opposite flat surfaces of the insulating member (1). The foils may have an overlapping pattern. <IMAGE>

Description

2 2 S f.) 5 'Y 3 INSULATING SUBSTRATE FOR MOUNTING SEMICONDUCTOR DEVICES
The present invention relates to an alumina insulating substrate, to which copper foil is applied, for mounting semiconductor circuit elements such as an inverter of a motor control or air conditioner, or a power module used in NC control, for example.
Electronic technology has advanced remarkably during the past decade, with rapidly increasing levels of integration and decreasing cost. The primary reason for this trend is that semiconductors have become the primary electronic device. The trend in the area of power modules is to decrease electronic component size and to include more circuitry in a single package. To achieve this goal, circuit elements are mounted on an insulating substrate such that individual circuit elements are electronically isolated from one another. Metal foil is applied to the f lat surfaces of the insulating substrate to which electronic components may be soldered. The substrate is usually made of a ceramic material, such as alumina (Al 2033. However, as electronic devices have become smaller and more powerful, substrate material having higher thermal conductivity for improved heat dissioation is required.
The thermal conductivity of Al 2 0 3 is 17 W m.k The thermal conductivity of aluminum nitride (AlN) is about 5 times 1 - greater, 80-140 W /[ m.k]. As a result, an AlN substrate offers higher heat dissipation than an Al 2 0 3 substrate. However, due to the high cost of AlN, its use has been limited to special applications.
one method for increasing the heat dissipation of an Al 2 0 3 substrate is to decrease the substrate's thickness. However, as the material's thickness is decreased, its stress resistance also decreases. For example, a conventional Al 2 0 3 substrate 0.635 mm thick has a bending strength of 8 kg. If the substrate's thickness is reduced to 0.275 mm, the bending strength is only 2 kg, a reduction of 75%. In such a substrate, there is a high probability of cracks developing over time as a result of thermal stress in the assembly.
The present invention has been made in view of the above circumstances and has as an object to provide an insulating substrate for mounting semiconductor devices in which the insulating substrate is made of inexpensive Al 2 0 3' whose thermal conductivity is improved by decreasing the ceramic substrate's thickness and to prevent crack formation caused by thermal stress from the heating and cooling of the semiconductor devices.
Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the
W instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the insulating substrate for mounting semiconductor devices, of this invention comprises an alumina (A1203) insulating member having f irst and second opposite flat surfaces terminating at an end surface of the member, a first sheet of metallic foil disposed on the first flat surface having edges terminating first predetermined distances back from the end surface, a second sheet of metallic foil disposed on the second flat surface having edges terminating second predetermined distances back from the end surface, the difference between the first and second corresponding predetermined distances being substantially no greater than 0.5 mm.
The accompanying drawings, which are incorporated in and constitute a part of this specification illustrate an embodiment of the invention and, together with the description, serve to explain the objects, advantages and principles of the invention. In the drawings,
Fig. I is a fragmentary cross-sectional view of an insulating substrate in accordance with an embodiment of the present invention; Fig. 2 is a graph of the substrate crack generation ratio as a function of the absolute value of the distance A - B between edges of the Cu foil; Fig. 3 is a graph of the calculated stress on both flat surfaces of the insulating substrate as a function of the value A - B; Fig. 4 (a) is a plan view showing an example of a Cu foil pattern on the first flat surface of the ceramic substrate; and Fig. 4 (b) is a plan view showing an example of a Cu foil pattern on the second flat surface of the ceramic substrate.
The purpose of the invention is to prevent crack formation in a Cucovered A1203 substrate used for mounting semiconductor devices, wherein the thickness of the substrate is decreased to improve the substrate's thermal conductivity.
To obtain adequate electrical isolation between two Cu foil sheets applied to opposite sides of a 0.26-0.29 mm thick alumina plate, the foil edges must not be applied up to the end surface or edge of the alumina plate. If the difference in distance, A - B, between the edges of two Cu foil sheets 2 and 3 and end surface 4 of alumina plate 1 is limited to a range of 0.5 mm or less, then the thermal stress on both flat surfaces 5 and 6 of the plate is balanced, and crack formation is prevented. Further, the balance of stress is improved if the Cu foil patterns applied to both flat surfaces 5 and 6 are similar and overlap on the top and bottom of the substrate when viewing the substrate in a vertical direction indicated by arrow 8 of Figure 1.
- 4 To realize the above-mentioned object the present invention provides a semiconductor device, wherein a semiconductor element is mounted on a surface of a flat alumina insulating substrate material, to which copper foil is applied, characterized in that the absolute value in the differences of distances between the edges of Cu f oil -on both sides and the end surf ace of the alumina substrate is 0.5 nun or less.
Further, the Cu foil applied to both flat surfaces of the Al 2 0 3 substrate advantageously has a pattern that overlaps up and down when viewed in a vertical direction shown by arrow 8 in Figure 1. Additionally, the thickness of the Al 20 3 plate is advantageously 0.26 to 0.29 mm.
When Cu foils applied to both sides of an insulating substrate extend up to the end surface of the Al 2 0 3 plate, the separation between the two foil sheets is merely the thickness of the Al 20 3 plate, and a breakdown voltage can not be obtained. Thus, to achieve good electrical isolation, the Cu foil sheets are not applied up to the end surface of the Al 2 0 3 substrate. Rather, as shown in Figure 1, Cu foils 2 and 3 are applied to positions back or inwardly from end surface 4 of Al 2 0 3 plate 1, by the distances A and B, respectively.
When positions of the cracks are detected that are generated by the heating history of the assembly it was found that the crack generated in the Al 2 0 3 plate was below the Cu foil whose edge is farther back from the end surface of the Al 2 0 3 plate 1. The reason for this is that stress in the ceramic varies as a function of temperature. When the distance between the edge of the copper foil on one side of the Al 2 0 3 substrate and the substrate end surface differs from the distance between the edge of the Cu foil on the other side of the Al 2 0 3 substrate and the substrate end surface, the stress is concentrated at the edge of the Cu foil farther back from the Al 2 0 3 substrate end surface.
The tensile stress in a ceramic which is generated in both surfaces of the Al 2 0 3 during the cooling time in the assembly heat history was calculated using the finite element method. The dependency of the stress value in a certain physical constant due to the technically calculated value, on the value of A - B was obtained. The thickness of Al 2 0 3 plate was defined as 0.27 mm and the thickness of Cu foil was defined as 0.25 mm. Stress as a function of the value of A - B was determined and the result is shown in Figure 3. The line 31 shows the tensile stress of Cu foil 2 on the Al 203 plate 1; the broken line 32 shows the tensile stress of Cu foil 3 on the Al 203 plate 1. As the calculations indicate, the tensile stress is greater the farther the foil edge is from the end surface of Al 203 1. That is, as shown by the line 31, the tensile stress of the Cu foil 2, which affects the Al 203 plate 1 during cooling time, increases as the value of A - B becomes large and positive, and it decreases as the value becomes large and negative. Conversely, as shown by the line 32, the tensile stress of the Cu foil 3, which affects the A1203 plate 1, decreases as the value of A - B becomes large and positive, and it increases as the value becomes large and negative. From both results, a suitable range for the absolute value of the difference A - B can be found in which cracks will not form in the Al 203 substrate. Furthermore, when A - B = 0 and the top and bottom Cu foil patterns on opposite flat surfaces overlap when viewed from a vertical direction corresponding to arrow 8 of Figure 1, the stresses of both Cu foils are balanced, with the result that crack formation is significantly reduced.
A power module was constructed using a ceramic insulating substrate in which 0.25 mm thick Cu foils 2 and 3 were applied to a 0.275 mm thick A1203 plate 1. When the value R = A - B is changed while changing methods of applying Cu foils 2 and 3, cracks were generated in the Al 2 0 3 plate after heating the assembly. Figure 2 illustrates the relationship between the crack generation ratio and R. As apparent from the drawing, when the value of R is 0.5 mm or less, cracks do not form. When the value of R is greater than 0.5 mm, the generation of cracks sharply increases. Thus, when insulating substrates having a value of R < 0.5 mm are prepared, power modules can be produced in which substrate defects do not result.
Figure 4 shows an example of a top plan view of the first and second flat surfaces of an insulating substrate according to the present invention. The patterns of the Cu foils 2 and 3 applied to the Al 203 plate 1 have line symmetry form and overlap when viewed from the vertical direction with respect to the surface of the substrate.
The standard practice has been to pattern the Cu foil 2 on the side of the substrate on which circuit elements are mounted, while not patterning the Cu foil 3 on the other side of the substrate which is soldered to a Cu heat sink. However, in the present invention, the Cu foil is patterned on both sides of the substrate, resulting in balanced thermal stress. The Cu foil 3 as well as the soldered layer thereunder are used to dissipate heat from a circuit element to the heat sink substrate. Nevertheless, since the Cu foil 3 always exists just under the element which is mounted on the Cu foil 2, there is no effect on the radiation of heat.
According to the present invention, when the thickness of an insulating substrate on which semiconductor elements are mounted is decreased to improve heat transfer, the stress produced by both Cu foil sheets, which is transferred to the Al 2 0 3 plate, is balanced by.setting the absolute value of the difference in distances between the edge of Cu foil and the end surface of the Al 2 0 3 substrate to 0.5 mm or less. Thus, breakage of the Al 203 plate is decreased, with the result that the high integration and miniaturization can be realized. Further, an improved stress balance can be obtained by overlapping the patterned Cu foils applied to both flat surfaces of the insulating substrate.
The foregoing description of preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be - 8 1 acquired from practice of the invention. The embodiment was chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.
- 9

Claims (6)

1. An insulating substrate for mounting semiconductor devices thereon, comprising: an alumina (A1203) insulating member having f irst and second opposite flat surfaces terminating at an end surface of the member, a first sheet of metallic foil disposed on said first flat surface having edges terminating first predetermined distances inwardly of said end surface, a second sheet of metallic foil disposed on said second flat surface having edges terminating second predetermined distances inwardly of said end surface, said first and second predetermined distance increasing the distance between the edges of the first and second sheet of metallic foil greater than the thickness of the insulating member, the difference between said first and second predetermined distances being substantially no greater than 0.5 mm to balance thermal stress on the opposite flat surfaces of the insulating member.
2. A substrate as claimed in Claim 1, wherein said first and second sheets of metallic foil have an overlapping pattern configuration when viewed through the opposite flat surfaces of the member.
3. A substrate as claimed in Claim 1 or Claim 2, wherein the metallic foil is copper (Cu).
4. A substrate as claimed in any one of Claims 1 to 3, wherein the alumina member is in the range of approximately of 0.26 to 0.29 millimeters in thickness.
5. A substrate as claimed in any one of Claims 1 to 4, wherein the metallic foil is 0.25 millimeters in thickness.
6. An insulating substrate for mounting semiconductor devices thereon substantially as hereinbefore described with reference to the accompanying drawings.
- 11
GB9220725A 1991-10-14 1992-10-01 Insulating substrate for mounting semiconductor devices Expired - Lifetime GB2260650B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26417491 1991-10-14
JP4010422A JPH05166969A (en) 1991-10-14 1992-01-24 Semiconductor device

Publications (3)

Publication Number Publication Date
GB9220725D0 GB9220725D0 (en) 1992-11-11
GB2260650A true GB2260650A (en) 1993-04-21
GB2260650B GB2260650B (en) 1995-03-22

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GB9220725A Expired - Lifetime GB2260650B (en) 1991-10-14 1992-10-01 Insulating substrate for mounting semiconductor devices

Country Status (3)

Country Link
JP (1) JPH05166969A (en)
DE (1) DE4234506A1 (en)
GB (1) GB2260650B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0670667A1 (en) * 1994-02-24 1995-09-06 Plessey Semiconductors Limited Direct copper bonded substrates
EP0723292A2 (en) * 1995-01-19 1996-07-24 Fuji Electric Co. Ltd. Semiconductor device
US7075103B2 (en) 2003-12-19 2006-07-11 General Electric Company Multilayer device and method of making
EP2315284A3 (en) * 2009-10-21 2013-03-27 Toshiba Lighting & Technology Corporation Light-Emitting apparatus and luminaire

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JP3316714B2 (en) * 1994-05-31 2002-08-19 三菱電機株式会社 Semiconductor device
DE4421319A1 (en) * 1994-06-17 1995-12-21 Abb Management Ag Low-inductance power semiconductor module
RU2190284C2 (en) 1998-07-07 2002-09-27 Закрытое акционерное общество "Техно-ТМ" Two-sided electronic device
JP4867793B2 (en) 2007-05-25 2012-02-01 株式会社豊田自動織機 Semiconductor device
JP2015035501A (en) * 2013-08-09 2015-02-19 日本特殊陶業株式会社 Heat radiation module and semiconductor module
JP6638284B2 (en) * 2015-09-28 2020-01-29 三菱マテリアル株式会社 Substrate for power module with heat sink and power module
JP6584928B2 (en) * 2015-11-16 2019-10-02 住友電工デバイス・イノベーション株式会社 Electronic equipment

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
EP0670667A1 (en) * 1994-02-24 1995-09-06 Plessey Semiconductors Limited Direct copper bonded substrates
EP0723292A2 (en) * 1995-01-19 1996-07-24 Fuji Electric Co. Ltd. Semiconductor device
EP0723292A3 (en) * 1995-01-19 1997-07-30 Fuji Electric Co Ltd Semiconductor device
US7075103B2 (en) 2003-12-19 2006-07-11 General Electric Company Multilayer device and method of making
US7595105B2 (en) 2003-12-19 2009-09-29 General Electric Company Multilayer device and method of making
EP2315284A3 (en) * 2009-10-21 2013-03-27 Toshiba Lighting & Technology Corporation Light-Emitting apparatus and luminaire

Also Published As

Publication number Publication date
GB9220725D0 (en) 1992-11-11
GB2260650B (en) 1995-03-22
JPH05166969A (en) 1993-07-02
DE4234506A1 (en) 1993-04-15

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