GB2258943A - Noise suppression in integrated circuit device - Google Patents

Noise suppression in integrated circuit device Download PDF

Info

Publication number
GB2258943A
GB2258943A GB9204460A GB9204460A GB2258943A GB 2258943 A GB2258943 A GB 2258943A GB 9204460 A GB9204460 A GB 9204460A GB 9204460 A GB9204460 A GB 9204460A GB 2258943 A GB2258943 A GB 2258943A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
substrate
power
circuit device
noises
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9204460A
Other versions
GB9204460D0 (en
Inventor
Byoung-Yun Kim
Yong-Bo Park
Deok Min Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9204460D0 publication Critical patent/GB9204460D0/en
Publication of GB2258943A publication Critical patent/GB2258943A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B29/00—Generation of noise currents and voltages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/005—Reducing noise, e.g. humm, from the supply
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Description

NOISE SUPPRESSION IN INTEGRATED CIRCUIT DEVICE The present invention relates to suppressing noise in a semiconductor integrated circuit device, and more particularly although not exclusively to an integrated circuit device with power noises suppressed, which may be induced on a power line during high-speed operation of the integrated circuit device.
Generally, the operation of an integrated circuit is performed by a continuous charging and discharging of an electric charge, and the charging and discharging operations in the integrated circuit are implemented within a range of capability of supplying and receiving electric charges to and from a power supply terminal. That is, an abrupt operation of the circuit means a high-speed travel of the charges supplied to and/or received from the power supply terminal, and if a recharging operation is, however, not rapidly performed from a power source, the voltage level of the power supply terminal losing the charges may become low. Meanwhile, if the power supply terminal receiving the charges is not rapidly redischarged up to the power source, the voltage level thereof becomes high.Thus, power noises may vary sensitively according to peripheral wiring capacity, inductance or resistance, etc., and lead to malfunction of the integrated circuit, such as a memory device, or interruption of high-speed operation.
Figure 1 of the accompanying diagrammatic drawings is a diagram showing an arrangement of a conventional power line. It is constructed such that a power line is supplied to each circuit portion along branch lines. In this case, power noises generated in a specific circuit portion are firstly filtered through a capacitor buried in corresponding branch lines. Thus, the degree that the power noises are spread to the main lines and the effect upon the other branch lines can be reduced. However, as high-speed operation in the integrated circuit is carried out, in the case that each circuit device disposed in the interior of a chip generates multiple power noises simultaneously, large noises may be generated in the main power lines. Moreover, noises generated in the main line may become a noise source supplying the noises to each branch line.In order to filter the above power noises, a method for forming a capacitor over the top surface of a semiconductor substrate has been proposed. However, this method has a disadvantage that an area for arranging the capacitor is insufficient, due to an internal circuit formed on the surface of the substrate. Furthermore, during the design of the integrated circuit, a malfunction caused by an unexpected signal defect may be generated.
Preferred embodiments of the present invention aim to provide an integrated circuit device for preventing a phenomenon that power noises are reversely spread on each branch line by effectively receiving the power noises induced to a main line from each power branch line.
It is another aim to provide an integrated circuit device for reducing power noises irrespective of location and interference.
In accordance with an aspect of the present invention, on the rear side of a semiconductor substrate having an integrated circuit formed thereon, is coated a thin film having a high permittivity, to thus form large capacity capacitance between a package lead frame and the substrate. Thereafter, power having a polarity opposite to that of a power supply applied to the substrate is connected to the lead frame so as to form a decoupling capacitor between power terminals of a chip.
According to one aspect of the present invention, there is provided an integrated circuit device having means for suppressing power noises, which means comprises a dielectric film formed on the rear side of a semiconductor substrate having an integrated circuit formed thereon, thereby to form a capacitor in association with said substrate, said dielectric film and a package lead frame.
Preferably, said package lead frame has a polarity opposite to a polarity of a voltage applied to said substrate.
According to a further aspect of the present invention, there is provided an integrated circuit device having means for suppressing power noises, which means comprises a thin film formed on the rear side of a semiconductor substrate having an integrated circuit formed thereon, thereby to form a given electric component.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 and 3 of the accompanying diagrammatic drawings, in which: Figure 2 is a schematic diagram showing an example of an arrangement of a power line in an integrated device, according to the present invention; and Figure 3 is an equivalent circuit diagram of Figure 2.
Referring to Figure 2, on the rear side of an n-type semiconductor substrate 10 having an integrated circuit device formed thereon, a thin film 12 having a high permittivity is coated, to thus form large capacity capacitance CB between a package lead frame 14 and the substrate 10. Then, power having an opposite polarity of a power supply terminal applied to the substrate 10 is connected to the lead frame 14 so as to form a decoupling capacitor between power supply terminals of a chip on the rear side of a semiconductor substrate.
In more detail, over the top surface of the semiconductor substrate 10, where a semiconductor device is formed, a BPSG (Boro-Phospho Silicate Glass) layer for flattening a metal layer is formed, and the rear of the substrate is ground for a package. Next, a nitride layer having a thickness of 40A -2000A is deposited on the rear side of the substrate by a LPCVD (low pressure chemical vapor deposition) method. Thereafter, an ONO (Oxide Nitride Oxide) layer is formed thereon by using a reflowing temperature during reflowing the BPSG layer. In this case, the permittivity of the nitride layer and the oxide layer may be preferably 7.5 and 3.9, respectively. Then metal and passivation processes, etc., are performed over the top surface of the substrate and then, the substrate is cut into a predetermined unit.
Following this, the chip is mounted on the lead frame. In Figure 2, RSUB denotes the resistance of the substrate 10, and C1, R1 the capacitance and resistance respectively of the supply lines.
Figure 3 shows an equivalent diagram of Figure 2. A rear capacitor 16 (=CB) is formed by the dielectric film 12 between a power supply terminal 32 connected to the substrate 10 and a ground terminal 34 connected to the lead frame 14. A specific resistance 18 (=sub) have a few tens of mQ exists naturally between the power supply terminal 32 and a lower side of the substrate, and a capacitor 20 (=C1) including a junction capacitance, line capacitance and gate capacitance is formed between the power supply 32 terminal and the ground terminal 34 on the surface of an integrated circuit 15 formed on the substrate 10.Resistor 22 (=R1) is connected between the capacitor 20 and a power supply terminal 31 or a ground terminal 33, and first and second inductors 24 and 26 formed by a bonding wire are used to connect the power supply terminal and the ground terminal to the package lead frame 14, respectively. Since the first inductor 24 suppresses the increase of the amount of charge, it plays a role in preventing the supply of the instantaneously necessary charge from the power supply terminal. As a result, the integrated circuit 15 comes to use the stored charge in the internal power line. However, if the storage capacity of the internal power line is not sufficient, the voltage of the internal power supply terminal 31 tends to become abruptly low so that the operation of the chip becomes unstable.
However, since the rear capacitor 16 can directly supply the charge stored therein to the internal power line, the momentary power noises of the integrated circuit can be removed and the level of the stable power voltage can be maintained. The amount of charge q stored in the rear capacitor 16 is as follows: q = cv = ed xv As shown in this expression, provided that the larger area s of the rear capacitor, smaller thickness d and larger permittivity e are provided, the chip can store a greater amount of charges and also become stabilized in operation.
In the illustrated embodiment, a description is given only for an n-type substrate. However, a p-type substrate may alternatively be applied. In this case, the p-type substrate should be connected to the ground terminal through the resistor and the power supply terminal connected to the lead frame positioned opposite to the rear insulation layer. Thus, the large capacity capacitance can be generated by forming the rear insulation layer between the ground terminal and the power supply terminal. Moreover, instead of the capacitor, another electric component may also be formed on the rear side of the substrate by forming a predetermined thin film.That is, by forming a high resistance material on the rear side of the substrate or a thin film of a second conductivity type on the rear side of the substrate having a first conductivity type, a resistor or a diode can be formed, respectively.
As described above, in an integrated circuit device for suppressing power noises, high capacitance can be formed between the package lead frame and the substrate by forming a dielectric film on a rear side of the substrate having an integrated circuit formed thereon. Consequently, the power noises are reduced and since the capacity adjustment of a rear capacitor is unrestricted, the internal power design in a chip, considering external environment, is easy. Further, in order to remove the power noises, since there is no necessity for installing an additional capacitor on the top surface of a substrate, the design area of the integrated circuit can be reduced.
While a preferred embodiment of the present invention has been particularly shown and described, it will be understood by those skilled in the art that in the foregoing, changes in form and details may be made without departing from the spirit and scope of the present invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (4)

CLAIMS:
1. An integrated circuit device having means for suppressing power noises, which means comprises a dielectric film formed on the rear side of a semiconductor substrate having an integrated circuit formed thereon, thereby to form a capacitor in association with said substrate, said dielectric film and a package lead frame.
2. A device as claimed in claim 1, wherein said package lead frame has a polarity opposite to a polarity of a voltage applied to said substrate.
3. An integrated circuit device having means for suppressing power noises, which means comprises a thin film formed on the rear side of a semiconductor substrate having an integrated circuit formed thereon, thereby to form a given electric component.
4. An integrated circuit device substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
GB9204460A 1991-08-19 1992-03-02 Noise suppression in integrated circuit device Withdrawn GB2258943A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910014266A KR930005334A (en) 1991-08-19 1991-08-19 Integrated Circuit for Suppressing Supply Noise

Publications (2)

Publication Number Publication Date
GB9204460D0 GB9204460D0 (en) 1992-04-15
GB2258943A true GB2258943A (en) 1993-02-24

Family

ID=19318748

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9204460A Withdrawn GB2258943A (en) 1991-08-19 1992-03-02 Noise suppression in integrated circuit device

Country Status (7)

Country Link
JP (1) JPH0547808A (en)
KR (1) KR930005334A (en)
DE (1) DE4206278A1 (en)
FR (1) FR2680602A1 (en)
GB (1) GB2258943A (en)
IT (1) IT1254810B (en)
TW (1) TW200631B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997012398A1 (en) * 1995-09-29 1997-04-03 Analog Devices, Inc. Integrated circuit and supply decoupling capacitor therefor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173339A (en) 2005-12-20 2007-07-05 Nec Electronics Corp Semiconductor circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1287110A (en) * 1968-12-20 1972-08-31 Philips Electronic Associated Semiconductor devices
GB2133929A (en) * 1982-12-27 1984-08-01 Western Electric Co Semiconductor integrated circuit
EP0230154A2 (en) * 1986-01-08 1987-07-29 Advanced Micro Devices, Inc. Integrated circuit structures comprising current busses
JPH02224367A (en) * 1989-02-27 1990-09-06 Ricoh Co Ltd Semiconductor device provided with capacitor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164246A (en) * 1982-03-24 1983-09-29 Nec Corp Semiconductor device
JPS6167231A (en) * 1984-09-10 1986-04-07 Matsushita Electric Ind Co Ltd Semiconductor device
JPS61108160A (en) * 1984-11-01 1986-05-26 Nec Corp Semiconductor device with built-in capacitor and manufacture thereof
JP2674073B2 (en) * 1988-03-17 1997-11-05 松下電器産業株式会社 Integrated circuit device
JPH01305543A (en) * 1988-06-03 1989-12-08 New Japan Radio Co Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1287110A (en) * 1968-12-20 1972-08-31 Philips Electronic Associated Semiconductor devices
GB2133929A (en) * 1982-12-27 1984-08-01 Western Electric Co Semiconductor integrated circuit
EP0230154A2 (en) * 1986-01-08 1987-07-29 Advanced Micro Devices, Inc. Integrated circuit structures comprising current busses
JPH02224367A (en) * 1989-02-27 1990-09-06 Ricoh Co Ltd Semiconductor device provided with capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997012398A1 (en) * 1995-09-29 1997-04-03 Analog Devices, Inc. Integrated circuit and supply decoupling capacitor therefor
US5895966A (en) * 1995-09-29 1999-04-20 Analog Devices, Inc. Integrated circuit and supply decoupling capacitor therefor

Also Published As

Publication number Publication date
KR930005334A (en) 1993-03-23
FR2680602A1 (en) 1993-02-26
ITMI920375A1 (en) 1993-08-20
GB9204460D0 (en) 1992-04-15
DE4206278A1 (en) 1993-02-25
IT1254810B (en) 1995-10-11
TW200631B (en) 1993-02-21
JPH0547808A (en) 1993-02-26
ITMI920375A0 (en) 1992-02-20

Similar Documents

Publication Publication Date Title
KR100399447B1 (en) Method for Direct Attachment of an On-Chip Bypass Capacitor to an Integrated Circuit
US7859825B2 (en) High yield, high density on-chip capacitor design
US7358555B2 (en) Semiconductor device
EP0795201B1 (en) Method of formation of a capacitor for an integrated circuit and a method of adding on-chip capacitors to an integrated circuit
US7994606B2 (en) De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits
US5739576A (en) Integrated chip multilayer decoupling capacitors
US5420449A (en) Capacitor for a semiconductor device
US5574621A (en) Integrated circuit capacitor having a conductive trench
EP0874393A3 (en) Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby
WO2001078093A3 (en) Distributed capacitor
EP1189262A3 (en) Semiconductor device comprising a capacitor and method of manufacturing the same
USRE39124E1 (en) Integrated circuit having capacitive elements
US6259149B1 (en) Fully isolated thin-film trench capacitor
JPH0552671B2 (en)
US6198153B1 (en) Capacitors with silicized polysilicon shielding in digital CMOS process
JP2000260939A (en) High-frequency circuit device
JP3467445B2 (en) Semiconductor device and manufacturing method thereof
US7355265B2 (en) Semiconductor integrated circuit
EP1020895A3 (en) Integrated circuit capacitor
GB2258943A (en) Noise suppression in integrated circuit device
US6362523B1 (en) Semiconductor device
US6744129B2 (en) Integrated ground shield
US6171899B1 (en) Method for fabricating a capacitor
US5808343A (en) Input structure for digital integrated circuits
US20020040997A1 (en) Semiconductor device

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)