TW200631B - - Google Patents

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Publication number
TW200631B
TW200631B TW081100147A TW81100147A TW200631B TW 200631 B TW200631 B TW 200631B TW 081100147 A TW081100147 A TW 081100147A TW 81100147 A TW81100147 A TW 81100147A TW 200631 B TW200631 B TW 200631B
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TW
Taiwan
Prior art keywords
power supply
substrate
integrated circuit
capacitor
lead frame
Prior art date
Application number
TW081100147A
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Chinese (zh)
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
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Publication of TW200631B publication Critical patent/TW200631B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B29/00—Generation of noise currents and voltages
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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Description

.1 ¾ β Λ οow M濟郎屮央榀準灼A工消if合作杜印3i 玉、發叫纪，叫（1 ) 發明背泶 本發明係關於半導體横體電路裝置之電源雜訊的抑制 装置，尤其是有關於（雖然不是專用於）能抑制電源雜訊 的積體電路裝置，該電源雜訊係在稻體電路裝置做高速度 操作時，在電源線上所産生。 積體電路之操作一般係藉電荷之連績充電及放電來實 施，而積體電路內之充電及放電操作係藉供應電荷到電源 供應端或由電源供應端接收電荷之能力來完成。易言之’ 電路之突然操作係供應電荷到電源供應端及/或由電源供 應端接收電荷的高速動程，然而，如果再充電操作不由電 源快速來完成，則失去電荷之電源供應端，其電壓位準就 會變低。同時，獲得電荷之電源供應端如果不快速再放電 到電源，則其電壓位準會變高。因此，電源雜訊會依隨週 邊配線之電容、電感或電阻等敏感改變，且引生像記憶裝 置之類的積體電路的障碍，或是高速操作的中斷。 圖1是習知電源線的布置圖，其如此構造使得電源線 可沿着支線而供應到每一電路部分。在本例中，特殊電路 部份所產生的電源雜訊首先被埋設在對應支線上的電容器 所過濾。因此，可減少電源雜訊分散到主線之程度及對其 它支線的影響。然而，在實施積體電路之高速操作時，如 果設置在晶片內部的每一電路同時產生多重的電源雜訊， 則大雜訊會在主電源線上産生。此外*主線上所産生的雜 訊會成爲將雜訊供給到每一支線的雜訊源。爲了過濾上述 之®源雜訊，有人建議一方法用來在半導體基板之頂面上 ik m ;ϊ 而 之 注 Λ 木 五、發明説明（2) 形成一電容器。然 基板表面上之內部 此外，在設計積體 所引生的障碍。 因此，本發明 來有效地接收由每 避免電源雜訊回散 本發明之另一 少電源雜訊而與地 依據本發明之 背後塗上一層高介 板間形成大容量之 極性相反的電源被 間形成一去耦電容 ^00〇31 A (i li (i 而，該方法有其缺點，即，由於形成在 電路，使得設置電容器之面積不夠大。 電路時，也會産生由於意外的信號缺點 發明槪述 之一目的是要提供一積體電路裝置，用 —電源支線引生到主線的電源雜訊，而 到每一支線上。 目的是要提供一積體電路裝置，用來減 點與干擾無關。 特徵*在具有積體電路之半導體基板的 電係數之薄膜，藉此在封裝引線框與基 電容。其後，極性與施加到基板之電源 連接到引線框，以便在晶片之電源端之 器。 附圖簡述 茲將參考附圖來詳述本發明之較佳實施例*以使本發 明之上述目的及其它優點會變得更淸楚。在附圖中： 圖1是顯示習知電源線之布置圖； 圖2是顯示依據本發明的電源線布置示意圖；及 圖3是圖2之等效圖。 較佳實施例之詳述 茲請參閱圖2，在具有積體電路裝置形成其上的半導 置i板10的背面，塗上一層具高介電係數的薄膜，藉此在 its 先 W! ifi if it * 項 線 3〇〇6於.1 ¾ β Λ οow M Ji Lang Yi Yang Zhuo Zhuo A Gong Xiao if cooperation Du Yin 3i jade, call Ji, called (1) The invention is related to the suppression of the power supply noise of the semiconductor horizontal body circuit device, In particular, it concerns (although not exclusively) integrated circuit devices capable of suppressing power noise, which are generated on power lines when rice circuit devices are operated at high speeds. The operation of the integrated circuit is generally carried out by the continuous charge and discharge of the electric charge, and the charging and discharging operation in the integrated circuit is accomplished by the ability to supply the electric charge to or receive the electric charge from the power supply end. It is easy to say that the sudden operation of the circuit is the high-speed movement of supplying charge to the power supply terminal and / or receiving the charge from the power supply terminal. The voltage level will become lower. At the same time, if the power supply terminal that obtains the charge does not quickly discharge to the power supply, its voltage level will become higher. Therefore, power supply noise may change sensitively with the capacitance, inductance, or resistance of the surrounding wiring, and may cause obstacles to integrated circuits such as memory devices, or interruption of high-speed operation. FIG. 1 is a layout diagram of a conventional power supply line, which is constructed so that the power supply line can be supplied to each circuit portion along the branch line. In this example, the power noise generated by the special circuit part is first filtered by the capacitor buried in the corresponding branch line. Therefore, the power noise can be reduced to the main line and the impact on other branches. However, when implementing high-speed operation of an integrated circuit, if each circuit provided inside the chip generates multiple power noises at the same time, large noises will be generated on the main power line. In addition, the noise generated on the main line will become the noise source that supplies noise to each branch. In order to filter the above-mentioned ® source noise, it was suggested that a method be used on the top surface of the semiconductor substrate ik m; ϊ and note Λ wood 5. Description of the invention (2) Form a capacitor. However, the internals on the surface of the substrate are also obstacles arising from the design integration. Therefore, the present invention can effectively receive the power supply between the opposite polarities of the present invention by avoiding the power noise to dissipate another small power noise of the present invention and coating a layer of high-dielectric board between the ground according to the present invention. Forming a decoupling capacitor ^ 00〇31 A (i li (i However, this method has its disadvantages, that is, because it is formed in the circuit, the area where the capacitor is provided is not large enough. When the circuit is also produced due to unexpected signal shortcomings One of the purposes of the description is to provide an integrated circuit device, which uses the power supply branch line to lead the power noise to the main line, and to each branch line. The purpose is to provide an integrated circuit device for reducing point and interference Irrelevant. Features * In the thin film of the electrical coefficient of the semiconductor substrate with integrated circuit, thereby encapsulating the lead frame and the base capacitor. Thereafter, the polarity and the power applied to the substrate are connected to the lead frame so that Brief Description of the Drawings The preferred embodiments of the present invention will be described in detail with reference to the drawings so that the above objects and other advantages of the present invention will become more apparent. In the drawings: FIG. 1 shows Know the layout of the power cord; Figure 2 is a schematic diagram showing the layout of the power cord according to the present invention; and Figure 3 is an equivalent diagram of Figure 2. For a detailed description of the preferred embodiment, please refer to Figure 2, in the integrated circuit device The back side of the semi-conducting i-plate 10 formed thereon is coated with a thin film having a high dielectric constant, so that before it's W! Ifi if it * Item line 3〇〇6

Λ ίί \\ (} 五m叫（3 ) ( 81年9月修正） "Κ木玎) 封裝引線框14及基板10之間形成一大容量之電容。然後， 極性與施加到基板丨0之電源供應端之極性相反的電源被連 接到引線框14，以便苍半導體基板之背面，晶片之電源供 應端之間形成一去耦電容器。詳言之，在形成有半導體装 置之半導體基板的頂面上，形成一用來使金屬層平坦化的 BPSG (硼磷矽酸塩玻瑀）層，而基板的背面枝封裝而接 地。其次，利周LPCVD (偟壓化學氣相沈積）法在基板之 背面形成一50〇A〜2000 A厚的氮化物層。之後，藉高溫使 BPSG層重新流動而在其上形成一ΟΝΟ(氧化物氮化物氧化 物）層。在本例中，氮化物層與氧化物層之介電係數'最好 分別爲7.5與3.9。然後，在基板之頂面上實施金屬與鈍 化等過程，之後，將基板切成預定大小之單位。隨後，晶· 片被嵌裝在引線框上。 經浒部中央枕準而只工消伢合作社5-¾ 圖3顯示圖2之等效圖。在被介電痪連接到基板的電 源供應端32與被連接到引線框的接地端34之間形成背面電 容器16。在電源供應端32與基板之較低邊之間自然存有一 幾十ιήΩ的特定電阻18。在基板上之積體電路15的表面上 而形成在電源供應端與接地端間的電容器20包括接頭電容 、線電容及閘電容。電阻器22被連接在電容器20與電源供 應端31之間，或是電容器20與接地端33之間，第一與第二 電感器24興26被用來分別將電源供應端與接地端連接到封 裝引線框上。因爲第一電感器24抑制電荷量的增加，故在 防止電源供應端供應即時必須的電荷上，其扮演着相當重要的 角爸。結果，積體電路15遂利兩了儲存在內部電源線上的 本紙5t尺度边用中S S家说丨 Λ、疗叫.¾叫(4 ) 電荷。然ifn，如果内部诺源線之儲存容量不足夠，則內部 電源供應端31的顆壓就突然變低而且晶片之操作也變得不 穩定。同時，因爲背面跑容器16可將儲存其內的氅荷直接 供應到內部電源線，故積體甭路之瞬間堪源雜訊可被去除 ，而且穩定的電源HI盤的位準可被維持。此時，儲存在背 面電容器16的電荷童：可表示如下： ε s i = c X v = - χ ν L d 如上述之所述，如果背面電容器之面積s愈大，厚度 d愈小，介電係數ε愈大，則晶片所能儲存的電荷量就愈 多，而且亦可使操作穩定下來。 仗濟部屮央標準XJA.X-消价人：作社印5i (4先閲:Λ.··ιι';ϊ·-5 之：/?-*? ^-項再砑艿木仃) 在較佳實施例中，僅對η型基板加以描述。然而，亦 可以Ρ型基板來取代。在此情況下，ρ型基板應由電阻器 被連接到接地端，而電源供應端被連接到背面絶緣層對面 的引線框上。因此，在接地端與電源供應端之間形成背面 絶緣層可産生大容量的電容。此外，爲取代電容器，將預 定之薄膜形成在基板之背面上而得到另一電之元件。易言 之，在基板之背面上形成高電阻材料，或是在第一導電型 基板之背面上形成第二導電型之薄膜，則分別可形成電阻 器或二極體。 如上所述，在可抑制電源雜訊之積體電路裝置中，在 具有積體電路之基板的背面上形成一介電膜，以便在封裝 引線框與基板之間形成一高電容。因此，可降低電源雜訊 ，而且，因爲背面電容器之容電量的調整不受限制，故考 本Μ«張尺度边州中《 W ί 焊 WCNS) ΙΜ,Ηί格UM〇x2D7 .：uV!n 200631 Λ (i η ϋ 五、發明説明（5) 慮外面環境米設計晶片之內部電源乃易行之事。此外*爲 了去除電源雜訊，因爲不需要在基板之頂面上增設額外的 電容器*故積體電路的設計面積可被縮小。 雖然，本發明係特別參考較佳實施例來加以說明與顯 示》但熟悉本行技術之人士會了解到，在不背離本發明之 精神與範圍下可對實施例之形式與細節加以改變。 裝· ·'訂- A 度 尺 張 紙 本 公Λ ίί \\ (} Five m called (3) (Amended in September 1981) " Κ 木 玎) A large-capacity capacitor is formed between the package lead frame 14 and the substrate 10. Then, a power source having a polarity opposite to the polarity applied to the power supply terminal of the substrate is connected to the lead frame 14 so that a decoupling capacitor is formed between the power supply terminal of the wafer and the back of the semiconductor substrate. In detail, on the top surface of the semiconductor substrate on which the semiconductor device is formed, a BPSG (borophosphosilicate glass) layer for flattening the metal layer is formed, and the back side of the substrate is encapsulated and grounded. Secondly, the Li Zhou LPCVD (Non-Pressure Chemical Vapor Deposition) method forms a nitride layer with a thickness of 50 to 2000 A on the back of the substrate. After that, the BPSG layer is reflowed by high temperature to form an ONO (oxide nitride oxide) layer thereon. In this example, the dielectric constants of the nitride layer and the oxide layer are preferably 7.5 and 3.9, respectively. Then, processes such as metal and passivation are performed on the top surface of the substrate, and then the substrate is cut into units of a predetermined size. Subsequently, the wafer is embedded on the lead frame. Through the central part of the Margin Department, only the Consumers' Cooperative Society 5-¾ Figure 3 shows the equivalent diagram of Figure 2. The back capacitor 16 is formed between the power supply terminal 32 connected to the substrate by the dielectric and the ground terminal 34 connected to the lead frame. Between the power supply terminal 32 and the lower side of the substrate, there is naturally a specific resistance 18 of several tens of Ω. The capacitor 20 formed between the power supply terminal and the ground terminal on the surface of the integrated circuit 15 on the substrate includes a connector capacitance, a line capacitance, and a gate capacitance. The resistor 22 is connected between the capacitor 20 and the power supply terminal 31, or between the capacitor 20 and the ground terminal 33, and the first and second inductors 24 and 26 are used to connect the power supply terminal and the ground terminal to Packaged on the lead frame. Because the first inductor 24 suppresses the increase in the amount of charge, it plays a very important role in preventing the supply of the necessary charge at the power supply end. As a result, the integrated circuit 15 takes advantage of the 5t scale edge of the original paper stored on the internal power supply line. The s, s, s, s, s, s, and (4) charges. However, if the storage capacity of the internal Nuo source line is insufficient, the particle pressure of the internal power supply terminal 31 suddenly becomes low and the operation of the chip becomes unstable. At the same time, because the back running container 16 can directly supply the stored charge to the internal power cord, the source noise can be removed at the moment of the integrated road, and the level of the stable power HI disk can be maintained. At this time, the charge stored in the back capacitor 16 can be expressed as follows: ε si = c X v =-χ ν L d As described above, if the area s of the back capacitor is larger, the thickness d is smaller, the dielectric The larger the coefficient ε, the more charge can be stored in the chip, and the operation can be stabilized. Based on the Ministry of Economics and Social Standards XJA.X- Consumers: Zuo She Yin 5i (4 first reading: Λ. ·· ιι '; ϊ · -5 of: /?-*? ^-项 再 砑 艿 木 伃) In the preferred embodiment, only the n-type substrate is described. However, it can also be replaced by a p-type substrate. In this case, the p-type substrate should be connected to the ground terminal by a resistor, and the power supply terminal should be connected to the lead frame opposite to the back insulating layer. Therefore, forming a back insulating layer between the ground terminal and the power supply terminal can generate a large-capacity capacitor. In addition, to replace the capacitor, a predetermined thin film is formed on the back surface of the substrate to obtain another electrical element. In other words, forming a high-resistance material on the back surface of the substrate or forming a thin film of the second conductivity type on the back surface of the first conductivity-type substrate can form a resistor or a diode, respectively. As described above, in an integrated circuit device capable of suppressing power supply noise, a dielectric film is formed on the back surface of a substrate with an integrated circuit to form a high capacitance between the package lead frame and the substrate. Therefore, the power supply noise can be reduced, and because the adjustment of the capacitance of the back capacitor is not limited, the textbook «Zhang Scale Bianzhou" W ί Welding WCNS) ΙΜ, Ηί 格 UM〇x2D7 .: uV! N 200631 Λ (i η ϋ) 5. Description of the invention (5) It is easy to design the internal power supply of the chip considering the external environment. In addition * In order to remove power noise, it is not necessary to add an additional capacitor on the top surface of the substrate Therefore, the design area of the integrated circuit can be reduced. Although the present invention is particularly described and shown with reference to the preferred embodiments, those skilled in the art will understand that without departing from the spirit and scope of the present invention Change the form and details of the embodiment. 装 ·· '定-A ruler sheet of paper

Claims (1)

,00631, 00631 Α7 Β7 C7 D7 六、申請專利範園 （81年9月修正） 1. 一種電源雜訊受抑制之積體電路裝置，其含有一厚 度爲500 λ〜2000 λ之介電膜形成在具有積體電路之半導 體基板的背面上*以便利用基板、介電膜及封裝引線框來 形成一電容器。 2. 如申請専利項目1所述之裝置*其中所述封裝引線 框之極性與施加到基板之電壓的極性相反。 3. —種電源雜訊受抑制之積體電路裝置*其含有一特 定薄膜形成在具有積體電路之半導體基板的背面上，以便 藉此形成一特定的電之元件。 (請先閱讀背面之注意事項再填窝本頁) .襄， Jr 經濟部屮央標準局貝工消費合作社印製 •綠· 本紙張尺度逍用中HH家揉準(CSS)甲4規格(210x297公釐)Α7 Β7 C7 D7 VI. Patent application (revised in September 1981) 1. An integrated circuit device with suppressed power supply noise, which contains a dielectric film with a thickness of 500 λ ~ 2000 λ formed on the integrated circuit On the back of the semiconductor substrate of the circuit * to form a capacitor using the substrate, dielectric film and package lead frame. 2. The device described in the application item 1 * wherein the polarity of the package lead frame is opposite to the polarity of the voltage applied to the substrate. 3. An integrated circuit device in which power supply noise is suppressed * contains a specific film formed on the back surface of a semiconductor substrate having an integrated circuit, in order to thereby form a specific electrical element. (Please read the precautions on the back before filling in the nest page). Xiang, Jr Printed by Beigong Consumer Cooperative, Department of Standards, Bureau of Economics, Ministry of Economics • Green 210x297mm)
TW081100147A 1991-08-19 1992-01-10 TW200631B (en)

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