GB2255693A

GB2255693A - A digital data decoder

Info

Publication number: GB2255693A
Application number: GB9109578A
Authority: GB
Inventors: James Kenneth Alexande Ritchie; Howard Stephen Mitchell
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1991-05-02
Filing date: 1991-05-02
Publication date: 1992-11-11
Also published as: EP0514041A2; ATE168850T1; GB9109578D0; EP0514041A3; DE69226307D1; DE69226307T2; EP0514041B1

Abstract

A digital data decoder which checks for errors in data which it receives and signals when there are more than a set number of errors found during a set period. The decoder and an associated demodulator use the error information to select one of a plurality of available data transmissions for decoding. <IMAGE>

Description

A digital data-decoder 2235o93 The present invention relates to a digital

data decoder which is especially suitable for decoding digital data which is encoded in accordance with EBU SPB 424, for example, NICAM 728 format data, but is not exclusively for that data format.

A digital data decoder is required to extract blocks of data from a received signal and to obtain the original data from the extracted blocks. A decoder of digital data may be required to obtain the original data from information which has been compressed, interleaved, and corrupted by noise by expanding the received information, de-interleaving it, and detecting and correcting errors such as those caused by noise corruption. In particular, a decoder for NICAM 728 transmissions is required to recognise and extract key blocks of data, to expand the received data to de-interleave it, and to detect and correct errors in it.

It is an object of the present invention to provide a digital data decoder which is especially, but not exclusively, for NICAM 728 data.

The present invention provides a digital data decoder which, in operation, checks for errors in data which it receives and signals when there are more than a set number of errors found during a set period.

Preferably, the decoder accumulates a total of the number of errors found, and, preferably the decoder performs error correction.

Preferably, the decoder and an associated demodulator, which are connected together, use the error information as a means of selecting one of a plurality of data transmissions which are available, by changing receiving characteristics in order to change the data transmission selected for decoding when the set number of errors is exceeded.

Preferably, the decoder is connected to a demodulator by a first signal transmission means along which, in operation, demodulated signals pass to the decoder, and connected to the demodulator by second signal transmission means along which, in operation, a signal from the decoder passes to indicate whether the decoder is able to establish a locked condition with the incoming demodulated signals, wherein the demodulator is capable of changing its receiving characteristics in response to the decoder signalling that it is unable to establish a locked condition with the incoming demodulated signals.

Preferably, the decoder includes means for reducing progressively the magnitude of its decoded output signal when the number of errors accumulated during the set period exceeds the set number.

Preferably, the means for reducing the magnitude of the decoded output signal includes means for dividing the output signal progressively.

Preferably, the means for reducing the magnitude of the decoded signal includes a shift register and means for shifting the data sent to the shift register towards the register which holds the least significant digit, by progressively more places, when the number of errors exceeds the set number.

Preferably, the decoder includes means for increasing progressively the magnitude of the decoded output signal when the number of errors ceases to exceed the set number.

Preferably, the means for increasing the magnitude of the decoded output signal includes means for doubling the magnitude of the output signal progressively.

Preferably, the means for doubling the magnitude of the output signal includes a shift register and means for shifting the data sent to the shift register towards the register which holds the least significant digit, by progressively fewer places, when the number of errors ceases to exceed the set number.

Preferably, the decoder includes means for varying the number set as the permitted number of errors.

Preferably, the decoder includes means connecting the decoder to a remote control interface for permitting the entry of the set number by way of the remote control interface.

Preferably, the decoder includes an addressable memory, means taking into account shuffling and interleaving of the data and writing the data into an addressable memory in the correct sequence for application to a digital-to-analogue converter.

Preferably, the decoder includes two data processing paths, in which means on one data processing path reads data from selected addresses in the addressable memory and places incoming data in the selected addresses from which data was read, and means on the other data processing path selects the neat addresses for the reading and writing of data.

Preferably, the decoder includes a bus-compatible output port, and, preferably, it includes a remote control interface.

Preferably, the decoder is capable of finding frames of serial data for storage by identifying a frame alignment word which precedes each frame of serial data, wherein the decoder operates by discarding single digits which are not the initial frame alignment and digit and discarding sequences of digits as soon as they deviate from the frame alignment word sequence.

Preferably, the decoder is capable of finding those frames which it is required to store by discarding single digits which are not an initial control digit of interest and of discarding specific sequences of control digits which follow a digit which has been discarded.

Preferably, the decoder operates by discarding data which follows discarded control digits.

A digital decoder in accordance with the present invention will now be described, by way of example only, with reference to the acompanying drawings, in which:

Fig. 1 is a diagrammatic representation of the decoder, Fig. 2 is a flow chart representation of the operation of the decoder in finding key blocks of data in a serial data stream, and Fig. 3 is a diagrammatic representation of the decoder and a demodulator connected together.

Referring to Fig. I of the accompanying drawings, the decoder includes an interface circuit 1, a frame store 2, an A-register 3, a parity reconstruction circuit 4, an arithmetic and logic unit (ALU) 5, a scale factor register store 6, an address state machine 7, an output circuit 8, a scratchpad memory 10, a parity state machine 10, a status register 11, and a control ROM 12 which controls the operation of the decoder.

Referring to Fig. 1, demodulated serial digital data is received by the interface circuit 1 from which it passes to the frame store 2 where it is stored in the order in which it is received and from which it is available in parallel form. The data supplied to the frame store 2 is also available to the A-register 3 which extracts the parity-check information and passes that information to the ALU 5, the scale factor register store 6, and the parity reconstruction circuit 4.

Referring to Fig. 1, the parity check information which forms part of the digital data provides information as to the extent of compression of the data which it accompanies and includes, also, error correction facilities. The decoder extracts the parity check information by way of the Aregister 3 and supplies data, based on the scale factor information, by way of the scale factor register store 6, for expanding the decoded data by an amount corresponding to the amount by which it was compressed. The decoder also determines the number of errors which are present in the received data and makes the error information available by way of the status register 11. The parity check reconstruction circuit 4 provides an output signal which indicates whether the number of errors found in the data received by the decoder is more than a set number.

Referring to Fig. 3 of the acompanying drawings, the decoder 30 is connected to a demodulator 29 which provides the demodulated serial data for the decoder 30, And the demodulator 29 receives the output signal from the control ROM 12 of Fig. I along a signal connection 31. The demodulator 29 is able to respond to the signal provided by the decoder 30, when that signal indicates that the decoder 29 is unable to decode the received data, by adjusting its bandpass characteristics to demodulate data in a frequency band different from the data giving rise to the decoder signal. The reasons for that mode of operation are that the system is capable of demodulating data which may be centred on 6.552 MHz or on 5.85 MHz, which are, respectively, NICAM system I and NICAM system B/G. The decoder 30 and demodulator 29 will treat incoming data as belonging to NICAM system I, centred on 6.55 MHz, unless the number received of received errors exceeds the set level, at which time the decoder 29 (will signal that it cannot decode the received data,) and the demodulator 30 will modify its bandpass parameters as for NICAM system B/G centred on 5.85 MHz.

Referring to Figs. I and 3, the demodulator 29 and decoder 30 are capable of detecting more than a set number of errors in received data and of changing their receiving characteristics when more than the set number of errors is detected. otherwise, the current receiving characteristics are maintained.

Referring to Fig. 1, the output circuit 8 is capable of reducing progressively the magnitude of the decoded output signal when the number of errors accumulated during a set period exceeds the set number. The output circuit 8 receives a signal from the status register 11 and is capable of performing shift operations, by the use of a shift register, on the digital words it receives from the frame store 2 in order to change the magnitude of the output signal. In the situation where the status register 11 indicates that the set number of errors has not been exceeded, the output circuit 8 shifts the stored digital signals towards the least significant digit, by progressively more places, until the minimum output signal is provided. When there are fewer than the set number of errorst the stored digital data is shofted by progressively fewer places towards the least significant digit and, eventually, there is no shofting of the output signal.

Referring to Fig. 1, the decoder includes provision for the alteration of the set number of errors to which the device operates. Such alteration would be made by an equipment manufacture during the production of equipment which includes the decoder. The control would be exercised through a remote control interface.

Referring to Figure 1, the decoder processes a serial bit stream and stores it in parallel in the frame store 2.

The decoder has two parallel paths to maximise throughput. In the first path, data is read from the frame store 2, mod fied with the incoming data bit and stored in the same store location. In the other processor path, the address to be used with next bit operation is selected and any temporary pointers are modified.

Decoding requires that the write/read addresses for e data in the frame store 2 be manipulated in real time. In the case when stereo is transmitted the A and B samples are stored alternately in a block of samples for each frame. on alternate frames read and write addresses switch between 0-63 and 64-127.

In the case of mono transmissions more memory is required because of the order in which mono samples are received. At any one time, two frames of data must be kept in a memory while a third frame of data is received and written to the memory. In addition, mono data for two time frames is received in a single frame. The addressing of the memory is much more complex than it is for stereo and the address state machine 7 is used to generate the addresses for the blocks of memory. Mono samples are stored in blocks of 32. The address state machine 7 has to generate addresses for the particular blocks which are being read and written. For example, the following sequence of addresses could be used to read data out Simultaneous access of blocks:- Frame Read Addresses Count Block 1 Block 2 1 2 3 6 7 11 12 0-31 64-95 128-159 0-31 32-63 128-159 160-191 32-63 96-127 160-191 64-95 96-127 Write Addresses 32-63 96127 160-191 64-95 96-127 0-31 64-95 128-159 0-31 32-63 128-159 160-191 96-127 031 64-95 128-159 0-31 32-63 128-159 160-191 32-63 96-127 160-191 64-95 repeats from frame 1.

32 is done in software.

160-191 32-63 96-127 160-191 64-95 96-127 0-31 64-95 128-159 0-31 32-63 128-159 AddressThe The sequence then ing within the blocks of addressing of the blocks is done by a 4 bit state machine generating 3 address bits for each block which must be read.

Stereo/mono selects between addresses exclusively from the ALU 5 and the addresses whose most significant 3 bits came from the address state machine 7.

When addresses are for mono sound the 6th bit from the read and write latches are used to select between block A and block B of the address space.

The state machine is clocked by a frame clock.

As will be evident from the above description of the manner in which the frame store 2 is addressed, the decoder includes means for taking into account shuffling and interleaving of the data and writing it into the frame store 2 in the correct sequence for application to a digital-toanalogue converter.

As is evident in Fig. 1, there are two data processing paths included in the decoder, and means on one data processing path reads data from selected addresses in the frame store 2 and places incoming data in the selected addresses from which data was read, and means on the other data processing path selects the next addresses for the reading and writing of data.

As has been mentioned above, one of the processing operations performed on the incoming data is the extraction of parity information, which is used to reconstruct a range scale factor for a block of samples.

In the operation of the decoder represented by Fig. 1, each range information bit is coded in 9 samples of received frames of data. Majority voting is performed on accumulated parity information for each coded bit. The accumulated parity information is stored in a scratch memory 9. The addressing for accumulating this parity information is controlled by a state machine 10 which is initialised by software.

Referring to Fig. 1, the range information which is coded in the parity of the samples, alters the parity of samples in the process. After the range information has been extracted from the parity coding it is stored in registers belonging to the ALU 5. The stored scale factor information is then used to reconstruct the original sample parity at the output circuit 8.

The output circuit 8 checks the reconstructed parity for correctness and takes appropriate action (flag an error on the sample or pass the sample to the output stages).

Referring to Fig. 1, additional information (other than scale factors) can also be coded in the parity of some samples. This is also extracted from the parity of samples, majority voting writing performed and the information then stored for parity reconstruction.

The decoder represented by Fig. 1 can lock on to NICAM data coded according to EBU SPB 424. Locking operates on the frame alignment codes and control bit sequences in the NICAM data stream.

The locking procedure in software determines whether NICAM data is present and uses this information to switch the filtering used to demodulate the received NICAM signal, as has been explained above.

The decoder represented by Fig. 1 extracts control information from the received data and writes it to status registers for use by a system interface bus. The control information also controls the program flow in the decoder as the control information indicates the type of information being received.

The decoder represented by Fig. 1 accumulates parity errors and status registers store the information as to the number of errors. The software puts an upper limit on the number of errors written to the status register.

The decoder represented by Fig. 1 also includes a bus-compatible output port and a remote control interface.

Fig. 2 is a flow chart representation of the operation of the decoder in establishing a locked condition in relation to the data being supplied to the decoder represented by Fig. 1.

Referring to fig. 2, the decoder first seeks to lock to a fixed code in the Nicam data stream, the frame alignment word (FAW), which occurs once per frame. Once frame alignment words on consecutive frames have been detected the decoder seeks to lock to the first of a block of sixteen frames.

A single control bit following the frame alignment word on each frame forms a pattern of eight binary 'Ill's then eight binary 1101's over a block of sixteen frames. The decoder seeks to lock on to the first of a block of sixteen frames by examining the received control bits.

If the frames received have binary 11011 control bits they are discarded until the arrival of a frame with a binary 11111 control bit. Control bits for the following fifteen frames are then retained and verified against the expected received pattern of control bits over a block of sixteen frames. If the control bit pattern is correct then following frames are retained.

If the frames received initially have binary control bits they are all discarded. Following frames with binary 11011 control bits are also discarded until the arrival of another frame with a binary 11111 control bit. Control bits for the following fifteen frames are then retained and verified against the expected received pattern of control bits over a block of sixteen frames. If the control bit pattern is correct then following frames are retained.

The procedure ensures that decoding always begins with a complete set of 16 frames having a binary pattern of eight 'Ill's followed by eight "Olls control bits.

As will be evident from the description of how the decoder operates, it is capable of detecting the frame alignment word (FAW) by the use of logic to discard single digits which are not the initial frame alignment and digit and to discard sequences of digits as soon as they deviate from the frame alignment word sequence. Also, the decoder is capable of finding those frames which it is required to store by the use of logic to discard single digits which are not the initial control - digit of interest and of discarding specific sequences of control digits which follow a digit which has been discarded, and of discarding the data which follows discarded control digits. The manner of operation of the decoder avoids the need to store significant amounts of data for finding the beginning of data sequences.

1

Claims

CLAIMS:

1. A digital data decoder which, in operation, checks for errors in data which it receives and signals when there are more than a set number of errors found during a set period.

2. A decoder as claimed in claim 1, which performs error correction and accumulates a total of the number of errors found.

3. A decoder as claimed in claim 1 or claim 2, and an associated demodulator, which is connected to the decoder, which use the error information as a means of selecting one of a plurality of data transmissions which are available, by changing receiving characteristics in order to change the data transmissions selected for decodeding when the set number of errors is exceeded.

4. A decoder as any one of claims 1 to 3, connected to a demodulator by a first signal transmission means along which, in operation, demodulated signals pass to the decoder, and connected to the demodulator by second signal transmission means along which, in operation, a signal from the decoder passes to indicate whether the decoder is able to establish a locked condition with the incoming demodulated signals, wherein the demodulator is capable of changing its receiving t characteristics in response to the decoder signalling that it is unable to establish a locked condition with the incoming demodulated signals.

5. A decoder as claimed in any one of the preceding claims, including means for reducing progressively the magnitude of its decoded output signal when the number of errors accumulated during the set period exceeds the set number.

A decoder as claimed in claim 5, wherein the means for reducing the magnitude of the decoded output signal includes means for dividing the output signal progressively.

7. A decoder as claimed in claim 6, wherein the means for reducing the magnitude of the decoded signal includes a shift register and means for shifting the data sent to the shift register towards the register which holds the least significant digit, by progressively more places, when the number of errors exceeds the set number.

8. A decoder as claimed in any one of claims 5 to 7, including means for increasing progressively the magnitude of the decoded output signal when the number of errors ceases to exceed the set number.

9. A decoder as claimed in claim 8, wherein the means for increasing the magnitude of the decoded output signal includes means for doubling the magnitude of the output signal progressively.

10. A decoder as claimed in claim 9, wherein the - 18 means for doubling the magnitude of the output signal includes a shift register and means for shifting the data sent to the shift register towards the register which holds the least significant digit, by progressively fewer places, when the number of errors ceases to exceed the set number.

11. A decoder as claimed in any one of the preceding claims, including means for varying the number set as the permitted number of errors.

12. A decoder as claimed in claim 11, including means connecting the decoder to a remote control interface for permitting the entry of the set number by way of the remote control interface.

13. A decoder as claimed in any preceding claim, which includes an addressable memory, means for taking into account shuffling and interleaving of the data and writing the data into an addressable memory in the correct sequence for application to a digital-to-analogue converter.

14. A decoder as claimed in claim 13, which includes two data processing paths, in which means on one data processing path reads data from selected addresses in the addressable memory and places incoming data in the selected addresses from which data was read, and means on the other data processing path selects the next addresses for the reading and writing of data.

15. A decoder as claimed in any one of the preceding claims, which includes a bus-compatible output port.

16. A decoder as claimed in any one of the preceding claims, which includes a remote control interface.

17. A decoder as claimed in any one of the preceding claims, which is capable of finding frames of serial data for storage by identifying a frame alignment word which precedes each frame of serial data, wherein the decoder operates by discarding single digits which are not the initial frame alignment word digit and discarding sequences of digits as soon as they deviate from the frame alignment word sequence.

18. A decoder as claimed in claim 17, which is capable of finding those frames which it is required to store by discarding single digits which are not an initial control digit of interest and of discarding specific sequences of control digits which follow a digit which has been discarded.

19. A decoder as claimed in claim 18, which operates by discarding data which follow discarded control digits.

20. A decoder substantially as herein described with reference to, and as illustrated by, the accompanying drawings.