JP2008072190A - Data transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmitter which reduces delay time as much as possible in interleave and deinterleave and gives a distribution interval to the last data and the start data of a block. <P>SOLUTION: The data transmitter comprises a transmitter which performs writing of data in the first and second columns of a transmission memory block while replacing, reads out such data as finishing writing before a plurality of continuous data are written in entirely, and performs interleaving of a plurality of arbitrary continuous columns from the last column to the third column of a transmission memory block such that the data of each row are read out and output while being replaced by the data before one row, and a receiver which can perform deinterleaving processing and which performs writing of a receiving memory block sequentially in the predetermined receiving order in the row direction, replacing the first and second columns of the receiving memory block, reads outs the data of a plurality of arbitrary continuous columns from the last column to the third column of the memory block while replacing by the data after one row and then outputs the data thus read out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to interleaving for distributing code arrangements on a transmission line in transmission of information data.

  In recent years, image compression technology has made remarkable progress, and it is possible to compress enormous amounts of image data to a few tenths of the original, increasing the total number of image frames that can be recorded on a recording medium, etc. Even when image data is transmitted using a transmission device having a relatively low transmission rate, it is used as a technique that enables transmission in real time.

  By the way, in the transmission path used for transmission of image data, since external noise is added, a part of the transmission data becomes incorrect data, and correct data is not transmitted to the receiving side, and the image is disturbed. There is a case.

  Therefore, an error correction function is added to the transmission function. For error correction, error correction codes such as Reed-Solomon, convolutional code and Viterbi decoding, which have high correction efficiency, are used. However, if errors occur in bursts, an interleave processing function is provided to continuously create a data string in which data divided into a plurality of unit blocks is distributed and arranged at a predetermined interval, and then transmitted. The decoding capability of the decoder is improved by dispersing long burst errors into short burst errors less than the maximum possible number of correction codes. (For example, refer to Patent Document 1).

  Here, the data transmission apparatus examined by the present inventors will be described with reference to FIGS. These data are stored in a memory block with multiple rows and multiple columns in the memory means, and are sequentially output so as to have a data interval in the row direction. It is a method.

  FIG. 6 is a block diagram showing an example of the configuration of a data transmission device having an interleaving function, and FIG. 7 is a block diagram showing an example of the configuration of a data receiving device having a deinterleaving function.

  FIG. 8 is a diagram showing a data writing order and a data reading order in the interleaving process, and FIG. 9 is a deinterleaving process, respectively.

  FIG. 10 is a diagram illustrating a time chart of data rearrangement and rearrangement in interleaving and deinterleaving processing. 8 to 10, the interleave input / output operation is shown for n (number of rows) = 5 and m (number of columns) = 4.

  As shown in FIG. 6, transmission information data 601 is encoded by an encoder 602, and redundant data for error correction is added.

  A case of a plurality of memory blocks provided in the memory 1 (604), for example, a memory block A and a memory block B having two blocks will be described. Here, symbol data (encoded data 603) encoded in units of blocks of n rows and m columns are alternately input and output to perform interleaving.

  In response to a control command from the interleaved matrix address count control circuit 610, an address for counting one row at a time in the column direction is output from the interleave write address generation circuit 608, and encoded data 603 to be transmitted is one data per n rows in each column. The m columns are sequentially input to the memory 1 (604) (see FIG. 8A).

  The interleaved output data 605 starts from the first data in the first row and the first column in accordance with the address count from the interleave read address generation circuit 609 by the interleave matrix address count control circuit 610 and sequentially outputs in the row direction. (See FIG. 8 (b))

  In this way, data dispersed in the data interval of the number of rows (n = 5) can be output as the interleave output data 605 output. Interleaved output data 605 is data-modulated by data modulator 606 and a transmission signal 607 is output.

  As shown in FIG. 7, in the data receiving apparatus, a received signal 701 is demodulated into received data 703 by a data demodulator 702. The received data 703 is input in the case of a plurality of memory blocks provided in the memory 2 (704), for example, a memory block A and a memory block B having two blocks.

  As shown in FIG. 9, received data is alternately input and output in units of blocks of m columns (m = 4) and n rows (n = 5) to perform deinterleaving.

  The deinterleave matrix address count control circuit 710 outputs an address for counting one column at a time in the row direction from the deinterleave write address generation circuit 708, and the received data 703 is stored in the memory 2 (704) for n rows, one for each m columns of each row. Are sequentially input to the memory block A and the memory block B.

  The deinterleaved output data 705 starts from the first data in the first column and the first row and sequentially outputs in the column direction according to the address count output from the deinterleave read address generation circuit 709 by the deinterleave matrix address count control circuit 710. .

  In this way, the data in which the column rows are rearranged by the interleaving process is restored to the same original data order as the encoded data 603.

  However, since the interleaved transmission data is distributed at the number of rows (n = 5) data interval, the burst noise added on the transmission path is restored to the original data order by deinterleaving processing. n = 5) Noise is distributed at data intervals.

  Deinterleaved deinterleaved output data is decoded by a decoder 706, and the burst noise is dispersed to improve the correction capability and output error-corrected received information data 707.

  FIG. 10 is a time chart showing the relationship between the rearrangement of the interleaving process and the rearrangement of the deinterleaving process described above. In the interleaving process on the transmission side, the time required for inputting the data block of n rows and m columns to the memory 1 (604) is mnT, where T is the time required per data. Since data is read and data is output after all the block unit data is input, the interleave delay time is mnT.

  Furthermore, on the receiving side, the time required to input the received data to the memory 2 (704) and output the deinterleaved data is mnT, so the delay time in the deinterleaving process is mnT.

Therefore, the total delay time required for the block data to be processed by the transmitting side interleaving and the receiving side deinterleaving is 2 mnT.
In the case of m columns (m = 4) and n rows (n = 5), the total delay time is 40T.
Japanese Patent Laid-Open No. 2002-217741 (FIG. 7)

  When using a transmitter / receiver using interleaving and deinterleaving as described above, for example, when performing TV signal transmission such as sports broadcasting, while viewing received images, image signals from a plurality of cameras performing live broadcasting simultaneously When switching control is attempted, it is difficult to switch according to the situation of the relay situation because of the influence of the long delay time described above, resulting in a large operational problem.

  Further, the final data and the start data of adjacent blocks have a drawback that a continuous data portion having no dispersion interval occurs even in the output after interleaving, and the correction capability of this portion is impaired.

  Accordingly, an object of the present invention is to provide a data transmission apparatus that solves the above-described problems, reduces the delay time in the interleaving process and the deinterleaving process, and has a dispersion interval between the final data and the start data of the block. There is to do.

  In order to achieve this object, a data transmission apparatus according to the present invention includes a transmission apparatus that interleaves and transmits transmission data, and a reception apparatus that receives and transmits data transmitted from the transmission apparatus. In the data transmission device

The transmitter is
a transmission side memory composed of a plurality of blocks of n rows (n ≧ 4) and m columns (n ≧ m ≧ 4);
Transmission data writing means for sequentially writing the transmission data to each block of the transmission side memory in the column direction in the order of the second column, the first column, and the third column to the last column;
The transmission data written in each block of the transmission side memory is sequentially read and transmitted in the row direction, and at the time of reading, the transmission data continues from the last column or the last column between the last column and the third column. A transmission data read-out means for replacing any data in a plurality of columns with data in the previous row;
With
The receiving device is:
A receiving side memory composed of a plurality of blocks in the same row and the same row as each block of the transmitting side memory;
Received data writing means for receiving transmission data transmitted from the transmitting device and sequentially writing in a row direction to each block of the receiving side memory;
The transmission data written in each block of the receiving side memory is sequentially read in the column direction in the order of the second column, the first column, and the third column to the last column, and at the time of reading, the third column from the last column Receiving data reading means for replacing the data in the same column as the data in which the read data is replaced with the data in the previous row in the transmission side memory by the data in the next row;
It is comprised so that it may comprise.

  In the present invention, the total delay time of the interleaving process and the deinterleaving process can be reduced within a time range in which no data is lost.

  In addition, the arrangement of the transmission data after the interleaving process does not continue in the final data and the start data of adjacent blocks, and in the n-by-m block interleaving, a dispersion interval of (n-1) data or more is secured. Thus, the burst error correction capability for some data is not impaired.

  Hereinafter, embodiments of a data transmission apparatus that performs interleaving processing and deinterleaving processing according to the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 3, FIG. 11, FIG. 12, and FIG. 13 will be described.

  As a first embodiment, FIG. 1 is provided with an interleaving processing function, a transmission device that transmits transmission data by interleaving processing, and FIG. 2 is provided with a deinterleaving processing function, and receives data transmitted from the transmission device. It is a block diagram which shows an example of a structure of the receiver which performs a deinterleaving process then. The data transmission device of the present invention comprises the transmission device and the reception device.

  FIG. 3 is a diagram showing a data writing order and a data reading order in the interleaving process, and FIG. 4 is a deinterleaving process.

  FIG. 5 is a diagram showing a time chart of data rearrangement and rearrangement in interleaving and deinterleaving processing.

  3 to 5 show an operation example for data to be written to and read from a block size of n rows (n = 5) and m columns (m = 4).

First, in the present invention, in the interleaving block, replacing the first column _{(A 0 ~A 4, B 0} ~B 4) and the second column _{(A 5 ~A 9, B 5} ~B 9), the last column ( Since the previous column (left column) to the third column of one column or multiple columns from the right column of the memory block is replaced with the previous row data, if m = 3 column, the final data of the adjacent memory block Since the start data are adjacent to each other, the number of matrixes of the data block is (n ≧ m ≧ 4) in order to avoid this. (Details will be described later.)

Hereinafter, a detailed description of the first embodiment will be given.
In the transmission apparatus (hereinafter referred to as data transmission apparatus), as shown in FIG. 1, transmission information data 101 that is input transmission data is encoded by an encoder 102, and then redundant data for error correction is generated. In addition, encoded data 103 is generated.

  A case of a memory block A and a memory block B including a plurality of blocks (hereinafter referred to as a memory block) of the memory 1 (104), which is a transmission side memory, will be described as an example. The memory units of the memory block A and the memory block B each have n rows (n ≧ 4) and m columns (n ≧ m ≧ 4), and symbol data (encoded) that is alternately encoded in units of blocks. Data 103) is input, interleaving is performed and output is performed.

  As a first embodiment, an interleaved input / output operation by the memory block A and the memory block B will be described with reference to FIG. 3 when n (number of rows) = 5 and m (number of columns) = 4.

  By the control operation of the interleaved matrix address count control circuit 110, addresses that are sequentially counted in the column direction are output.

  The column data replacement control circuit 112 to which this address is input replaces the first and second columns, the replaced address output is input, and this is output as a write address by the interleave write address generation circuit 108. As shown in the memory block A and the memory block B in FIG. 3A, the encoded data 103 is written in the column direction by replacing the second column from the first row to the second column and the first column. Thereafter, data is sequentially written in the column direction. (Number of replacement columns: k = 1).

That is, the transmission information data 101 is sequentially written in the column direction in the order of the fourth column, which is the final column of m = 4 from the second column, the first column, and the third column, to each memory block of the memory 1 (104). Go on.
Similarly, data reading is shown in FIG. 3B for the number of replacement columns: k = 1.

  By the control operation of the interleaved matrix address count control circuit 110, the address sequentially counted in the row direction is output, and the row data replacement control circuit 111 to which this is input outputs the address replaced one row before the last column of the memory block. Further, this address is output as an address for data reading from the interleave read address generation circuit 109, data is read out in the order shown in FIG. 3B, and a dispersion interval of n (number of rows) or more is obtained. The interleaved output data 105 is output.

  This interleaved output data 105 is data-modulated by a data modulator 106 and a transmission signal 107 is output.

  Thus, the transmission data which is the encoded data 103 written in each block of the memory 1 (104) is sequentially read and transmitted in the row direction, and at the time of reading, the final column (fourth column) is transmitted. Is replaced with the previous data.

  As shown in FIG. 2, the receiving device (hereinafter referred to as a data receiving device) receives a transmission signal 107 that is data transmitted from the transmitting device that has been transmitted, and inputs it as a received signal 201. Is demodulated into received data 203 by a data demodulator 202.

  The received data 203 is a memory block composed of a plurality of memory blocks that are in the same row as the blocks of the memory 1 of the memory 2 (204) that is the receiving side memory, for example, two blocks so as to correspond to the transmitting side. A case of A and memory block B will be described.

  As shown in FIG. 4A, the configuration of the memory unit of each of the memory block A and the memory block B is composed of block units of m columns (m = 4) and n rows (n = 5). Received data 203 is input to the data, and deinterleave processing is performed to output deinterleaved data.

  Since the data of the previous input block is partially replaced with respect to a plurality of columns from the last (right column of the memory block), in the example of FIG. 4, the deinterleaving start operation from the memory block B which is the subsequent input block is performed. Show.

  An address counted in the row direction is output from the deinterleave write address generation circuit 208 by the control operation of the deinterleave matrix address count control circuit 210, and this is input to the memory block A and the memory block B as the deinterleave write address. As shown in (a), received data 203 is sequentially input to the memory block A and the memory block B of the memory 2 (204) for n rows, one for each row.

  In this way, the transmission data transmitted from the data transmission device is received and sequentially written in the row direction to each block of the memory 2 which is the receiving side memory.

  Data reading is shown in FIG. 4B for the case where the number of replacement columns: k = 1 so as to correspond to the transmission side. An address for sequentially counting in the column direction is output by the control operation of the deinterleave matrix address count control circuit 210, which replaces the first and second columns by the column data replacement control circuit 211, and one row for the last column of the memory block. The previously replaced address is output, the read address is output from the deinterleave read address generation circuit 209, the data is read out in the order shown in FIG. 4B, and rearranged by the interleave processing on the transmission side The obtained data is restored to the original data order having the same arrangement as the encoded data 103 before being interleaved, and deinterleaved output data 205 is obtained.

  As described above, the transmission data written in each block of the memory 2 is sequentially read in the column direction in the order of the second column, the first column, the third column, and the last column (fourth column). The data in the last column is replaced with the data after one row.

  Deinterleaved data 205 is decoded by decoder 206, and error-corrected received information data 207 is finally output.

  FIG. 5 is a time chart of the data transmission apparatus according to the first embodiment showing the relationship on the time axis of the rearrangement of the interleave processing and the rearrangement of the deinterleave processing described above.

  The input / output delay time for each data unit that writes and reads data in the memories 1 and 2 will be described below with a focus on the delay time T of the transmission data in each data.

As can be seen from the data arrangement of the interleaved output data (read data) shown in FIG. 5, the interleaved data on the transmission side is obtained by replacing the first and second columns at the time of writing. In the data (for example, B ₁₉ ) and the start data (for example, A ₀ ), the number of rows is equal to or greater than n, and the interleaved output is equal to (n−1) data or more.

The maximum input / output delay time in interleaving is the first row and mth column data of the block, in the example of FIG. 3, the read timing of (A ₁₅ ) (B ₁₅ ), and [{n · (m−1) +1} − (2m−p _i )] · T, [p _i = 1 (other than the right), p _i = 2 (m = n, number of replacement columns k = 1)] are obtained.

In the above example, if n = 5 and m = 4 are substituted, 9T is obtained. The case of p _i = 2 (m = n, number of replacement columns k = 1) will be described in an example described later.

On the other hand, on the receiving side, in the rearrangement of the deinterleave in the received data 203, that is, the deinterleave input data (write data), the data is written in the row direction and read in the column direction. Is the time until _n data (A _{0 to An} or B _{0 to} B _n ) in the first column are written, [{m · (n−1) +2} − (n−1)]. A relational expression of T is obtained. In the above example, if n = 5 and m = 4 are substituted, 14T is obtained.

From the above results, the total delay time from before the interleaving to after the deinterleaving is {2 · m · n− (3m + 2n−p _i −4)} · T, [p _i = 1 (other than the case on the right), p _i = 2 (m = n, number of replacement columns k = 1)]. In the above example, if n = 5 and m = 4 are substituted, 23T is obtained.

As a result, the total delay time of the interleaving method described with reference to FIGS. 6 to 10 is 2 · m · n · T = 40T. By using the technique of the present invention, (3m + 2n−p _i -4) · T = 17T of time can be shortened.

  The second embodiment will be described. FIGS. 11 to 13 show an example of the operation in the block data of the minimum matrix number of n rows = m columns of n rows (n = 4) and m columns (m = 4), and FIG. 11 shows data writing in the interleave processing. FIG. 12 is a diagram showing the order of reading and the order of reading, FIG. 12 is a diagram showing the order of writing and reading of data in the deinterleaving process, and FIG. 13 is a time chart of data rearrangement and rearrangement in the interleaving and deinterleaving processes FIG.

  This is a memory block configuration in which the number of rows and the number of columns of the interleave block are equal and the minimum number of rows and columns is adopted, and the replacement is performed when n (number of rows) = 4 and m (number of columns) = 4 The embodiment of the data transmission apparatus in which the rearrangement of the interleaving process and the rearrangement of the deinterleaving process are performed under the respective conditions in the case of the number of columns (k = 1) and (k = 2). This will be described with reference to FIGS.

  In interleaving, as shown in FIG. 11 (a), input is started from the second column and the first row, and the second and first columns are replaced and written in the column direction. Sequential writing is performed.

  When reading and outputting data, reading is sequentially performed in the row direction as shown in FIG. 11B, and in the case of the number of replacement columns (k = 1), as shown in the left diagram of FIG. 11B, When the number of replacement columns (k = 2) is read for the last column, as shown in the right diagram of FIG. 11B, the data for the previous row is read for the last two columns. Is done.

  In the case of the number of replacement columns (k = 1) and (k = 2) in deinterleaving, as shown in FIGS. 12 (a1) and (a2), writing is sequentially performed in the row direction from the first column of the first row. Done.

  As shown in FIGS. 12 (b1) and 12 (b2), the deinterleaved data read output is read starting from the second column and the first row, replacing the second column and the first column. Read sequentially in the direction.

  In the case of the number of replacement columns (k = 1), as shown in FIG. 12 (b1), the data after one row is read for the last column, and in the case of the number of replacement columns (k = 2), FIG. As shown in (1), the data after one row is read for the last two columns. The data rearranged by the interleaving process on the transmission side is restored to the same original data order as the transmission data by the above deinterleaving, and is received and output as deinterleaved output data.

  The relationship between the rearrangement of the interleaving process and the rearrangement of the deinterleaving process is as shown in FIG. 13 (ab1) when the number of rewrite columns is k = 1, and as shown in FIG. 13 (ab2) when the number of rewrite columns is k = 2. It becomes like the time chart operation.

  The input / output delay time in units of data read and written in the memory is defined as transmission data delay time T in each data, and will be described below.

  As can be seen from the interleaved output data (read data) in FIG. 11, the interleaved data is the number of rows n data in the last data and the start data of the adjacent blocks by replacing the first and second columns at the time of writing. The above-mentioned dispersion interval is obtained, and the interleave output is also a dispersion interval of (n-1) data or more.

The maximum input / output delay time in interleaving is the data in the first row and mth column of the block, FIG.
In the examples of (ab1) and (ab2), the read timing of (A ₁₂ ) (B ₁₂ ) is a reference, and [{n · (m−1) +1} − (2m−p _i )] · T, [ p _i = 1 (in cases other than the right), p _i = 2 (m = n, number of replacement columns k = 1)], and in the case of the number of replacement columns (k = 1) in FIG. , (P _i = 2) and 7T, and in the case of the number of replacement columns (k = 2) in FIG. 13 (ab2), (p _i = 1) and 6T.

In the first row and m-th column data, that is, in the examples of FIGS. 13 (ab1) and (ab2), the read timing of (A ₁₂ ) (B ₁₂ ) is the reference for the input / output delay time in the interleaving.

The data of the 1st row (m-1) th column data [(A ₈ ) (B ₈ ) in the example of FIG. 13] 1 data before the 1st row in the writing row direction with respect to the 1st row mth column data which is the reference of the input / output delay time The time difference in the input order is n · T.

However, in the case of the number of replacement columns (k = 1) in the example of FIG. 13 (ab1), one row is replaced in the last column, m columns, so that the reading sequence of the first row and m-th column data is read. The time difference is a time difference of (m + 1) · T. When the number of rows and the number of columns are equal (example m = n = 4 in FIG. 13), the time difference is (n + 1) · T. Will increase (p _i = 2).

In the example of FIG. 13 (ab2), in the case of k = 2> 1, since the 1st row and mth column data and the data before 1 data in the row direction are replaced together, the 1st row and mth column data The time difference of the reading order with respect to is 1 · T, and it is not necessary to increase the interleaved reading delay (p _i = 1).

As in the first embodiment, when n> m, even if the time difference of the reading order with respect to the first row and m-th column data is (m + 1) · T in the number of replacement columns (k = 1), n ≧ Since (m + 1), there is no need to increase the interleave read delay (p _i = 1).

  In the example of deinterleaving in FIGS. 13 (ab1) and (ab2), the delay time is 11T from the equation in the figure, and the total delay time in FIG. 13 (ab1) is 18T, in FIG. 13 (ab2). The total delay time is 17T.

In the case of the interleave method described with reference to FIGS. 6 to 10, the total delay time when m = n = 4 is 32T (2 · m · n · T = 32T). On the other hand, as described above, according to the present invention, the time is reduced by the time of (3m + 2n−p _i −4) · T (32T−18T = 14T, 32T−17T = 15T) and no data is lost. If the code processing is within the range, transmission with reduced delay time can be realized.

  Also, the transmission data after the interleaving process does not continue in the final data and the start data of adjacent blocks, and in the block interleaving of n rows and m columns, the transmission interval is equal to or greater than (n-1) data, and the burst data The ability to correct errors is not impaired.

  In each of the above embodiments, the case where the memory block has 4 rows and 5 columns and the case where the memory block has 4 rows and 4 columns are exemplified, but the number of rows and columns of the memory block is not limited thereto.

  In the first embodiment, when the transmission data written in each block of the transmission side memory is read in the row direction, only the data in the last column is replaced with the data in the previous row. Data in a plurality of columns (in the first embodiment, the third column and the fourth column in the first embodiment) from the last column up to the third column may be replaced with the data of the previous row.

  When the transmission data written in each block of the reception side memory is read out, the data in the same column as the column in which the read data is replaced with the data of the previous row in the transmission side memory among the third column from the last column May be replaced with the data after one line. As a result, a deinterleave output in the same order as the transmission data before interleaving can be obtained.

It is a block diagram which shows the structure of the data transmitter of one Embodiment of this invention. It is a block diagram which shows the structure of the data receiver of one Embodiment of this invention. In the interleaving process of the data transmission apparatus of the data transmission apparatus of the present invention, the order of data writing and reading in the case of n rows (n = 5) m columns (m = 4) blocks and the number of replacement columns (k = 1) is shown. It is a memory block block diagram shown. In the deinterleaving process of the data receiving apparatus of the data transmission apparatus of the present invention, the data write order and read order in the case of n rows (n = 5) m columns (m = 4) blocks and the number of replacement columns (k = 1) It is a memory block block diagram which shows. In the interleaving and deinterleaving processing of the data transmission apparatus of the present invention, data rearrangement and rearrangement codes in the case of n rows (n = 5) m columns (m = 4) blocks and the number of replacement columns (k = 1) It is a time chart figure which shows these time series. It is a block diagram which shows an example of a structure of the data transmission apparatus which this inventor examined. It is a block diagram which shows an example of a structure of the data transmission apparatus which this inventor examined. FIG. 5 is a memory block configuration diagram showing a data writing order and a reading order in the case of n rows (n = 5) and m columns (m = 4) blocks in the interleaving process of the data transmission apparatus examined by the present inventors. FIG. 3 is a memory block configuration diagram showing a data writing order and a reading order in the case of n rows (n = 5) and m columns (m = 4) blocks in the deinterleaving process of the data transmission apparatus examined by the present inventors. In the interleaving and deinterleaving processing of the data transmission apparatus examined by the present inventors, the time indicating the time series of the data rearrangement and rearrangement codes in the case of n rows (n = 5) m columns (m = 4) blocks It is a chart figure. In the interleaving process of the data transmitting apparatus according to the second embodiment of the present invention, the data write order in the case of n rows (n = 4) m columns (m = 4) blocks and the number of replacement columns (k = 1, 2) and It is a memory block block diagram which shows reading order. Data writing order in the case of n rows (n = 4) m columns (m = 4) blocks and replacement column numbers (k = 1, 2) in the deinterleaving process of the data receiving apparatus of the second embodiment of the present invention FIG. 3 is a memory block configuration diagram showing a reading order. In the interleaving and deinterleaving processing of the second embodiment of the present invention, the data is rearranged and arranged in the case of n rows (n = 4) m columns (m = 4) blocks and the number of replacement columns (k = 1, 2). It is a time chart figure which shows the time series of the correction | amendment code | symbol.

Explanation of symbols

101,601: Transmission information data
102,602: Encoder (with redundant data added)
103,603: Encoded data
104,604; Memory 1 (for sending side interleaving)
105, 605: Interleave output data
106,606: Data modulator
107, 607: Transmission signal
108,608: Interleave write address generator
109, 609: Interleave read address generation circuit
110, 610: Interleave matrix address count control circuit
111: Row data replacement control circuit (for interleave reading)
112: Column data replacement control circuit (for interleave writing)
201, 701: Received signal
202, 702: Data demodulator
203, 703: Received data
204, 704: Memory 2 (for sending side interleaving)
205, 705: Deinterleaved output data
206, 706: Decoder (error correction)
207, 707: Received information data
208, 708: Deinterleave write address generation circuit
209, 709: Deinterleave read address generation circuit
210, 710: Deinterleave matrix address count control circuit
211: Column data replacement control circuit (for deinterleave reading)

Claims (1)

In a data transmission device comprising: a transmission device that interleaves and transmits transmission data; and a reception device that receives data transmitted from the transmission device and performs deinterleaving processing;
The transmitter is
a transmission side memory composed of a plurality of blocks of n rows (n ≧ 4) and m columns (n ≧ m ≧ 4);
Transmission data writing means for sequentially writing the transmission data to each block of the transmission side memory in the column direction in the order of the second column, the first column, and the third column to the last column;
The transmission data written in each block of the transmission side memory is sequentially read and transmitted in the row direction, and at the time of reading, the transmission data continues from the last column or the last column between the last column and the third column. A transmission data read-out means for replacing any data in a plurality of columns with data in the previous row;
With
The receiving device is:
A receiving side memory composed of a plurality of blocks in the same row and the same row as each block of the transmitting side memory;
Received data writing means for receiving transmission data transmitted from the transmitting device and sequentially writing in a row direction to each block of the receiving side memory;
The transmission data written in each block of the receiving side memory is sequentially read in the column direction in the order of the second column, the first column, and the third column to the last column, and at the time of reading, the third column from the last column Receiving data reading means for replacing the data in the same column as the data in which the read data is replaced with the data in the previous row in the transmission side memory by the data in the next row;
A data transmission device comprising:

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