GB2248720A

GB2248720A - Capacitors for dram cells

Info

Publication number: GB2248720A
Application number: GB9101316A
Authority: GB
Inventors: Youngtae Kang; Laeku Kang
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-10-11
Filing date: 1991-01-21
Publication date: 1992-04-15
Anticipated expiration: 2011-01-21
Also published as: DE4103596A1; FR2667984B1; ITMI910245A0; ITMI910245A1; JPH0770622B2; DE4103596C2; KR930005738B1; IT1244544B; KR920008931A; JPH06342887A; GB9101316D0; FR2667984A1; GB2248720B

Abstract

In a dynamic random access memory cell array having trench and stacked capacitors, the punch-through phenomenon is prevented by providing a difference between the trench depths (11, 12) of adjacent trench capacitors. Further, the insufficient capacitance of the capacitor having a shallower trench is compensated by making the area of the electrode (15) of the associated stacked capacitor larger than the area of the electrode (16) of the stacked capacitor of the memory cell having a deeper trench capacitor. Thus, the coupling phenomenon liable to occur between the stacked capacitors can be prevented, thereby providing a DRAM cell applicable to ultra large scale integrated circuits. <IMAGE>

Description

2 2 4 3 72---) is DRAM CELL This invention relates to a dynamic random

access memory cell (Dram Cell) and a formation process thereof. In particular, it relates to a dynamic random access memory cell and a formation process thereof, in which a mixed stacked trench (MIST) type capacitor is provided.

In the field of semiconductor memories, efforts have been focused on increasing the number of memory cells. To this end, it is important to minimize the area of each cell of the memory cell array formed on a chip which has a limited area. Thus, providing one transistor and one capacitor in a memory cell in the smallest possible area is desirable. However, in a 1- transistor/1-capacitor cell, the capacitor occupies the largest part of the area. Therefore, it is important not only that the area occupied by the capacitor is minimized, but also that the capacitance of the capacitor is maximized, thereby making it possible to detect the stored data with a great reliability, and reducing the soft errors due to alpha particles.

With a view to minimizing the occupation area of the capacitor and in maximizing the capacitance, a trench type capacitor has previously been proposed. In this trench type capacitor, a cylindrical well is formed on the surface of the chip, and the capacitor electrode consists of the wall of the cylindrical well. Such a conventional trench type capacitor is disclosed in International Electron Devices Meeting, IEDM85 (PP 710713, 1985).

This trench type capacitor is formed in the following manner. A wafer in which a p epitaxial layer is grown on a high concentration P+ substrate is used, and a cylindrical well is formed into the high concentration P+ layer. Then an insulating layer is formed on the wall of the well, and an n+ polysilicon is 4286 positioned into it, while a connection is formed to the source region of the transistor thereafter.

However, in forming the above described trench type capacitor, the thickness of the epitaxial layer may be of several micrometers, and therefore, the depth of the trench has to be deep enough to obtain a proper value of the capacitance, i.e, a value of capacitance suitable for the operation of the DRAM cell. Further, a thin oxide layer is formed on the wall of the trench, but, due to the sharpness of the corners of the bottom of the trench, the insulating layer can be damaged by the voltage supplied to the polysilicon which is filled into the trench for serving as the electrode of the capacitor. 'Further, when the voltage on the polysilicon layer is varied, a strong inversion layer is formed between the above mentioned low concentration layer and the surface of the wall, thereby causing a punch through phenomenon on the adjacent capacitors.

Another technique for maximizing the capacitance with the limited memory cell has previously been proposed, and is disclosed in pages 31 through 34 of IEDM (International Electron Devices Meeting) (S. Inoue et al.) of 1989. This describes a DRAM cell using a stacked capacitor (STC), and the description also includes a spread stacked capacitor (SSC) which is an improvement over the stacked capacitor.

The above conventional techniques will be further described referring to Figures 3 and 4. Figure 3 is a sectional view of a DRAM cell having a stacked capacitor.

In the Figure, S'02 is eliminated in order to simplify the structure. Here, reference code 21 indicates a storage electrode, 22 a word line, and 23 a field oxide layer.

As shown in the drawing, the storage electrode 21 of this DRAM cell uses only its own one memory cell 4286 region, and therefore, it cannot provide a sufficient storage capacitance within its limited own cell region for a memory device having a large capacity of over 16M bits.

Figure 4 illustrates a structure in which each of the storage electrodes 31, 32, 33 occupy two memory cell regions, thereby doubling the storage capacitance of the STC type memory cell of Figure 3. In Figure 4, reference code 31 indicates a storage electrode of a first memory cell; 32 a storage electrode of a second memory cell; 33 a storage electrode of a third memory cell; 34 a bit line; 35 a common drain region; 36 and 37 word lines to serve as the gate electrodes; 38 and 39 source electrodes, and 40 a field oxide layer.

As shown in Figure 4, the two memory cells, i.e.

the first and second memory cells are formed between the field oxide layer 40 and another field oxide layer 40.

The spread stacked storage electrode 31 of the first memory cell is formed in such a manner that, in the vertical direction, it is extended between the bit line 34 and the storage electrode 32 of the second memory cell, and in the lengthwise direction, it is extended over a length equivalent to the two memory cell regions formed between the second storage electrode 32 and the third storage electrode 33.

Accordingly, the storage capacitance Cs is greatly increased because it is proportionate to the area, but the distance between the first storage electrode 31 and the second storage electrode 32 and the third storage electrode 33 may become too close, thereby causing the coupling of the electrodes to be too close, and consequently, causing disturbances in the stack structure.

An object of the present invention is to overcome the above-described disadvantages of the conventional 4286 techniques. That is, an object of the present invention is to overcome the problems of punch-through and coupling occurring respectively in the trenched capacitor and the stacked capacitor.

The intersections between electrodes have to be reduced as far as possible if the coupling phenomenon between the storage electrodes is to be reduced. Further, the step difference has to be reduced, and the trench type of capacitor has to be used if the intersections between electrodes are to be reduced whilst the capacitance is increased. Further, in using the trench, the depth of the trench is modified in order to reduce the current leakage due to the punch-through.

It is another object of the present invention to provide a capacitor structure having a storage capacitance sufficient to be applied to an ultra large scale integrated circuit (ULSI).

In achieving the above objects, according to one aspect of the present invention, a dynamic random access memory cell is provided having a single transistor and a single capacitor, and is characterized in that: the capacitor comprises a trenched capacitor, and stacked capacitor having a vertical relation to the trenched capacitor and formed on the position of the transistor; the depth of the trench of the trenched capacitor is designed to be different from the depth of the trenched capacitor of the adjacent memory cell; and the area of the stacked capacitor of the first memory cell having a shallow trenched capacitor is designed to be larger than the area of the electrode of the stacked capacitor of an adjacent second memory cell having deeper trenched capacitor.

According to another aspect of the present invention, a formation process for the DRAM cell having a single transistor and a single capacitor and having mixed 4286 trenched and stacked structure, comprises: step of forming a first trench of a required depth using a first mask when forming the trenched capacitor; step of forming a second trench having a deeper trench relative to the first trench using a second mask; and step of forming a stacked capacitor.

In the step of forming the stacked capacitor, the area of a first storage electrode of the first memory cell stacked capacitor having the first trenched capacitor is designed to be larger than the area of a second storage electrode of the second memory cell stacked capacitor having the second trenched capacitory.

Embodiments of the present invention will now be described by way of example only, with reference to the accompanying drawings, in which:

Figures 1A to 1J are sectional views showing the formation process for a DRAM cell; Figure 2 is a partly sectional perspective view of the DRAM, in which the S'02 has been removed; Figure 3 is a partly sectional perspective view of a DRAM cell having a conventional stacked capacitor, in which S'02 has been removed; and Figure 4 is a partly sectional perspective view of a DRAM cell having a conventional spread stacked capacitor, in which S'02 has been removed.

Referring to the Figures, Figure 1A illustrates the step of defining an active region and an inactive region, which step is carried out by growing a field oxide layer 2 on a P type silicon substrate in a conventional way.

Figure 1B illustrates the step in which a gate insulting layer 3 is formed by applying a thermal oxidation method and then polysilicon is spread, having a thickness of 2000 k. Then a patterning is carried out in such a manner that two memory cells should be assigned 4286 per active region, thereby forming two gate electrodes 4, the rest of the portion being removed thereafter.

Then, as shown in Figure 1C a first memory cell source region 5, a common drain 6 and a second memory cell source region 7 are formed, in such a manner that arsenic ion implantation is carried out, at a rate of approximately 5 x 1015 atoms/CM2 with an energy of 40 KeV, thereby forming the sources and the common drain.

Figure 1D illustrates the step of spreading a first insulating layer 8 upon the structure obtained through the step of Figure 1C, and in this step, Si02 is spread, having a thickness of 1000 k and in the form of an HTO (high temperature oxidation) layer.

Figure IE illustrates the step of forming a bit by spreading polysilicon to a thickness of 500 carrying out a patterning.

Figure 1F illustrates the step of forming a second insulating layer 10 on the structure obtained through the step of Figure 1E. Layer 10 has a thickness of 2000 k and is in the form of an HTO layer.

Figure 1G illustrates the step of forming a first trench 11 having shallow depth. Specifically, an exposing development is carried out using a first trench mask in order to form a trench through the source region 5 of the left first memory cell among the two memory cells disposed on the first active region. Before carrying out the exposing development, a photoresist is spread on the surface of the second insulating layer 10. Thereafter, a reactive ion etching (RIE) is carried out to form a second insulating layer 10, a first insulating layer 8 and a gate insulating layer 3, in such a manner that the insulating layer surrounding the gate 4 should line 9 and by not be etched. Succeedingly, the same kind of etching is carried out, that is, the source region 5 and the P type silicon substrate 1 are etched to form a first trench 11, 1 -7 4286 the photoresist remaining on the substrate being removed thereupon.

Figure 1H illustrates the step of forming a second trench 12, which is formed in the same manner as that of Figure 1G except that a second trench mask is used so as for the trench to be formed only through the source region 7 of the right second memory cell, and that the etching time is controlled so that the depth of the second trench 12 is deeper than that of the first trench 11.

The trench forming steps of Figures 1G and 1H can be finished in a single process by forming in advance the step difference on the portion where the trench is to be formed.

Figure 1I illustrates the step of forming a first electrode of the capacitor. An insulating layer 13 consisting of a silicon oxide layer is formed on the insides of the trenches 11, 12 formed through the step of Figure 1H; a polysilicon layer 14, to be the first electrode of the capacitor is spread by applying a CVD method; and then, a first electrode material is formed by dipping the obtained device into POC13 to diffuse phosphorus, or by implanting a phosphorus or arsenic ion into the polysilicon layer 14.

Figure 1J illustrates the step of forming a stacked storage electrode.

The right portion of storage electrode 15 of the stacked capacitor is allowed to extend in an elongate manner up to the upper portion of the gate electrode 3 of the second memory cell in order to compensate the insufficient storage capacitance of the first memory cell having a shallow trench depth; and, for the second memory cell having a sufficient trench depth, the polysilicon layer 14 is patterned in such a manner as to form the left portion of a storage electrode 16 of the stacked 4286 capacitor in a short form, thereby forming a contact opening 17, and separating the storage electrodes.

Thereafter, an insulating layer 18 made of a dielectric substance having high dielectric constant and comprising S'02 or Si02, S'3N4 and S'02 (so called ONO) films is formed on the first electrode. on the whole surface of the structure, including the insulating layer 18, there is grown a polysilicon layer 19 to serve as the second electrode, which is dipped into POC13 to diffuse phosphorus, thereby forming a second electrode material.

A DRAM cell having the mixed stacked and trenched capacitor according to one embodiment of the present invention is manufactured through the process described above.

A partly sectional perspective view showing, for clarity the insulating layer removed from the completed DRAM cell is illustrated in Figure 2. As clearly can be seen in this drawing, the depths of the trenches of adjacent memory cells are different. Accordingly, the punch-through phenomenon liable to occur between the adjacent memory cells can be inhibited, and the capacitance of the capacitor having a shallower trench depth can be compensated relative to that of the capacitor having a deeper trench depth by means of a larger capacitor area. Further, in this case, the compensation of the capacitance is achieved without the existence of a step difference and an overlapping, and therefore, there occurs no coupling between adjacent storage electrodes.

N 4286

Claims

1. A dynamic random access memory having at least a first and a second adjacent memory cell, each memory cell having a single transistor and a single capacitor, said capacitor comprising: a trenched capacitor formed in the shape of a trench; and a stacked capacitor having a vertical relation to said trenched capacitor, and formed on the place where said transistor is to be formed; wherein the depth of said trenched capacitor of said first memory cell is different from the depth of the trenched capacitor of the second memory cell, and said stacked capacitor of the first memory cell has a shallower trench depth provided with a larger electrode area than that of the capacitor of the second memory cell.

2. A dynamic random access memory as claimed in Claim 1, wherein a pair of memory cells within an active region comprises a first memory cell with a capacitor having a shallower trench depth and a larger electrode area and a second memory cell with a capacitor having a deeper trench depth and a smaller electrode area.

3. A formation process for a dynamic random access memory having a mixed trenched stacked capacitor, including the steps of: forming a first trench of a certain depth using a first mask when forming said trenched capacitor; forming a second trench having a depth deeper than that of said first trench using a second mask; and forming a stacked capacitor; wherein, in forming said stacked capacitor, the area of a first storage electrode of said stacked capacitor of a first memory cell with a first trenched capacitor of said first trench is smaller than the area of a second storage electrode of said stacked capacitor of a second memory cell with a second trenched capacitor of said second trench.

4286

4. A formation process for a dynamic random access memory as claimed in Claim 3, wherein said first and second memory cells are formed within a single active region.

5. A formation process for a dynamic random access ememory as claimed in Claim 3 or Claim 4, wherein the process of forming said first and second trenches is performed by a single etching step by providing a stepped structure in advance on the region where said trench is to be formed.

6. A DRAM having an adjacent pair of memory cells substantially as hereinbefore described with reference to, and as illustrated by, Figures 1 and 2 of the accompanying drawings.

is

7. A formation process for a DRAM substantially as hereinbefore described with reference to, and as illustrated by, Figures 1 and 2 of the accompanying drawings.