DE102005020079A1 - Hybrid memory cell for dynamic random access memory (DRAM), containing specified substrate with transistor structure(s) with drain, source, control contact and channel zone between drain and source, etc - Google Patents

Abstract

Memory cell contains drain, source, control contact (18) and channel zone (20) between drain and source in its transistor structure on device plane (10). In lower region (14) of substrate (12) is formed first capacitor structure, with first memory electrode (28) coupled to drain. Counterelectrode (30) is separated from first memory electrode by first dielectric film (32) to form first capacity. In top region (16) of substrate is formed second capacitor structure, similar to first one, using second memory electrode (34), second counter electrode (36) and second dielectric film (38).

Description

The The present invention relates to a semiconductor memory device with a high surface density.

Semiconductor memory chips and in particular DRAMs (Dynamic Random Access Memories) in the sector of highly integrated semiconductor circuits worldwide the largest market share. High cost efficiency therefore plays an essential role in the Production of DRAMs. Important prerequisites for this are the increase the number of memory chips per wafer, increasing the yield and the simultaneous Reduction of process complexity.

The increase The integration density requires a reduction of the individual Memory cells occupied chip area, i.e. the lateral extent of a single memory cell.

2A shows a conventional memory cell with a planar capacitor structure. It is at a substrate interface 102 a substrate 100 a transistor structure arranged. This transistor structure comprises a first contact region 104 , on whose extension a storage electrode 106 is formed, a second contact area 108 , one between the first contact area 104 and the second contact area 108 positioned channel area 110 and a control contact 112 , The transistor structure is designed as a field effect transistor whose gate electrode through the control contact 112 is formed.

In a complete memory chip having a plurality of such memory cells, the control contact 112 formed by the word line (word line) or is in an electrically conductive connection with this. The second contact area 108 is with a bit line 114 connected electrically conductive.

The storage electrode 106 is through a dielectric layer 116 to a counter electrode 118 electrically isolated. In this case, the storage electrode form 106 and the counter electrode 118 together with the dielectric layer 116 a storage capacitor over the channel area 110 can be loaded and unloaded. The capacitance of this capacitor structure determines the storable charge and is proportional to the capacitor area.

In This structure also requires a reduction in chip area a reduction of the area of the Spokesman transistor. A reliable one Charge storage requires a certain minimum charge on can be stored in the capacitor. At a given charging voltage Consequently, a certain minimum capacity is required. This results there are limits in reducing the chip area per memory cell.

One way of reducing the required chip area, that is to say the lateral extent of a memory cell, without reducing the capacitance of the storage capacitor is an embodiment of the capacitor as a so-called "trench cell" (or "deep trench cell"). 2 B shows such a "trench cell", where the capacitor structure is below the substrate interface 102 in a tunnel or trench-shaped recess in the substrate 100 educated. Thus, the interface between the storage electrode 106 and the counter electrode 118 essentially through the dielectric layer 116 is formed, and thus the capacity of the storage capacitor can be maintained even with a lateral reduction of the cell area. However, it is technologically difficult to produce the required deep trenches or tunnels in the substrate. Reactive Ion Etching (RIE) opens up the possibility of producing such tunnels or holes with high aspect ratios from vertical to lateral dimensioning of these tunnels.

However, as the lateral expansion of a memory cell progressively reduces due to the reduction in feature sizes, not only the technological requirements of the manufacturing process increase. Also in terms of electronic properties, this concept has limitations. Thus, with a lateral reduction of the capacitor structure, ie with a reduction in the diameter of these tunnels in the lateral direction, by a corresponding increase in the vertical extent of this structure, ie the depth of the tunnel, the electrical capacitance but not the increasing electrical series resistance can be compensated. The effective or average series resistance actually increases with increasing tunnel length. In particular, the total electrical resistance of the counter electrode increases 118 with decreasing diameter of the substrate 100 formed tunnels, which leads to an increase in the charging and discharging of the capacitor.

An alternative concept is the so-called "stacked cells". 2C shows such a cell, for example, that of the control contact 112 occupied lateral surface of the capacitor structure is thereby used, that in the vertical direction (ie perpendicular to the substrate interface 102 ) above the control contact 112 folded or at least partially arranged. By a multilayer or lamellar configuration of this capacitor structure, the electrical capacitance can be further increased. However, because of the emergence of undesirably high levels in the chip top An enlargement of the capacitor structure in the lateral direction would only be possible to a limited extent. As a result, the increase in the electrical capacity limits are set.

It It is an object of the present invention to provide a semiconductor memory device to provide that at a higher level Surface density a simultaneous increase the yield in the production of the semiconductor memory device allows.

These Task is solved by a semiconductor memory device having the features listed in claim 1. Preferred embodiments are the subject of the dependent Claims.

• – zumindest eine Transistorstruktur mit zumindest einem ersten Kontaktbereich (DRAIN), einem zweiten Kontaktbereich (SOURCE), einem Steuerkontakt und einem zwischen dem ersten und zweiten Kontaktbereich positionierten Kanalbereich, der an der Vorrichtungsebene angeordneten ist;
• – zumindest eine im wesentlichen im unteren Bereich angeordnete erste Kondensatorstruktur mit einer elektrisch leitfähigen ersten Speicherelektrode (storage node), die mit dem ersten Kontaktbereich (DRAIN) elektrisch leitfähig verbunden ist, und einer elektrisch leitfähigen ersten Gegenelektrode (cell plate), die durch eine erste dielektrische Schicht von der ersten Speicherelektrode getrennt ist, wodurch sich zwischen der ersten Speicherelektrode und der ersten Gegenelektrode eine erste elektrische Kapazität C₁ ausbildet; und
• – zumindest eine im wesentlichen im oberen Bereich angeordnete zweite Kondensatorstruktur, mit einer elektrisch leitfähigen zweiten Speicherelektrode (storage node), die mit dem ersten Kontaktbereich elektrisch leitfähig verbunden ist, und einer elektrisch leitfähigen zweiten Gegenelektrode (cell plate), die durch eine zweite dielektrische Schicht von der zweiten Speicherelektrode getrennt ist, wodurch sich zwischen der zweiten Speicherelektrode und der zweiten Gegenelektrode eine zweite elektrische Kapazität C₂ ausbildet.

Thus, according to the present invention, there is provided a semiconductor memory device comprising a substrate having a substrate normal direction and lateral directions perpendicular thereto and a device plane parallel to the lateral directions separating a lower region relative to the substrate normal direction from an upper region relative to the substrate normal direction, and at least one memory cell which includes:

• At least one transistor structure having at least a first contact region (DRAIN), a second contact region (SOURCE), a control contact and a channel region positioned between the first and second contact region, which is arranged at the device plane;
• - At least one arranged substantially in the lower region of the first capacitor structure with an electrically conductive first storage electrode (storage node), which is electrically conductively connected to the first contact region (DRAIN), and an electrically conductive first counter electrode (cell plate) by a first dielectric layer is separated from the first storage electrode, whereby a first electric capacitance C _{1 is} formed between the first storage electrode and the first counter electrode; and
• - At least one arranged substantially in the upper region of the second capacitor structure, with an electrically conductive second storage electrode (storage node), which is electrically conductively connected to the first contact region, and an electrically conductive second cell electrode (cell plate) through a second dielectric layer is separated from the second storage electrode, whereby a second electric capacitance C _{2 is} formed between the second storage electrode and the second counter electrode.

Preferably becomes the semiconductor memory device according to the invention on a flat substrate, such as a semiconductor wafer formed, the one having substantially planar process surface. The surface normal this surface falls in the process essentially together with the substrate normal direction. Preferably sets the process surface essentially fixed the device level. Preferably, the process surface extends at least essentially parallel to the device plane.

By the embodiment of a memory cell having a first and a second capacitor structure, the electrical capacity of the memory cell can be increased, without the technological limits for the production of the individual To have to stretch capacitor structures. This achieves a reduction the lateral chip area per memory cell and increased at the same time the reliability the individual process steps, which, for example, no longer operated at the lithographic resolution limit Need to become.

Thereby reduce uncertainties and manufacturing errors which increases the yield of memory cells. Even if the number of required process steps for producing a semiconductor memory device according to the invention be greater could as in conventional Storage devices, can Production costs are lowered by the technological Requirements with regard to the precision of individual process steps can be lowered. The raised Yield carries also to a reduction in the total cost of production.

In addition, the individual capacitor structures in their electrical properties independently be optimized from each other, for example, series resistors and thereby the loading and To reduce unloading times, so the possible switching speeds to increase the memory cells.

Preferably the at least one transistor structure comprises a field-effect transistor, whose gate contact is formed by the control contact. Thereby For example, the present invention may be implemented in standard logic circuits, and in particular for DRAMs Find application.

More preferably, the first and / or the second capacitor structure directly adjoins the first contact region. In particular, the first and / or the second storage electrode are connected directly to the first contact region. Thus, neither electrical lines or distribution channels nor electronic circuit components are interposed. Thus, the size of the memory cell, for example, in the lateral direction, as well the series resistances between the capacitor structures and the transistor structure are kept small.

Especially the first capacitor structure is preferably at least partially so in the substrate normal direction under the first contact area arranged that the first storage electrode and the first contact area overlap in the lateral directions. Thus, overlap the projections of the first storage electrode and the first contact region in the substrate normal direction to the device level. In substrate normal direction is the first storage electrode against the first contact area added. This allows the chip area in lateral directions at least partially simultaneously from the first capacitor structure and the transistor structure can be used.

Besides that is Preferably, the second capacitor structure at least partially arranged in the substrate normal direction above the control contact, that the second storage electrode and the control contact in the lateral Overlap directions. This will overlap the projections of the second control electrodes and the control contact in the substrate normal direction to the device level. The second Capacitor structure thus uses a part in the upper part of the Semiconductor memory device, in the substrate normal direction above the Control contact is located. Thus, the lateral chip area is at least partially simultaneously from the second capacitor structure and used the transistor structure.

In a preferred embodiment the semiconductor memory device according to the invention the first capacitor structure in a known manner as "trench cell "trained. More preferably, the second capacitor structure is stacked cell "designed. It can used the known advantages of these concepts for capacitor structures and at the same time the conventional ones Memory cells occurring in the technological boundary area disadvantages be reduced.

Preferably, the ratio C ₁ / C _{2 of} the first to second capacitance is in a range between 0.2 and 5, more preferably between 0.5 and 2, and most preferably at about 1. Thus both capacitor structures contribute significantly to the overall capacitance and thus contributing to the overall charge storage in the memory cell. As a result, the technological requirements for the manufacturing process can be reduced in a comparable manner for both capacitors and their electrical properties can be improved.

Preferably The first capacitor structure has a direction normal to the substrate extending longitudinal axis and at least partially substantially the same cross-sectional areas perpendicular to longitudinal axis on. The cross-sectional areas can do it Make circles, rectangles or any polygons. In particular, the Cross-sectional areas of a Be adapted crystal structure of the substrate. Especially preferred has the first capacitor structure at least partially substantially one Cylinder shape on.

Preferably is the extent of the first capacitor structure in the substrate normal direction in a range between 200 nm and 5 microns, more preferably between 500 nm and 2 μm.

It also lies the extent of the first capacitor structure in directions parallel to the device level, preferably in a range between 10 nm and 250 nm, more preferably between 50 nm and 100 nm.

Preferably The first dielectric layer has at least one area tubular structure on, which separates a core area and a cladding area from each other.

there In a preferred embodiment, the core region the first storage electrode and the cladding region the first counter electrode at least partially. This concept is referred to as a "burried plate." In particular could a conductive doped substrate forming the first counter electrode, preferably connected to a predetermined electrical potential (grounded substrate).

In another preferred embodiment The core region includes the first counter electrode and the cladding region the first storage electrode at least partially.

Preferably has the second storage electrode and / or the second counter electrode Ribs or lamellae, at the rib surface at least partially the second dielectric layer is arranged. The second counterelectrode preferably also has ribs or fins, which in the ribs or long waves of the first storage electrode engage and together with the second dielectric layer a form large capacitor area. Thereby, a high electric capacitance of the second capacitor structure becomes reached. Preferably, the ribs or lamellae have a longitudinal direction the type that the second capacitor device comb-like cross-sectional areas perpendicular has to this longitudinal direction.

Preferably, the extent of the Kon capacitor structure in directions parallel to the device plane in a range between 50 nm and 500 nm, more preferably between 100 nm and 250 nm.

Preferably For example, the first and / or second counter electrode comprises metal (e.g., Ti and / or TiN). More preferably, the first and / or second storage electrode comprises doped semiconductor material.

In a preferred embodiment the first and the second counterelectrode are by means of a device plane penetrating ground connection electrically conductive interconnected. The ground connection preferably comprises conductively doped semiconductor material and / or metal. By means of the ground connection, the two counterelectrodes kept at the same electrical potential.

Preferably is in the semiconductor memory device according to the invention a plurality of memory cells are provided, which are particularly preferred grid-like arranged in rows and columns. Here are special prefers the second contact areas within each row and the control contacts are electrically conductively connected within each column. In this case, the electrical connections of the second contact areas Bit lines and the electrical connections of the control contacts word lines firmly.

Preferably For example, the counter electrodes of a plurality of memory cells are electrically conductive with each other connected. It is particularly preferred for a plurality of memory cells provided a common ground connection.

The The invention will be described below with reference to the accompanying drawings preferred embodiments described by way of example. Showing:

1A - 1B FIG. 3: Cross-sectional views of a semiconductor memory device according to preferred embodiments of the invention; FIG.

2A - 2C : Cross-sectional views of conventional semiconductor memory devices according to the prior art.

1A shows a semiconductor memory device according to a first preferred embodiment of the present invention. The semiconductor memory device has a device level 10 substantially with a surface of a semiconductor substrate 12 on which the semiconductor memory device is formed may coincide. The device level 10 vertical direction is referred to as substrate normal direction. The device level 10 divides the semiconductor memory device in a lower region relative to the substrate normal direction 14 and a range upper to the substrate normal direction 16 , At the device level 10 a transistor structure is formed, which has a first contact region (DRAIN), a second contact region (SOURCE) and a control contact 18 includes. In the present embodiment, the transistor structure is designed as a field effect transistor. In this case, a channel region is between the first contact region (DRAIN) and the second contact region (SOURCE) 20 trained by a gate oxide 22 from the tax contact 18 is electrically isolated. The first (DRAIN) and the second contact region (SOURCE) are designed as n ⁺ -doped, conductive semiconductor region, which in a p-doped semiconductor layer 24 (p-well) are embedded. The channel area 20 also forms in the semiconductor layer 24 out. Preferably, the semiconductor material comprises silicon.

The second contact area (SOURCE) is electrically conductive with a bit line 26 connected. The channel area 20 is according to the invention at the device level 10 arranged. In the present case, the first contact region (DRAIN) and the second contact region (SOURCE) are also at the device level 10 arranged.

In the area below 14 a first capacitor structure is formed. This capacitor structure comprises a first storage electrode 28 a first counter electrode 30 and a first dielectric layer interposed therebetween 32 , Here is the first counter electrode 30 as n-doped conductive region of the substrate 12 designed. The first dielectric layer 32 isolates the first storage electrode 28 electrically against the first counterelectrode 30 , In this case, a first electrical capacitance C _{1 is formed} between the first storage electrode 28 and the first counter electrode 30 out.

The first dielectric layer preferably comprises silicon oxide. The first storage electrode 28 In the present case, it is designed as an n ⁺ -doped, conductive semiconductor region, which preferably comprises polysilicon. It connects directly to the first contact area (DRAIN) and is electrically conductively connected to it.

In the preferred embodiment shown, the first capacitor structure is completely in the lower region 14 arranged. It is completely below the device level 10 positioned and adjacent to this. The first capacitor structure has a substantially cylindrical structure of the cylinder with a longitudinal axis in the substrate normal direction. In particular, the first capacitor structure is designed as a "deep trench" cell is at least partially disposed in the substrate normal direction below the first contact region (DRAIN). Thus, the projections of the first capacitor structure and the first contact region (DRAIN) in the substrate normal direction overlap on the device plane 10 , As a result, the transistor structure and the first capacitor structure share regions of the lateral chip area.

In the upper area 16 The semiconductor memory device has a second capacitor structure, which is a second storage electrode 34 , a second counter electrode 36 and a second dielectric layer interposed therebetween 38 includes. The second storage electrode 34 is by means of an electrically conductive via 40 electrically conductively connected to the first contact region (DRAIN). In this preferred embodiment, the first counter electrode are located 30 and the second counter electrode 36 at the same electrical potential. In a semiconductor memory comprising a plurality of memory cells or semiconductor memory devices according to the invention, it is not necessary for each of these memory cells to be implemented 40 exhibit. The implementation 40 is preferably provided where the regular array of memory cells is interrupted, for example in the area of a so-called word line twist. Preferably, only a plurality of first counterelectrodes are in the remaining area 30 and independently a plurality of second counter electrodes 36 electrically conductive interconnected.

In the present embodiment, the second capacitor structure is completely in the upper region 16 arranged. It is at least partially in the substrate normal direction above the first contact region (DRAIN) and the control contact 18 arranged. That is, the projections of the second capacitor structure and the transistor structure in the substrate normal direction to the device level overlap at least partially. In addition, the second capacitor structure is arranged at least partially in the substrate normal direction over the first capacitor structure. Thus, the first capacitor structure, the second capacitor structure, and the transistor structure share at least partially common areas of the lateral chip area. This advantageous utilization of the lateral chip area allows a high areal storage density, without having to exhaust the spatial resolution of the lithographic steps in the manufacturing process up to the currently technologically possible limits, for example.

The second storage electrode 34 , the second dielectric layer 38 and the second counter electrode 36 are each formed as a layer having a substantially constant layer thickness. The layer sequence of the individual superimposed layers is arranged angled to require less lateral surface. This layer structure could also be folded several times in order to further increase the capacitor area.

Overall, the includes in 1A illustrated memory cell two storage capacitors, which can be charged and discharged via a field effect transistor. Consequently, at least two storage capacitors are connected in parallel in a memory cell of a semiconductor memory device according to the invention. As a result, the electrical capacitance of the memory cell is the sum of the capacitances of the individual storage capacitors. Characterized in that one of the two capacitors substantially in the lower region 14 and the other essentially at the top 16 is arranged, both capacitors can at least partially use a common lateral chip area. As a result, the capacity can be increased with a small lateral area requirement.

1B shows a second preferred embodiment of the present invention. In this embodiment, the second storage electrode 34 the second capacitor structure ribs 44 on, at the rib surface, the second dielectric layer 38 is arranged. This results in a large effective capacitor area, which leads to a high second electrical capacitance C ₂ . In a preferred embodiment, the second dielectric layer may have a high dielectric constant in order to further increase the second electrical capacitance C ₂ .

In the second preferred embodiment, the second storage electrode is adjacent 34 directly to the first storage electrode 28 at. In addition, this embodiment has an electrically conductive ground connection 44 on, which is the second counter electrode 36 with the first counterelectrode 30 electrically conductive connects and to the device level 10 penetrates.

The present invention is not limited to the embodiments shown. In particular, the transistor structure could, for example, have a vertically extending channel region, that is to say the charging current between the first contact region (DRAIN) and the second contact region (SOURCE) could flow essentially in the substrate normal direction. In another embodiment, the second capacitor structure could be in the substrate normal direction substantially above the bit line 26 be arranged. A via 40 could then be the electrically conductive connection between the second storage electrode 34 and the first contact area (DRAIN).

10

device level

12

substratum

14

lower Area

16

upper Area

18

control contact

20

channel area

22

Gate oxide

24

Semiconductor layer

26

bit

28

first storage electrode

30

first counter electrode

32

first dielectric layer

34

second storage electrode

36

second counter electrode

38

second dielectric layer

40

via

42

ribs

44

ground connection

DRAIN

first contact area

SOURCE

second contact area

100

substratum

102

Substrate interface

104

first contact area

106

storage electrode

108

second contact area

110

channel area

112

control contact

114

Bit line

116

dielectric layer

118

counter electrode

Claims (17)

Semiconductor memory device comprising a substrate ( 12 ) with a substrate normal direction and lateral directions perpendicular thereto and a device plane parallel to the lateral directions ( 10 ) having a lower portion relative to the substrate normal direction ( 14 ) from an upper area relative to the substrate normal direction ( 16 ), and at least one memory cell comprising: - at least one transistor structure having at least a first contact region (DRAIN), a second contact region (SOURCE), a control contact ( 18 ) and a channel region positioned between the first (DRAIN) and second contact regions (SOURCE) ( 20 ) at the device level ( 10 ) is arranged; At least one substantially at the bottom ( 14 ) arranged first capacitor structure with an electrically conductive first storage electrode ( 28 ), which is electrically conductively connected to the first contact region (DRAIN), and an electrically conductive first counterelectrode ( 30 ) through a first dielectric layer ( 32 ) from the first storage electrode ( 28 ), whereby between the first storage electrode ( 28 ) and the first counterelectrode ( 30 ) forms a first electrical capacitance C ₁ ; and - at least one substantially at the top ( 16 ) arranged second capacitor structure, with an electrically conductive second storage electrode ( 34 ), which is electrically conductively connected to the first contact region (DRAIN), and an electrically conductive second counterelectrode ( 36 ) through a second dielectric layer ( 38 ) from the second storage electrode ( 34 ) is separated, whereby between the second storage electrode ( 34 ) and the second counterelectrode ( 36 ) forms a second electrical capacitance C ₁₂ . 1. The semiconductor memory device according to claim 1, wherein the at least one transistor structure comprises a field-effect transistor, the gate contact of which is controlled by the control contact. 18 ) is formed. A semiconductor memory device according to claim 1 or 2, wherein the first and / or the second capacitor structure directly adjacent to the first contact area (DRAIN). Semiconductor memory device according to one of the preceding claims, wherein the first capacitor structure is at least partially disposed in the substrate normal direction below the first contact region (DRAIN) that the first storage electrode ( 28 ) and the first contact area (DRAIN) overlap in the lateral directions. A semiconductor memory device according to any one of the preceding claims, wherein the second capacitor structure is at least partially so in the substrate normal direction above the control contact ( 18 ) is arranged, that the second storage electrode ( 34 ) and the tax contact ( 18 ) overlap in the lateral directions. A semiconductor memory device according to any one of the preceding claims, wherein the ratio C ₁ / C _{2 of} the first to second capacitance is in a range between 0.2 and 5, preferably between 0.5 and 2, most preferably about 1. Semiconductor memory device according to one of the preceding Claims, wherein the first capacitor structure is one in the substrate normal direction extending longitudinal axis and at least partially substantially the same cross-sectional areas perpendicular to the longitudinal axis having. Semiconductor memory device according to one of the preceding Claims, wherein the first capacitor structure at least partially substantially has a cylindrical shape. Semiconductor memory device according to one of the preceding claims, wherein the exp tion of the first capacitor structure in the substrate normal direction in a range between 200 nm and 5 microns, preferably between 500 nm and 2 microns. Semiconductor memory device according to one of the preceding claims, wherein the extent of the first capacitor structure in directions parallel to the device level ( 10 ) is in a range between 10 nm and 250 nm, preferably between 20 nm and 200 nm, most preferably between 50 nm and 100 nm. Semiconductor memory device according to one of the preceding claims, wherein the first dielectric layer ( 32 ) has at least partially a tubular structure which separates a core region and a cladding region from each other. A semiconductor memory device according to claim 11, wherein said core portion is said first memory electrode (15). 28 ) and the cladding region the first counterelectrode ( 30 ) at least partially. A semiconductor memory device according to claim 11, wherein the core region is the first counter electrode (15). 30 ) and the cladding region the first storage electrode ( 28 ) at least partially. Semiconductor memory device according to one of the preceding claims, wherein the second memory electrode ( 34 ) and / or the second counterelectrode ( 36 ) Ribs ( 42 ) has on its rib surface at least partially the second dielectric layer ( 38 ) is arranged. Semiconductor memory device according to one of the preceding claims, wherein the extension of the capacitor structure in directions parallel to the device plane ( 10 ) is in a range between 50 nm and 500 nm, preferably between 100 nm and 250 nm. Semiconductor memory device according to one of the preceding claims, wherein the first ( 30 ) and the second counterelectrode ( 36 ) by means of a device level ( 10 ) penetrating ground connection ( 44 ) are electrically conductively connected to each other. Semiconductor memory device according to one of the preceding claims, wherein a plurality of memory cells are provided, which are arranged in raster-like rows and columns, and the second contact areas (SOURCE) within each row and the control contacts ( 18 ) are electrically conductively connected within each column.