EP1396026A2

EP1396026A2 - Dram cell arrangement with vertical mos transistors and method for the production thereof

Info

Publication number: EP1396026A2
Application number: EP02740639A
Authority: EP
Inventors: Brian Lee; Till Schlösser
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-05-29
Filing date: 2002-05-23
Publication date: 2004-03-10
Also published as: KR20040005997A; US20050253180A1; CN1513208A; WO2002097891A2; WO2002097891A3; KR100567495B1; TW569397B; DE10125967C1; CN1290198C; US6939763B2; US7329916B2; JP2004527920A; US20040259312A1

Abstract

The channel regions, which are arranged along one of the columns of the storage cell matrix, are parts of a connecting element surrounded by a gate dielectric layer. The gate electrodes of the MOS transistors of a row are parts of a strip-shaped word line. According to the invention, a vertical double gate MOS transistor having gate electrodes, which are formed in the trenches on both sides of the assigned connecting element, of the assigned word line, is provided at each point of intersection of the storage cell matrix.

Description

description

DRAM cell arrangement with vertical MOS transistors and method for their production

The invention relates to a DRAM cell arrangement with vertical MOS transistors and a method for their production, the transistors not having a so-called floating body, but should be "fully depleted".

The memory cell of a DRAM cell arrangement, that is to say a dynamic semiconductor memory, is currently used almost exclusively as the long-known one-transistor memory cell, which comprises a MOS selection transistor and a capacitor. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor in such a way that when the transistor is driven via a word line, the charge on the capacitor can be read out via a bit line.

The general aim is to produce a DRAM cell arrangement that has a high packing density. For this purpose, it is advantageous to design the MOS transistor as a vertical transistor in which the source, channel region and drain are arranged one above the other. Such a MOS transistor can have a small space requirement regardless of a channel length. Furthermore, the aim is to arrange the vertical transistor and the associated capacitor of each memory cell on top of one another on a semiconductor substrate in the vertical direction.

An arrangement of many such memory cells is known for example from DE 44 30 483 AI. Each memory cell has a column-shaped, vertically arranged selection transistor which contains a drain region and a source region in a semiconductor substrate column, a vertical region likewise extending between the drain and the source region. fender current channel runs, which is controlled by a control gate electrode, which completely surrounds the substrate column separated by an oxide layer. The control gate electrodes of different memory cells, for example made of doped polysilicon, are electrically connected to one another and form the word line for driving the selection transistor.

A particular problem with the known MOS transistor is the columnar channel region isolated from the substrate, in which charge carriers accumulate and e.g. can change the threshold voltage. The complete isolation of the active area, which is also present, for example, in SOI (silicone-on-insulator) substrates and has several advantages there, accordingly also leads to negative effects, the so-called floating body effects. These effects are caused by the fact that charge carriers generated in the active area cannot flow off. This applies in particular to charge carriers generated in a channel region of a MOS transistor.

On the other hand, in the known MOS transistors, in spite of the gate electrode surrounding the channel region, it is not ensured that the depletion zone extends from the periphery of the columnar channel region to its center, ie whether the MOS transistor is actually "fully depleted" in the sense of completely filling the channel region Is depletion zone.

A MOS transistor of the "fully depleted" type, which is increasingly desired due to its advantages, appears to be realizable at most in cases where the p-doped channel region, unlike the (planar) standard MOS transistor (in which it is not off the substrate is separated) is limited in any way. This is the case, for example, with the columnar channel region of the known transistor, or also with a planar MOS transistor on an SOI substrate. In these cases, the missing connection due to the isolation but on the other hand, as described above, lead to a situation with a floating body.

From DE 199 29 211 AI a DRAM cell arrangement and a manufacturing method are known in which the MOS transistors are designed as vertical transistors and in which floating body effects are avoided. For this purpose, the transistor there forms a bump-like projection in the substrate with a laterally adjacent gate electrode, the channel region being electrically connected to the gate electrode via a conductive structure on another side of the projection, so that charge carriers generated in the channel region can flow off. Overall, however, this known cell arrangement results in a complicated, nested structure, which is correspondingly complex to manufacture.

The invention is based on the object of creating a DRAM cell arrangement and a method for its production which offers transistors of the fully depleted type, as far as possible without a floating body, and at the same time ensure a simple production process.

This object is achieved according to the invention by a DRAM cell arrangement with the features specified in claim 1.

The invention provides a DRAM cell arrangement with vertical MOS transistors, - with a matrix arrangement of memory cells, each having a MOS transistor with an upper source / drain region, a channel region and a lower source / drain region, which as Layers are stacked one above the other and have a capacitor connected to the MOS transistor,

- In which the channel regions of the MOS transistors

Memory cell matrix are arranged in rows and columns and the channel regions arranged along one of the columns are parts of a web running horizontally in a substrate,

in which the webs are surrounded on both sides and above the upper source / drain region by a gate dielectric layer,

- In which the gate electrodes of the MOS transistors, which are arranged along one of the rows of the memory cell matrix, are parts of a strip-shaped word line which runs parallel to the row, above the webs, and which engages from above into the trenches formed in the column direction between the webs and fill it up across the width of the word line,

- So that at each crossing point of the memory cell matrix, a vertical double-gate MOS transistor with on both

Sides of the associated web in the trenches formed gate electrodes of the associated word line is provided.

The basic idea of the invention is, on the one hand, to be able to realize the transistors without further "fully depleted" by the lateral double gates of the vertical transistors, depending on the width and doping of the channel regions, and on the other hand the channel regions, via the webs connecting them, on the substrate edge to be able to contact, so that the charge carriers can flow off.

In a preferred embodiment, a DRAM cell arrangement is created

- In which each memory cell has a capacitor stacked under the MOS transistor, the capacitor with the lower one

Source / drain region is electrically connected,

- And in which above the MOS transistors, which are arranged along one of the columns, a metal bit line runs parallel to the column, which lies above the word lines and which is electrically connected to the upper source / drain regions of the associated MOS transistors , The upper source / drain regions of a column can advantageously be designed as a strip-shaped, coherent region and can be connected together to the corresponding metal bit line.

The invention further provides a method for producing a DRAM cell arrangement according to claim 1, which comprises the following steps:

- a) implanting doping ions to produce an array of upper source / drain regions on a substrate;

- b) etching the trenches using lithographically generated mask patterns in order to produce the channel regions connected to webs; - c) generation of a covering layer in the trenches and generation of a gate dielectric layer on the surfaces of the webs; d) depositing and structuring the strip-shaped word lines, with gate electrodes being produced on both sides of each MOS transistor;

- e) depositing a first wafer-bondable auxiliary layer on the front of the substrate, subsequently attaching a first auxiliary carrier substrate to this first auxiliary layer and then removing the substrate; f) implanting doping ions to produce an array of lower source / drain regions on the channel regions;

- g) Generation of shallow isolation trenches using STI technology.

This opens up the possibility of an overall simple DRAM production using the following additional steps:

- h) generation of contact structures and of contact on the front of the first subcarrier substrate lower source / drain regions of the associated MOS transistors stacked capacitors; - i) depositing a second wafer-bondable auxiliary layer on the front side of the first auxiliary carrier substrate, subsequently attaching a second auxiliary carrier substrate to this second auxiliary layer and then removing the first auxiliary carrier substrate and the first auxiliary layer; j) Forming a structured metal bit line on the front side of the second subcarrier substrate for direct electrical contacting of the upper source / drain regions.

Preferred embodiments of the DRAM cell arrangement according to the invention and their production method are described below with reference to the attached figures.

Show it:

Figure la, 2a, and 3 and 4 sectional views along the section line A-A in Figure lb to illustrate successive process steps in the manufacture of the DRAM cell arrangement according to the invention;

FIGS. 1b and 2c are top views of DRAM cell arrangements produced according to the invention in the process steps according to FIGS. 1a and 2a;

Figure 2b is a sectional view taken along section line B-B in Figure 2c.

The individual process steps for producing the DRAM cell arrangement according to the invention are described below with reference to FIGS. 1 to 4. An arrangement (matrix) of four memory cells can be seen in FIG. 1b, the strip-shaped word lines 10 (gate) in the view according to FIG strip-shaped, column-defining upper source / drain regions 4 each run above the transistors which are arranged in one of the columns. The section through this cell arrangement along the line AA indicated in FIG. 1b is shown in FIG. As will be explained in more detail below, it is advantageous in terms of production technology to start from an SOI substrate, that is to say from a substrate 1 with an overlying p-silicon layer 3 to be structured and an intermediate, buried oxide layer 2.

On the SOI wafer, i.e. As can be seen in FIG. 1 a, an array of upper n-doped source / drain regions 4 is first produced on the p-silicon layer 3 by implantation. Advantageously, further implantations (tub array, periphery, etc.) and trench isolation using STI (shallow trench isolation) technology for the periphery can be carried out at this point in the process.

Subsequently, the (dry) etching of the trenches 5 running in the column direction takes place by means of lithographically generated mask patterns, so that continuous webs 7 (see FIG. 2b) delimited by the trenches 5 are made of p-silicon. In the row direction, cf. FIG. 1a, the channel regions 6 of the transistors arranged next to one another result.

In the next step, silicon nitride, for example, is deposited, planarized by means of a CMP process and then etched back, so that nitride layers are produced in the trenches 5, which later serve as a covering layer 8. The gate oxide 9 is then produced on both sides and above the webs 7, possibly with regard to the transistors can be carried out separately in the cell field and in the periphery. The gate oxide 9 can be produced in particular with the aid of a thermally grown oxide layer.

In the next process step, the strip-shaped word lines 10 are deposited, lithographically structured and etched. The conductive material, for example doped polysilicon, tungsten, silicon nitride or a layer system with an intermediate tungsten nitride layer, also fills the trenches 5 so that the gate electrodes 11 and 12 arise. After the etching of the wordline 10, further SiN depositions and etching, in particular for the production of spacers, can be carried out. In addition, other source / drain regions in the periphery z. B. implanted for the production of logic circuits on the chip.

Finally, a first wafer-bondable auxiliary layer 13, typically an oxide layer (however, a BPSG layer is also possible), can be deposited on the top of the substrate 1 and, if necessary, planarized, so that the production state shown in FIG.

In a further process step, a wafer bonding step, a first auxiliary carrier substrate 14 is attached or glued to the planarized auxiliary (oxide) layer 13. This can be done by heating the opposite surfaces and then joining them together. After the interfaces have been joined and cooled, an insoluble chemical bond is formed between the auxiliary (oxide) layer 13 and the first auxiliary carrier substrate 14 after a predetermined period of time.

The processing of the resulting structure is carried out for the further process steps (initially) from the opposite side. For this purpose, the entire structure is “turned over” and the substrate 1, which is now on top, is etched away by wet etching, the buried oxide layer 2 advantageously serving as an etching stop. Through chemical mechanical planarization CMP or by a further etching step, the buried oxide layer 2 is further removed, the previously generated cover layer 8, in particular a silicon nitride layer, being used to stop these processes in front of the gate oxide 9.

In the now exposed surface, cf. Figure 2a, the previous back, doping ions are implanted to produce an array of lower source / drain regions 15 on the channel regions 6. Then, cf. 2b and c, flat isolation trenches 16 are produced in the form of stripes in the usual manner (lithography, etching, oxide deposition, CMP), since the lower source / drain regions, unlike the upper regions, are electrically separated have to.

The production state shown in FIG. 2 is thus achieved. The basic idea of the invention can be seen most easily in the overview of FIGS. 2a and 2b, which each show a section in mutually perpendicular cutting directions along one of the two lines indicated in the top view according to FIG. 2c.

The vertical MOS transistors can be clearly seen in FIG. 2a, each comprising an upper and lower source / drain region 4 and 15 and a channel region 6 running vertically therebetween, and the gate oxide 9. Laterally, ie to the left and right of the channel regions 6, gate electrodes 11 and 12 are formed in the trenches 5, which are connected to one another by the strip-shaped word line 10.

According to the invention, these are vertical transistors with lateral double gates, so that on the one hand, depending on the width and doping of the channel regions 6, it is easily possible to implement the transistors "fully depleted". The transistors are connected to one another in the row direction in such a way that each transistor laterally has two gate electrodes 11 and 12, and each gate electrode in a trench 5 can also be assigned to two adjacent transistors. On the other hand, the vertical transistors are connected to one another in the column direction, cf. Figure 2b that the channel areas 6 are formed as a continuous web 7. The transistors, more precisely the channel regions 6 of the transistors in a column, therefore do not form individual silicon columns which are insulated from one another, but instead form a wall-like structure, namely the web 7. These structures can either assume a substrate-like character due to their size or in any case open up the possibility of contacting on the substrate edge. By means of the channel regions 6 placed on ground by contacting at the substrate edge, floating body effects can be substantially reduced or completely avoided.

It makes sense to produce cell arrangements with memory cells, each of which comprises a vertical transistor, a capacitor arranged underneath and a metal bit line arranged above the transistor. The following additional steps are essentially required:

First, contact structures 17 and, above, stack capacitors are produced on the front side of the first auxiliary carrier substrate 14. The contact structures 17 each connect the lower source / drain region 15 of each transistor to the first electrode 18 of the capacitor stacked under the transistor. A dielectric 19, for example tantalum pentoxide, in each case separates the first electrode 18 from the counter electrode of the capacitor, which is designed and connected as a common capacitor plate 20. In the case of the stacked capacitor, all conventional embodiments (box, cylinder, etc.) are possible, as are the materials, with metal electrodes and dielectrics with a very high dielectric constant being preferred. All in all, capacitors with a simple, low-impedance connection and without any restrictions in the aspect ratio due to the metallization, as would be associated with trench capacitors, are possible. After the stacked capacitors have been produced, a second auxiliary (oxide) layer 21 is in turn deposited above the capacitors and a second auxiliary carrier substrate 22 is attached or glued in a wafer bonding step. The entire structure is then turned over again so that metal bit lines 23 and contacts (not shown) can now be produced on the front side of the subcarrier substrate 22 using conventional method steps.

The DRAM cell arrangement according to the invention shown in FIG. 4, which, after “turning” twice, now has the desired arrangement (substrate, above that the buried capacitor, above that the vertical transistor and above the metal bit line), offers a very high degree of integration due to the vertically arranged selection transistors and the capacitors stacked underneath. A memory cell is approximately the size of 4F ² , the smallest lithographic size being F <0.2 μm.

The production process for producing the DRAM cell arrangement according to the invention is very simple, especially with regard to lithography (use of stripe masks) and in particular has a very simple metallization process.

In particular, the multiple use of wafer bonding in the process enables the principle advantages of trench technology (simple metallization, easy integration of vertical transistors, since capacitance and metallization are in different directions from the device point of view) and stack technology (process order) descending thermal budget: device, capacitor, metallization).

Claims

claims

1. DRAM cell arrangement with vertical MOS transistors,

- With a matrix arrangement of memory cells, each having a MOS transistor with an upper source / drain region (4), a channel region (6) and a lower source / drain region (15), which are stacked as layers , and have a capacitor (18, 19, 20) connected to the MOS transistor,

- in which the channel regions (6) of the MOS transistors of the memory cell matrix are arranged in rows and columns and the channel regions (6) arranged along one of the columns are parts of a web (7) running horizontally in a substrate (1),

- in which the webs (7) are surrounded on both sides and above the upper source / drain region (4) by a gate dielectric layer (9),

- In which the gate electrodes (11, 12) of the MOS transistors, which are arranged along one of the rows of the memory cell matrix, are parts of a strip-shaped word line (10) which runs parallel to the row, above the webs (7), and which reaches into the trenches (5) formed between the webs (7) in the column direction and fills them up over the width of the word line (10),

- So that at each crossing point of the memory cell matrix a vertical double gate MOS transistor with gate electrodes (11, 12) of the associated word line (10) formed in the trenches (5) on both sides of the associated bridge (7) is provided ,

2. DRAM cell arrangement according to claim 1,

each memory cell has a capacitor (18, 19, 20) stacked under the MOS transistor, which is electrically connected to the lower source / drain region (15), - And in which above the MOS transistors, which are arranged along one of the columns, a metal bit line (23) runs parallel to the column, which lies above the word lines (10) and which has the upper source / drain regions (4) the associated MOS transistors is electrically connected.

3. DRAM cell arrangement according to claim 2, in which an auxiliary carrier substrate (22) is provided, with the interposition of a wafer-bondable auxiliary layer

(21) below the capacitors (18, 19, 20) is arranged.

4. A method for producing a DRAM cell arrangement according to claim 1, comprising the following steps: - a) implanting doping ions to generate a

Arrays of upper source / drain regions (4) on a substrate (1);

- b) etching the trenches (5) by means of lithographically generated mask patterns to produce the channel regions (6) connected to webs (7);

- c) Generation of a cover layer (8) in the trenches (5) and generation of a gate dielectric layer (9) on the surfaces of the webs (7);

- d) depositing and structuring the strip-shaped word lines (10), gate electrodes (11, 12) being produced on both sides of each MOS transistor;

- e) depositing a first wafer-bondable auxiliary layer (13) on the front of the substrate (1), subsequently attaching a first auxiliary carrier substrate (14) to this first auxiliary layer (13) and then removing the substrate (1); f) implanting doping ions to produce an array of lower source / drain regions (15) on the channel regions (6); - g) Generation of shallow isolation trenches (16) using STI technology.

5. The method according to claim 4 with the following additional steps:

- h) Generation of contact structures (17) and of capacitors (18, 19, 20 stacked on the front of the first subcarrier substrate (14) in contact with the lower source / drain regions (15) of the associated MOS transistors ); i) depositing a second wafer-bondable auxiliary layer (21) on the front side of the first auxiliary carrier substrate (14), subsequently attaching a second auxiliary carrier substrate (22) to this second auxiliary layer (21) and then removing the first auxiliary carrier substrate (14) and the first auxiliary layer (13); - j) Forming a structured metal bit line (23) on the front of the second subcarrier substrate (22) for direct electrical contacting of the upper source / drain regions (4).

6. The method according to claim 4 or 5, in which in the process step

- a) an SOI substrate (1, 2, 3) is used and in which at the end of process step e) the silicon substrate (1) is first etched back or split off and then the buried oxide layer (2) of the SOI substrate (1 , 2, 3) is removed.