GB2247965A

GB2247965A - Dual-port memory device with redundancy

Info

Publication number: GB2247965A
Application number: GB9020183A
Authority: GB
Inventors: Jang-Kyu Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-09-14
Filing date: 1990-09-14
Publication date: 1992-03-18
Anticipated expiration: 2010-09-14
Also published as: GB2247965B; FR2666917B1; DE4029247A1; FR2666917A1; DE4029247C2; GB9020183D0

Abstract

A dual-port memory device for split data transfer comprises: a first normal memory pan comprising a first RAM 20, a first SAM 22 and a first transfer gate 24 connected for memory data transfer between them, a second normal memory pan comprising a second RAM 30, a second SAM 32 and a second transfer gate 34 connected for memory data transfer between them; a transfer memory signal generator 40 for providing first and second transfer signals to the first and second transfer gates respectively; and a redundant memory 50 comprising a redundant RAM 60, a redundant SAM 62, a redundant transfer gate 64 and a redundant transfer signal generator 70 for selecting one of the first and second transfer signals so that if a defect arises in either memory pan the redundant memory can substitute therefor. <IMAGE>

Description

1 DUAL-PORT MEMORY DEVICE This invention relates to a dual-port memory

device with RAM (Random Access Memory) and SAM (Serial Access Memory) ports, more particularly, a dual-port memory device which also comprises a redundant circuit. The dual-port memory device has one or more RAM and SAM ports comprising respective memory cell array blocks. Dual-port memory devices have been developed to be used as VRAMs (video RAMs) for graphic display.

In a conventional DRAM (Dynamic RAM), when data are transferred from a processor to a peripheral device, the data are first transferred to a memory and subsequently the peripheral device accesses the transferred data from the memory. In that case, the processor is unable to transfer the data to the memory whilst the peripheral device is accessing data from the memory.

However, with the dual-port memory, the peripheral device carries out the access of the transfered data in the memory through a second RAM port, while data are transferred to the memory through a first SAM port. SAM port has a fast access time so that the VRAM is suitable for the high resolution and the high speed required for graphic display.

In order for a conventional dual-port memory device to operate in split transfer mode, the normal memory is divided into upper and lower parts. The lower part can be termed a first normal memory part and the upper part, a second normal memory part. A SAM of the second normal memory carries out a read transfer operation RT or a write transfer operation WT while a SAM of the first normal memory part carries out a read operation or a write operation.

2 For a conventional memory device which is not divided for split transfer operation, a redundant circuit can be provided to prevent reduction of the data transfer capacity if a defect arises in a certain part of the normal memory. The redundant circuit is then connected instead of the defective normal memory to maintain the correct operation. Thus, a first and a second transfer signal are required to regulate split data transfer between the first and the second normal memory parts.

It will be apparent that for split transfer operation, both first and and a second redundant circuits are actually required so that a respective redundant circuit can be connected instead of the first and/or the second normal memories when the latter become defective. This, however, has the disadvantage that the overall size of the memory device must be enlarged for providing both first and second redundant circuits.

We have now found a way in which a dual-port memory device can be provided with a single redundant circuit to compensate in the event of a defect in one of the first and the second normal memories.

Thus, the present invention provides a dual-port memory device for splitdata transfer and comprising:

a first normal memory part comprising a first RAM, a first SAM and a first transfer gate connected for memory data transfer between said first RAM and first SAM; a second normal memory part comprising a second RAM, a second SAM and a second transfer gate connected for memory data transfer'between said second RAM and second SAM; 3 a transfer memory signal generator for providing first and second transfer signals to said first transfer gate and second transfer gate respectively; a redundant memory comprising a redundant RAM, a redundant SAM, and a redundant transfer gate connected for memory data transfer between said redundant RAM and redundant SAM and a redundant transfer signal generator for selecting one of said first and second transfer signals so that if a defect arises in said first or second memory parts, the redundant memory can substitute therefor.

The invention will now be explained by the following description of a preferred embodiment, with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of a dual-port memory device according to the present invention; and Fig. 2 is a detailed circuit diagram of the redundant transfer signal generator illustrated in Fi g. 1.

In Fig. 1 a dual-port memory device comprises at least one normal memory 10 and a redundant memory 50. The normal memory 10 includes a RAM part having a first and second RAM, 20 and 30, a SAM part having a first and second SAM, 22 amd 32, a first and a second memory transfer gate 24 and 34 respectively interposed between the first RAM and the first SAM and between the second RAM and the second SAM. A memory transfer signal generator 40 is provided for generating respective transfer signals and providing them to the first and the second memory transfer gates 22 and 32.

The redundant memory 50 includes a redundant RAM 60, 4 a redundant SAM 62, a redundant memory transfer gate 64 interposed between the redundant RAM 60 and the redundant SAM 62, and a redundant transfer signal generator 70 interposed between the redundant transfer gate 64 and the first and second memory transfer gates 24 and 34.

The normal memory 10 may be regarded as comprising a first normal memory part made from the first RAM 20 and the first SAM 22 and a second normal memory part made from the second RAM 30 and second SAM 32. In operation, the first SAM 22 is in the access state if the MSB (Most Significant Bit) of a relevant address is 10, (logic low), while the second SAM 32 is in the access state if the MSB of the address is 11, (logic high).

When the first SAM 22 is in the access state, the data transfer is carrried out in the second SAM 32. On the other hand, if the second SAM 32 is in the access state, the data transfer is carried out in the first SAM 22. First and the second transfer signals are generated by the memory transfer signal generator 40 and are provided to the first and the second memory transfer gates 24 and 34, respectively. The first and second transfer signals are multiplexed with the MSB of the aforementioned address and provided to the first and the second memory transfer gates 24 and 34 respectively. These multiplexed signals turn the memory transfer gates 24 and 34 on and off, respectively.

For example, if the MSB of the address is 111, the first transfer signal is multiplexed with it, thereby to turn on the first memory transfer gate 24. Then, the first normal memory part comprising the first RAM 20 and the first SAM 22 operates in RT mode or the WT mode, while the second normal memory part comprising the second RAM 30 and the second SAM 32, carries operates in read mode or write mode and the signals to be provided to the first and the second memory transfer gates 24 and 34 are also provided to the redundant transfer signal generator 70.

In the redundant transfer signal generator 70, the first of the transfer signals to turn on the redundant transfer gate 64 in response to a defect is selected. Then, the redundant memory 50 comprising redundant RAM 60 and the redundant SAM 62 effects data transfer, thereby to substitute for the defective part of the first normal memory.

Referring now to Fig. 2, the redundant transfer signal generator 70 comprises a fuse circuit 72 and a transfer signal selector circuit 74. When a defect occurs in part of the normal memory 10, the fuse circuit 72 provides the MSB of a redundant address RCAm (which is always logical 111) in response to both the MSB of a fundamental address CAm and to a redundant enable signal RE which takes on the value 11, when said defect occurs.

The transfer signal selector circuit 74 selects either of the first or second transfer signals to be the redundant transfer signal according to the MSB of the fundamental address CAm and the MSB of the redundant address RCAm.

First, the first normal memory part effects data transfer if the MSB of the fundamental address CAm is 111, but if a defect is detected, data transfer is interrupted and the RE signal changes to 111. Then, the RE signal 11, is applied to each gate of two NMOS transistors N1 and N2 and the RE signal is inverted to 101 by an inverter 12 and is then applied to each gate of an NMOS transistor N5 and two PMOS transistors PI and P2, whereby the NMOS transistor N5 is turned off and the 6 other transistors N1, N2, P1 and P2 are turned on to establish an initial value.

Thus, the MSB of the fundamental address CAm provides the MSB of the redundant address RCAm to a node 77 through the transistors N1 and P1 and a first fuse Fl, or through an inverter Il, the transistors N2 and P2, and a second fuse F2. Since the MSB of the redundant address RCAm must always be Ill, the second fuse F2 cuts off and the MSB of the fundamental address CAm is transferred through the first fuse Fl. The MSB of the redundant address RCAm, ie Ill, is applied to an input terminal of a NAND- gate NA1 and an ORgate OR.

Also, the MSB of the fundamental address CAm, ie 111 is applied to each of the other input terminals of the NAND-gate NA1 and the ORgate OR. Thus, the NAND-gate NA1 and the OR-gate OR provide 101 and 111 respectively to inut terminals of a NAND-gate NA2. The NAND-gate NA2 provides the output 111 to each gate of a PMOS transistor P3 and an NMOS transistor N4.

Further, the output of the NAND-gate NA2 is inverted by an inverter 13 and this inverted output is applied to each gate of a PMOS transistor P4 and NMOS transistor N3. Thus, the transistors P4 and N4 are turned on to provide the first transfer signal to the redundant transfer gate 64. Then, the redundant transfer gate 64 is turned on so that the redundant RAM 60 and the redundant SAM 62 can accomplish the data transfer instead of the defective first normal memory part.

On the other hand, if the second normal memory part is carrying out the data transfer, the MSB of the fundamental address CAm is logical 101. Thus, if the defect occurs in the second normal memory part, the first fuse F1 of the redundant transfer signal generator 7 cuts off. Then, the PMOS transistor P3 and the NMOS transistor N3 are turned on to provide the second transfer signal to turn on the redundant transfer gate 64. The redundant RAM 60 and the redundant SAM 62 then substitute the data trasfer function for the defective second normal memory part.

To summarise, in the dual-port memory device of the present invention, if a defect occurs in one or other normal memory parts, the respective first or second transfer signal corresponding to the defective normal memory part is selected by the redundant transfer signal generator. The transfer signal selected, turns on the redundant transfer gate to substitute the data transfer function to the redundant RAM and the redundant SAM isntead of the relevant defective normal memory part. Thus, the present invention provides the advantage of a single redundant circuit to substitute for whichever part of the normal memory proves defective during split data transfer. This enables fabrication of a smaller dual-port memory device than would otherwise be the case.

The invention is not limited to the embodiment described hereinabove. Various modifications as well as other embodiments of the invention will readily be apparent to persons skilled in the art upon reference to the above description of the invention. Any modifications or embodiments will fall within the scope of the invention, as defined by the appended claims.

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Claims

1. A dual-port memory device for split-data transfer and comprising..

a first normal memory part comprising a first RAM, a first SAM and a first transfer gate connected for memory data transfer between said first RAM and first SAM; a second normal memory part comprising a second RAM, a second SAM and a second transfer gate connected for memory data transfer between said second RAM and second SAM; a transfer memory signal generator for providing first and second transfer signals to said first transfer gate and second transfer gate respectively; a redundant memory comprising a redundant RAM, a redundant SAM, and a redundant transfer gate connected for memory data transfer between said redundant RAM and redundant SAM and a redundant transfer signal generator for selecting one of said first and second transfer signals so that if a defect arises in said first or second memory parts, the redundant memory can substitute therefor.

2. A dual-port memory device according to claim 1, wherein said redundant transfer signal generator comprises a fuse circuit providing the MSB of a redundant address and having the logical value 111 irrespective of the MSB of an input address enabled by a redundant enable signal when the defect occurs, and a redundant signal selector for selecting either the first or second transfer signal according to the MSB of an input address and that of the redundant address and providing it as a redundant transfer signal.

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3. A dual-port memory device according to claim 2, wherein said redundant enable signal always has the logical value 111 if the effect occurs in said first or second normal memory part.

4. A dual-port memory device according to Claim 2 or claim 3, wherein the MSB of the input address has the logical value 1 01 or 1 11.

5. A dual-port memory device according to claim 4, wherein the MSB of the redundant adddress is provided by the cutting off of a second fuse when the MSB of the input address is 11', and by the cutting off of a first fuse when the MSB of address is 101

6. A dual-port memory device according to claim 5, wherein said first fuse is connected to an inverter and said second fuse is not connected to the inverter.

7. A dual-port memory device substantially as hereinbefore described with reference to the accompanying drawings.

Published 1992 at The Patent Office. Concept House, Cardiff Road. Newport. Gwent NP9 1RH. Further copies may be obtained from Sales Branch. Unit 6. Nine Mile Point. Cwmfelinfach. Cross Keys. Newport, NP1 7HZ. Printed ky Multiplex techniques lid. St Mary Crky. Kent.