GB2240889A - Clamping circuit - Google Patents

Abstract

A clamping circuit comprises a pair of operational amplifiers A1, A2 where the input signal at A has its d.c. level removed at capacitor C1 and a reference signal is applied to the non-inventing input of amplifier A2. The voltage at C cannot rise above zero since the output of the operational amplifier would fall by a corresponding amount and the peaks of waveform are therefore clamped to zero. With amplifiers A3, A4 the signal at D cannot fall below the reference signal at the non-inventing input of A4 and is therefore clamped to zero or some pre-set fixed level at the peaks of reference signal, which is the voltage at point C. Diode D3 conducts when voltage at C attempts to go positive to pull voltage at B to zero as the output of A2 is negative. When C goes negative, diode D4 conducts to keep A2 in active mode. <IMAGE>

Description

Clamping Circuit This invention relates to clamping circuits.

Diode clamping circuits are known, but suffer from disadvantages, such as a finite turn-on voltage.

The invention provides a clamping circuit comprising a differential amplifier, a reference voltage being connected to one input and the signal to be clamped to the other input, first rectifying means being connected between the signal voltage input and the output of the differential amplifier, and second rectifying means being connected between the input and output of the differential amplifier.

The differential amplifier prevents the turn-on voltage of the first rectifying means from impairing its clamping the signal voltage, while the second rectifying means maintains the differential amplifier in its active mode at all times, and hence promotes a rapid response of the clamping circuit.

The reference voltage may be connected to the non-inverting input of the differential amplifier, and a buffer such as an operational amplifier or other voltage follower may be connected between the input and output of the amplifier.

A clamping circuit constructed in accordance with the invention will now be described by way of example with reference to the accompanying drawing, which is a circuit diagram of the clamping circuit.

The purpose of the clamping circuit is to clamp the voltage at point D to zero volts or any fixed pre-determined voltage at the point in its waveform which coincides with the voltage at point A being a maximum. The clamping circuit may be used in an envelope amplitude error correction circuit as described in our co-pending British patent application number 9002788.9.

The circuit includes two clamping circuits, each including a pair of operational amplifiers Al, A2 and A3, A4, together with a pair of diodes, D3, D4 and D5, D6.

In the first clamping circuit the voltage shown at point A is to be clamped with a zero level at the peaks of its envelope, as shown at point C. The d.c.

component of the waveform at A is removed by capacitor C1. The buffer Al has a 100% feed back and unity again, and the voltage at point C therefore follows the voltage at point B.

The operational amplifier A2 compares the voltage at point C with a reference voltage of zero (or in general with any fixed d.c. level), the non-inverting input of the amplifier A2 being grounded. If the voltage at point B attempts to go positive, the voltage at point C also attempts to go positive by the same amount, and, since this is fed to the inverting input of the operational amplifier A2, the output attempts to go negative by the same amount, with the result that diode D3 pulls the voltage at B down to zero. In other words the voltage at point B and C can never exceed zero volts. If the voltage at B attempts to go negative, this is not counteracted since the negative voltage at C creates a positive voltage at the output of A2, but this cannot pass diode D3. Instead, diode D4 conducts and A2 is always kept in its active mode i.e. it never overloads.This prevents the generation of spikes due to recovery from overload, which could otherwise appear on the output.

The voltage signal clamped at zero volts at point C is used in an inverse form of the clamp consisting of amplifiers A3 and A4. Again, capacitor C2 removes the d.c. component of the voltage to be clamped shown at point D. The diodes are connected in the reverse sense to the clamp of amplifiers Al and A2 with the result that, if the non-inverting input of amplifier A4 was connected to zero, the voltage at E and F would never fall below zero. If point E and point F attempted to go negative, the output of the amplifier would go positive by the same amount. However the non-inverting input of A4 is actually connected to clamped voltage at point C, and the circuit therefore operates so that the voltage at point F can never fall below the voltage at point C.

The result of this is that the voltage at point F is clamped at zero at the points at which the voltage at C is zero (or, in general, some pre-set level) i.e. the peaks of the waveform at point A and point C.

Claims (6)

1. A clamping circuit comprising a differential amplifier, a reference voltage being connected to one input and the signal to be clamped to the other input, first rectifying means being connected between the signal voltage input and the output of the differential amplifier, and second rectifying means being connected between the input and output of the differential amplifier.

2. A clamping circuit as claimed in claim 1, in which the reference voltage is connected to non-inverting input of the differential amplifier.

3. A clamping circuit as claimed in claim 1 or claim 2, in which there is a buffer between the input and output of the amplifier.

4. A clamping circuit as claimed in claim 3, in which the buffer is an operational amplifier.

5. A clamping circuit as claimed in any one of claims 1 to 4, including a second differential amplifier, third rectifying means being connected between the output of the second differential amplifier and an input of the second differential amplifier for a second signal voltage to be clamped at particular times only, the other input of the second differential amplifier being connected to the input of the first differential amplifier to be clamped, the clamping instants of the second signal voltage depending on the first clamped signal.

6. A clamping circuit substantially as herein described with reference to the accompanying drawings.