GB2239115A

GB2239115A - Direct dividing frequency synthesiser

Info

Publication number: GB2239115A
Application number: GB8928411A
Authority: GB
Inventors: Michael James Underhill
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1989-12-15
Filing date: 1989-12-15
Publication date: 1991-06-19
Also published as: GB8928411D0

Abstract

A direct dividing frequency synthesiser comprises a dual modulus frequency divider (12) for dividing a clock frequency (Fc) selectively by an integer (n) or (n+1), where n is the integer part of the divisor (n+0.m). The output (Fin) of the frequency divider (12) is applied via a delay modulator (14) to a rate multiplier (16). In the rate multiplier (16) the frequency of the signal (Fo) is multiplied by the fractional part (n+0.m) of the divisor (n+0.m). An output of the rate multiplier (16) is applied to a modulus control input (18) of the frequency divider (12) and the state of a signal (Fs) on the modulus control input (18) determines whether the frequency division is by (n) or (n+1). A phase error circuit (20) is provided to derive phase errors based on the excess or accumulated value in the rate multiplier (16) and to provide phase error samples. The delay modulator (14) converts these samples to time displacements which are used to delay transitions in the signal (Fin) by an amount to remove jitter. <IMAGE>

Description

DESCRIPTION DIRECT DIVIDING FREQUENCY SYNTHESISER The present invention relates to a direct dividing frequency synthesiser of a type where the output waveform transitions are generated directly from a clock generation.

A known direct frequency synthesiser is described and claimed in British Patent Specification 2062315B (Applicant's reference PHB 32678). This known frequency synthesiser selects pulses from a clock pulse source, of higher pulse frequency (Fc) than the required output frequency (Fo), in order to provide said frequency Fo. The synthesiser includes an adjustable accumulator of the type which, for each input clock pulse thereto, adds a preselected adjustable increment Y to the accumulated value in the accumulator and gives an output pulse each time an accumulated value C (where C is equal to or greater than Y) is reached or exceeded, any excess being left as a residue Rn in the accumulator.The synthesiser further includes delay means for delaying each output pulse from the accumulator for a respective period which is calculated using the function (1-Rn/Y)Fc to produce a jitter free signal at the desired frequency Fo. This calculation is carried out each time a pulse appears on the output of the accumulator. To allow time for the analogue voltages involved to settle after the appearance of an output pulse from the accumulator a constant period K is added to the delay calculated. The necessity to carry these calculations together with having to add the constant period K not only complicates the operation of the frequency synthesiser, especially when scanning successive channels, but also imparts a limitation on the maximum value of Fo which can be generated.

However, an advantage of this known direct frequency synthesiser is that it is readily suited to producing frequencies which are a multiple of a fixed fraction of the clock frequency, such frequencies are required in many multichannel applications where the channel spacing is fixed.

An object of the present invention is to be able to correct for jitter in the output frequency of a frequency synthesiser in a simpler way than is effected in the known frequency synthesiser.

Another object of the present invention is to provide a direct dividing frequency synthesiser which is able to produce sufficiently accurate multiples of a fixed fraction of the clock frequency without excessive circuit complexity.

According to the present invention there is provided a direct dividing frequency synthesiser in which phase corrections for phase errors in the division process are derived from a fractional part of the division process.

The present invention also provides a direct dividing frequency synthesiser comprising a clock source, dividing means for dividing a signal derived from the clock source by a number having an integer part (n) and a fractional part (O.m) to give a desired output frequency, means for deriving signals representative of the phase errors produced as a result of the fractional part of the division operation and delay modulating means arranged in the signal path between the clock source and a signal output, the delay modulating means having a control input to which, in operation, signals representative of the phase errors are applied and an output for signals which have been delayed in response to the values of the signals representative of the phase errors, whereby the signals at said desired output frequency are substantially free of phase errors.

Compared to known dividing frequency synthesisers, a frequency synthesiser made in accordance with the present invention is truly a direct dividing frequency synthesiser because the output frequency is derived directly from dividing down a stable clock source frequency. The accuracy of the output frequency is dependent only on the accuracy by which the divisor can be defined, for example if the fractional part is defined by a 32 binary bits then for a clock frequency of 200MHz the accuracy can be of the order of 0.47Hz.

The dividing means may comprise a dual modulus dividing means for dividing a signal on its input by (n) or (n+1) and a rate multiplier for multiplying a signal on its input by the fractional part (O.m).

In one arrangement of the frequency synthesiser made in accordance with the present invention, the delay modulating means is coupled between the dual modulus dividing means and the rate multiplier. A useful feature of such an arrangement is that the phase correction of a phase error is carried out under stable conditions because until the delay modulating means produces an output signal there will be no change in the signal conditions pertaining to the rate multiplier.

In another arrangement of the frequency synthesiser made in accordance with the present invention the rate multiplier and the delay modulating means have inputs coupled to an output of the dual modulus dividing means. Unless some precautions are taken it is possible for the phase error as derived from the rate multiplier to change at the same time as the delay modulating means is effecting a phase correction due to a transition being produced by the dual modulus dividing means. One such precaution comprises delaying or buffering the signals representative of the phase errors which are applied to the delay modulating means.

In an embodiment of the present invention the dual modulus dividing means has a modulus control input, the state of a signal on the modulus control input determining whether the division is by (n) or (n+1), wherein the rate multiplier has a signal output coupled to the modulus control input of the dual modulus dividing means.

In another embodiment of the present invention the dual modulus dividing means comprises a fixed divider for dividing an input signal by (n), a pulse subtractor being responsive to a signal on a modulus control input indicative that the divisor should be (n+l), to subtract one clock transition from the input signal from the clock source whenever the said modulus control signal is present, and wherein the rate multiplier has a signal output coupled to the modulus control input of the dual modulus dividing means.

The means for deriving the phase errors may have an input connected to the rate multiplier.

The rate multiplier may be an addition rate multiplier comprising an accumulator in which, in response to each transition thereto, a programmable increment is added to a value in the accumulator. An output signal is produced each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulaor, the excess or accumulated value in the accumulator being representative of the phase error.

The rate multiplier may alternatively be a binary rate multiplier. A d.c. removal stage may be coupled to an output of the binary rate multiplier. An output is coupled to an integrating means which produces the phase error signal. A binary rate multiplier is simpler to implement compared to an addition rate multiplier but does not have the same precision as the addition rate multiplier.

In view of the fact that the delay introduced by the delay modulator is a function of the clock frequency which is fixed rather than a function of the output frequency which can be varied, the gain of the delay modulating means can be preset to a constant value which minimises the phase jitter on the output pulses irrespective of what frequency is selected. However, in order to maintain a substantially constant gain, in the case when aging and/or temperature changes of circuit components cause the gain to deviate from the desired value, automatic gain control means may be connected to the delay modulating means.

The automatic gain control means may comprise frequency discriminating means coupled to the signal output of the delay modulator to detect any unwanted frequency or phase modulation in the output frequency and produce an error signal in response thereto, phase sensitive detecting means having inputs coupled respectively to an input of the delay modulator and to the output of the phase discriminator. The phase sensitive detecting means in use correlates the error signal with the input signal to the delay modulator. A loop filter is coupled between an output of the phase sensitive detector and a gain control input of the delay modulator.

The frequency discriminator may comprise a delay discriminator or a phase lock loop. Such a phase lock loop may comprise a voltage controlled oscillator (VCO) for generating a signal at a multiple, r, of the output frequency of the delay modulator, means for dividing the output frequency of the VCO by r, a phase detector having inputs connected respectively to the delay modulator and to the dividing means and an output connected to the phase sensitive detector and to a loop filter having an output connected to the VCO.

In the event of the output frequency being expressed by a multiplying factor x, that is Fo = xFc, the frequency synthesiser comprises a digital reciprocal unit for converting the multiplying factor x into the required integer part n and the required fractional part O.m of the divisor.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a block schematic diagram of one embodiment of a direct dividing frequency synthesiser made in accordance with the present invention, Figure 2 illustrates diagrammatically the operation of the rate multiplier shown in Figure 1, Figures 3A, 3B and 3C illustrate graphically the principle of operation of a direct dividing frequency synthesiser made in accordance with the present invention, Figure 4 is a block schematic diagram of a delay discriminator in the automatic gain control circuit shown in the broken line rectangle in Figure 1, Figure 5 is a block schematic diagram of a phase lock loop which may be used as a frequency discriminator in the automatic gain control circuit shown in the broken line rectangle in Figure 1, Figure 6 illustrates a Johnson code divider, Figure 7 is a block schematic diagram of a second embodiment of a direct dividing frequency synthesiser made in accordance with the present invention, and Figure 8 is a block schematic diagram of a phase error deriving circuit utilising a binary rate multiplier.

In the drawings the same reference numerals have been used to indicate corresponding features.

Referring to Figure 1 of the drawings, the direct dividing frequency synthesiser comprises a stable crystal controlled clock source 10 operating for example at a frequency Fc of 200MHz. The output of the clock source 10 comprises defined transitions or pulses equally spaced in time, in this example every 5nS. The transitions are applied to a dual modulus divider 12 which divides the transitions by either the modulus n or n+1, where n is the integer part of a fractional divisor (n+O.m) and O.m is the fractional part. The divider 12 comprises a digitally adjustable accumulator to which is fed an increment Y, selected in response to the value of the integer part n by an adjustable selector, at each occurrence of a corresponding clock transition.When an increment fills, or more likely overfills, the accumulator, the accumulator produces an output pulse leaving a residue, that is the difference or excess between the capacity of the accumulator and the count produced by increment which exceeds the capacity of the accumulator. The next following increment Y is then added to the residue.

The output from the divider 12 comprises a series of irregularly spaced transitions having a mean frequency of Fin.

The signal Fo is applied to a rate multiplier 16 in which it is multiplied by the fractional part O.m of the divisor. The rate multiplier 16 comprises a frequency reducer which reduces the mean input frequency Fin by cancelling some of the transitions in this signal and produces an output pulse signal having an average frequency Fs, where Fs = O.m x Fin. More particularly, the rate multiplier 16 may be implemented as an addition rate multiplier which in response to a transistion in the signal Fo adds a predetermined increment to the contents of an accumulator to form a new cumulative sum. This operation is illustrated in Figure 2. Once the cumulative sum exceeds a predetermined sum value S, the signal Fs is produced.The excess E, that is the difference between the cumulative sum value and the sum value S forms a residue to which the next following increment is added. The signal Fs is applied to a modulus control input 18 of the dual modulus divider 12 to cause the modulus to change from n to nal for as long as Fs is present.

Phase or time displacement errors are produced by the rate multiplier 16 and are applied as digital signals to a phase error circuit 20. When the rate multiplier 16 comprises an addition rate multiplier as described above, the current cumulative sum, represented by a step in Figure 2, is the displacement error.

The phase error circuit 20 comprises a digital to analogue converter (DAC) which produces analogue phase error samples which are applied to the delay modulator 14 in which the phase error samples are converted into time delay signals which are used to correct phase errors in the signal Fin which is applied to the delay modulator 14. The phase error samples are of opposite sign to the phase errors in Fin and are used to cancel the error in position or phase or to make the error equal to a constant value thereby producing a substantially jitter free signal at the frequency Fo. In certain applications it is desirable to have a well defined square wave output waveform and in order to provide such a waveform at a frequency of Fo/2 a flip-flop 24 is connected to an output of the delay modulator.

When implementing the circuit shown in Figure 1 the phase error circuit 20, which comprises a DAC, together with the delay modulator 14 may be an Analog Devices AD 9500 Digitally Programmable Delay Generator which has an internal DAC and can accept digital phase delay signals from the rate multiplier.

Figure 3A illustrates the defined output transitions of the clock source Fc, the time between successive output transitions is 5ns in the case of a 200MHz clock source. Figure 3B represents the signal Fin which has phase jitter indicated by irregularity of spacing of the transitions. Figure 3C illustrates the phase corrected signal Fo, where Fo = Fc/(n+O.m).

This equation may be expressed using a multiplying factor, x, where x = (n+O.m)-l so that the equation is now Fo = x.Fc. In Figure 3C the phase corrections, which have been indicated as At, vary in duration from one transition to the next.

The reciprocal of x can be calculated by a digital reciprocal unit 22 (Figure 1) each time a new frequency Fo is selected.

In order to illustrate the operation of the frequency synthesiser circuit a numerical example will be given in which the clock source 10 generates a stable frequency Fc of 200MHz and the frequency Fo is 19.651 MHz. Hence the multiplying factor x 5 10.177599 for a frequency resolution of 1Hz. The value of n is 10 and that of O.m is 0.177599. The dual modulus divider 12 controlled by the rate multiplier 14 to divide by 10 (or n) for 82.2401% of the time and by 11 (or n+l) for 17.7599% of the time. For the purposes of illustration if the value 82.2401% is rounded down to 80% and the value 17.7599% is rounded up to 20%, the divider 12 will divide by n+l for every 5th pulse in the signal Fin.

An alternative embodiment of the dual modulus divider to that described above comprises the combination of a single modulus divider and a pulse subtractor, otherwise termed a pulse swallow circuit. This embodiment makes use of the fact that dividing by n+l is equivalent to subtracting an input transition from the clock signal applied to the divider in which the divisor has a single value n.

Irrespective of which divider is used the effect of dividing by (n+l) introduces a delay of one clock period of the clock frequency Fc, which period is constant.

As the values of the phase error samples do not exceed one period of the clock frequency then the gain or sensitivity can be substantially constant.

In order to maintain the gain constant against for example variations in component values due to aging and/or temperature changes an automatic gain control circuit (agc) 26 is provided.

The agc circuit 26 comprises a frequency (or phase) discriminator 28 having an input connected to the output of the delay modulator 18 for deriving the jitter-free output signal Fo. The output signal Fo is compared with a reference signal and any unwanted frequency or phase modulation in Fo is detected by the discriminator 28 and converted to an error signal which is applied to a phase sensitive detector 30 which may comprise a multiplier. The detector 30 has a second input for receiving a signal containing the original phase error information and for convenience the signal Fin is used because its nominal frequency is the same as that of Fo but it contains phase information as a result of the division of Fc in the divider 12. In the detector 30 the error signal is correlated with Fin to provide an output signal for phase sense control.The output of the detector 30 is smoothed in a loop filter 32 and its output is applied as a gain control signal to the delay modulator 14 which controls the conversion of the phase error samples to the time delay actually exercised.

The frequency (or phase) discriminator 28 may be implemented in several ways. Figure 4 illustrates the discriminator 28 as comprising a delay discriminator in which the signal Fo is applied to a delay device 34 and to a multiplier type of phase sensitive detector 36. The delayed version Fo' of the input signal Fo is used as a reference signal by the phase sensitive detector 36.

Figure 5 illustrates the frequency (or phase) discriminator 28 being implemented as a phase lock loop. The phase lock loop comprises a voltage controlled oscillator (VCO) 38 which generates a frequency FVCO which is four times that of Fo.

FVco is divided by a divisor r, where r is 4, to produce an output frequency Fo". The frequency Fo" and the output frequency Fo from the delay modulator 14 (Figure 1) are correlated in a phase detector 42 to produce an error signal which is applied to a loop filter 44 and to the phase sensitive detector 30. The output from the loop filter 44 is used to adjust the frequency of the VCO 38. In view of the fact that Fo can be varied by altering the multiplying factor x, the VCO 38 has to be capable of producing the required range of frequencies.

The divider 40 may comprise a Johnson code type of divider which is able to produce two quadrature outputs at a quarter of the VCO frequency, that is at FVCO/4 but with a 90 degree phase shift between them. Figure 6 illustrates a Johnson code divider which comprises two D-type flip-flops 46,48 the clock inputs CK of which are connected to the VCO 38 output. The Q output of the flip-flop 46 is connected to the data input D of the flip-flop 48. The Q output of the flip-flop 48 is connected to the data input D of the flip-flop 46. Quadrature phase shifted outputs at a quarter of the VCO 38 frequency are derived on lines 50, 52 connected respectively to the Q output of the flip-flop 46 and to the Q output of the flip-flop 48.

Referring to Figure 7 of the drawings, the second embodiment of the direct dividing frequency synthesiser comprises a stable crystal controlled clock source 10 operating for example at a frequency Fc of 200MHz. The output of the clock source 10 comprises defined transitions or pulses which are applied to a dual modulus divider 12 which divides the transitions by either the modulus n or n+1, where n is the integer part of a fractional divisor (n+O.m) and O.m is the fractional part. The dual modulus divider 12 is of a type similar to that used in the embodiment shown in Figure 1 and in the interests of brevity it will not be described again.

The signal Fin is applied to a rate multiplier 16 in which it is multiplied by the fractional part O.m of the divisor. The rate multiplier 16 comprises a frequency reducer which reduces the mean input frequency Fin by cancelling some of the transitions in this signal and produces an output pulse signal having an average frequency Fs, where Fs = O.m x Fin. The signal Fs is applied to a modulus control input 18 of the dual modulus divider 12 to cause the modulus to change from n to n+1 for as long as Fs is present.

Phase or time displacement errors are produced by the rate multiplier 16 and are applied as digital signals to a phase error circuit 20 which is implemented as a DAC. The phase error circuit 20 produces analogue phase error samples which are applied to the delay modulator 14 in which the phase error samples are converted into time delay signals which are used to correct phase errors in the signal Fin which is applied to the delay modulator 14. The phase error samples are of opposite sign to the phase errors in Fin and are used to cancel the error in position or phase or to make the error equal to a constant value thereby producing a substantially jitter free signal at the frequency Fo.

In certain applications it is desirable to have well defined square wave output waveform and in order to provide such a waveform at a frequency of Fo/2 a flip-flop 24 is connected to an output of the delay modulator.

When implementing the embodiment shown in Figure 7 it is necessary to ensure that the timing is correct, otherwise for example the delay modulator 14 could be in the course of effecting a correction of a phase error when the extent of the correction is itself changed by an output from the phase error circuit 20 or alternatively the correction being effected is done to the wrong transition in Fin.

There are a number of alternative ways whereby the circuit timing can be adjusted to obtain the desired result. A first of these ways is to provide a buffer 15 on the input to the rate multiplier 16. The time delay introduced by the buffer 15 is such that the correction effected in the delay modulator 14 to a particular transition in Fin is that determined by the previous transition in Fin. When determining the actual time delay account must also be taken of the fact that the rate multiplier 16 can operate quicker than the delay modulator 14.

A second of these alternative ways is to insert a buffer 17 in the signal path for phase or time displacement errors from the rate multiplier 16 to the delay modulator 14. As shown, the buffer 17 is connected between the phase error circuit 20 and the phase error sample input of the delay modulator 14. The buffer 17 conveniently comprises a latching device which stores successive phase error samples until commanded to feed the next sample to the delay modulator 14.

In an alternative arrangement a buffer 171, embodied as a k bit wide latch, where k is an integer having a value of for example 8, is provided between the rate multiplier 16 and the phase error circuit 20. As with the previously described arrangement, the buffer 171 holds a newly derived phase or time displacement error until it is commanded to download this error to the phase error circuit 20.

A convenient method of commanding the latch 17 or 171 is to use a signal derived from Fin which in practice is a square wave. Fin is applied to an inverter 19 which inverts the square wave. The rising trailing edge of the inverted waveform is used to actuate the latch 17 or 171.

For convenience of implementation, since the AD9500 mentioned previously also has input latches, then the latch 171, the phase error circuit (or DAC) 20 and the delay modulator 14 can comprise an AD9500.

In order to maintain the gain of the delay modulator 14 constant an agc circuit 26 may be provided. The agc circuit 26 is similar in its construction and operation to that described and illustrated in Figures 1, 4, 5 and 6 and in the interests of brevity it will not be described again.

As will be apparent from a comparison of Figures 1 and 7, the primary difference is that in Figure 7 the delay modulator 14 is not in the signal path from the dual modulus divider 12 to the rate multiplier 16. When implementing the embodiments of the frequency synthesiser, each has its own advantages and disadvantages when compared to the other(s). In the case of the embodiment shown in Figure 1, the phase error applied to the delay modulator 14 by the rate multiplier remains constant until there is another transition in the frequency Fo at the output of the delay modulator 14. In consequence the phase error correction loop 14,16,20 has an opportunity to settle prior to the production of the reset transition.However, when the rate multiplier 16 produces an output pulse signal Fs, it is necessary to time the next transition from the dual modulus divider 12 to coincide with the action caused by the pulse signal Fs. In this latter respect, the embodiment of Figure 7 is less critical but the timing of effecting the phase correction in the delay modulator 14 is more critical. This is because, without any timing adjustment provided by the buffer 15, the signal Fin would be applied simultaneously to the delay modulator 14 and the rate multiplier 16. As a result the phase error signal produced by the rate multiplier 16 would be in the course of changing its value as the corresponding transition in the signal Fin is being processed by the delay modulator 14. In order to avoid this risk of instability, the buffer 15 delays Fin sufficiently long to allow the phase error adjustment to be stabilised.

Implementing the rate multiplier 16 by an adder is particularly effective from a performance point of view but from an electronic circuit design point of view such an arrangement is relatively complex. This is because the rate multiplier 16 will comprise a plurality of stages, the actual number depending on the desired precision required for the final frequency. In order to obtain a final frequency precision of y bits the sum of the bits used to define n and to define O.m must equal y. With a clock frequency Fc of 200MHz, a precision of 0.47Hz can be achieved with 32 binary bits. As 32 bit microprocessors are currently available then such a processor can be used to perform the binary long division in the digital reciprocal unit 22.

Alternatively the digital reciprocal unit 22 may comprise any standard 16 bit, 8 bit or 4 bit or other microprocessor which is programmed to generate the 32 bit reciprocal in a number of steps and to store the result in a 32 bit buffer.

The rate multiplier 16 may comprise a binary rate multiplier arrangement, an example of which is shown in Figure 8. In the arrangement illustrated, the binary rate multiplier comprises a 4-stage binary counter 54 having an output from each stage connected to a respective AND-gate 56 to 62. The signal input 55 to the counter 54 comprises Fo in the case of the Figure 1 embodiment and Fin in the case of the Figure 7 embodiment. Each of the AND-gates 56 to 62 has a second input to which a respective bit of the fractional part O.m of the divisor obtained from the digital reciprocal unit 22 (Figures 1 and 7) is applied. As signal outputs from the stages of the counter are produced on the 0 to 1 transition then in the case of a 4 stage counter 54, beginning with the least significant bit stage, the respective stages will produce 8,4,2,1 outputs for every 16 transitions on the input 55.Additionally these outputs will be interlaced. In order to multiply by O.m, one has to decide which of the required output pulses are required and enable the AND-gates accordingly. For example if 9 output pulses per cycle of 16 input transitions are required then gates 56 and 62 are enabled and if 13 output pulses are required then gates 56,58 and 62 are enabled. The outputs from the AND-gates 56 to 62 are connected to an OR-gate 64 which has an output 66.

In order to obtain an indication of the phase error, the signal at the output 66 is applied to a d.c. removal circuit 68 which removes any d.c. in the output signal on the output 66.

The signal output from the d.c. removal circuit which comprises a plurality of transitions, is integrated in an integrator 70 and the output, which comprises the sum of the transitions in a 16 transition cycle, is applied to the delay modulator 14. As will be realised integration is equivalent to addition and hence the integrator output represents the phase error in the signal being applied to the delay modulator 14.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of frequency synthesisers and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

CLAIM(S)

1. A direct dividing frequency synthesiser in which phase corrections for phase errors in the division process are derived from a fractional part of the division process.

2. A frequency synthesiser as claimed in Claim 1, comprising dividing means for dividing a signal obtained from a fixed clock reference source by a number having an integer part (n) and a fractional part (O.m) to give a desired output frequency.

3. A frequency synthesiser as claimed in Claim 2, wherein the phase corrections are effected by delay modulating means.

4. A direct dividing frequency synthesiser comprising a clock source, dividing means for dividing a signal derived from the clock source by a number having an integer part (n) and a fractional part (O.m) to give a desired output frequency, means for deriving signals representative of the phase errors produced as a result of the fractional part of the division operation and delay modulating means arranged in the signal path between the clock source and a signal output, the delay modulating means having a control input to which, in operation, signals representative of the phase errors are applied and an output for signals which have been delayed in response to the values of the signals representative of the phase errors, whereby the signals at said desired output frequency are substantially free of phase errors.

5. A frequency synthesiser as claimed in Claims 2, 3 or 4, wherein the dividing means comprises a dual modulus dividing means for dividing a signal on its input by (n) or (nay) and a rate multiplier for multiplying a signal on its input by the fractional part (O.m).

6. A frequency synthesiser as claimed in Claim 5, wherein the delay modulating means is coupled between the dual modulus dividing means and the rate multiplier.

7. A frequency synthesiser as claimed in Claim 5, wherein the rate multiplier and the delay modulating means have inputs coupled to an output of the dual modulus dividing means.

8. A frequency synthesiser as claimed in Claims 5, 6 or 7, wherein the dual modulus dividing means has a modulus control input, the state of a signal on the modulus control input determining whether the division is by (n) or (n+l), and wherein the rate multiplier has a signal output coupled to the modulus control input of the dual modulus dividing means.

9. A frequency synthesiser as claimed in Claims 5, 6 or 7, wherein the dual modulus dividing means comprises a fixed divider for dividing an input signal by (n), a pulse subtractor connected in the signal path from the clock source to the fixed divider, the pulse subtractor being responsive to a signal on a modulus control input indicative that the divisor should be (n+l), to subtract one clock transition from the input signal from the clock source whenever the said modulus control signal is present, and wherein the rate multiplier has a signal output coupled to the modulus control input of the dual modulus dividing means.

10. A frequency synthesiser as claimed in any one of Claims 5 to 9 when appended to Claim 4, wherein the means for deriving phase errors is connected to the rate multiplier.

11. A frequency synthesiser as claimed in Claim 10 when appended to Claim 7, further comprising buffer means for controlling the time of application of the signals representative of the phase errors to the delay modulating means.

12. A frequency synthesiser as claimed in Claim 7 or in any one of Claims 8 to 10 when appended to Claim 7, further comprising buffering means connected in the signal path to the input of the rate multiplier.

13. A frequency synthesiser as claimed in any one of Claims 5 to 12, wherein the rate multiplier is an addition rate multiplier comprising an accumulator in which, in response to each transition thereto, a programmable increment is added to a value in the accumulator, an output signal being produced each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulator, the excess accumulated value in the accumulator being representative of the phase error.

14. A frequency synthesiser as claimed in any one of Claims 5 to 12, wherein the rate multiplier is a binary rate multiplier.

15. A frequency synthesiser as claimed in Claim 14, wherein an output of the binary rate multiplier is coupled to a d.c.

removal stage and in which an integrating means is coupled to an output of the d.c. removal stage, the phase error signal being derived from the integrating means.

16. A frequency synthesiser as claimed in any one of Claims 6 to 15 when appended to Claims 3 or 4, further comprising automatic gain control means connected to the delay modulating means.

17. A frequency synthesiser as claimed in Claim 16, wherein the automatic gain control means comprises frequency discriminating means coupled to the signal output of the delay modulating means to detect any unwanted frequency or phase modulation in the output frequency and produce an error signal in response thereto, phase sensitive detecting means having inputs coupled respectively to an input of the delay modulator and to the phase discriminator, said phase sensitive detecting means in use correlating the error signal with the input signal to the delay modulating means, and a loop filter coupled between an output of the phase sensitive detector and a gain control input of the delay modulator.

18. A frequency synthesiser as claimed in Claim 17, wherein the frequency discriminator comprises a delay discriminator.

19. A frequency synthesiser as claimed in Claim 17, wherein the frequency discriminator comprises a phase lock loop.

20. A frequency synthesiser as claimed in Claim 19, wherein the phase lock loop comprises a voltage controlled oscillator (VCO) for generating a signal at a multiple, r, of the output frequency of the delay modulator, means for dividing the output frequency of the VCO by r, a phase detector having inputs connected respectively to the delay modulator and to the dividing means and an output connected to the phase sensitive detector and to a loop filter having an output connected to the VCO.

21. A frequency synthesiser as claimed in any one of Claims 2 to 20, further comprising a digital reciprocal unit for converting an incoming frequency multiplying factor x, where x = Fo/Fc and Fc is the clock source frequency and Fo is the desired output frequency, into the required integer part (n) and the required fractional part (O.m) of the divisor.

22. A direct dividing frequency synthesiser constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in the accompanying drawings.