GB2215539A

GB2215539A - All-digital phase-locked loop

Info

Publication number: GB2215539A
Application number: GB8804974A
Authority: GB
Inventors: Bhajan Singh; Vincent Considine
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-03-02
Filing date: 1988-03-02
Publication date: 1989-09-20
Anticipated expiration: 2008-03-02
Also published as: GB8804974D0; GB2215539B

Abstract

An all-digital phase-locked loop circuit is described in which a numerically-controlled oscillator (4) is driven at a multiple of a required output frequency; a counter (7) is provided to divide the output frequency of the oscillator by the multiple; an analogue-to-digital converter (1) is provided to sample an input signal having the required frequency, and the frequency of the most significant bit (msb) of the numerically-controlled oscillator output provides the sampling rate of the converter. These measures allow a reduction in size of look-up tables (ROM) in a sinewave generator (5) providing the nominal required frequency. <IMAGE>

Description

DIGITAL PHASE LOCKED LOOP This invention relates to a digital phase locked loop having an output waveform convertable to a sinewave in a sinewave generator.

The sinewave generator normally includes a ROM based look-up table and, for accurate phase angles, requires a large address range.

Such an all-digital phase locked loop comprises an analogue to digital (A/D) converter, a multiplier to perform a mixing operation, a digital filter to define the bandwidth of the loop, and a numerically controlled oscillator (NCO).

Figure 1 of the accompanying drawings illustrates a known phase locked loop (PLL) circuit including an NCO. As shown, an NCO 4 is clocked at a frequency F5 to provide an output signal of triangular waveform which is converted in a sinewave generator 5 to provide an output sinewave signal at a desired frequency. In the illustrated circuit, the output signal is a pilot tone locked to an input signal input to an A/D converter 1 at a sampling rate F5. The sampled input signal is fed to a multiplier 2 whereto the output of the sinewave generator 5 is also fed. The difference signal is passed by a low pass filter 3 and fed to a summer 6. The difference signal (a correction signal) is summed in the summer 6 with a constant value K and is applied to the NCO 4 to control the output frequency thereof.The word widths of the digital outputs are indicated on the drawing. As stated above, for accurate control of frequency and phase, the output frequency of the NCO 4 requires a large number of stored values in the sinewave generator 5 to produce the requisite sinewave output signal, the extracted pilot tone. The size of the ROM conventionally provided in the generator is consequently large.

It is an object of the present invention to provide a digital phase locked loop incorporating a sinewave generator in which the required address range of the generator is much reduced.

According to the present invention, there is provided an alldigital phase locked loop circuit comprising a numerically controlled oscillator, a sinewave generator for generating, from the output of the oscillator, a sinewave of a required frequency, a counter interposed between the oscillator and the sinewave generator, and control means for controlling the output frequency of the oscillator at a multiple of the required frequency, the counter being arranged to divide the output frequency of the oscillator by said multiple.

The invention will be described further, by way of example, with reference to Figure 2 of the accompanying drawings which illustrates. in block diagram form, an all-digital phase locked loop circuit according to the present invention.

As shown in Figure 2, an input signal is sampled in an analogue to digital (A/D) converter 1 and is input to a multiplier 2 together with the output signal of a sinewave generator 5. The output of themultiplier 2 is fed to a low pass filter 3 to extract the difference signal which is fed, as a correction signal to a summer 6 wherein it is summed with a constant input. The output of the summer 6 controls a numerically controlled oscillator 4 which is clocked at a frequency F5. The circuit so far described is substantially, identical to that described above in relation to Figure 1.

In accordance with the present invention, it is arranged that the constant input K to the summer 6 controls the NCO 4 such that the output frequency is a predetermined multiple N of the desired output signal. To this end, a counter 7 is interposed between the NCO 4 and the sinewave generator 5 to divide the output frequency of the NCO 4 by N i.e. down to that of the required output frequency of the sinewave generator 5. Additionally, instead of the input signal being sampled at the same rate as the clocking frequency F5 of the NCO 4, it is arranged to be clocked by the most significant bit (MSB) of the NCO output signal. In this way the input signal is sampled at 2rc/N intervals of the signal generated by the NCO.The output signal of the sinewave generator 5 is thus nominally at the same frequency as that of the required output signal and hence of the input signal to the A/D converter 1. The multiplier 2 and the filter 3 provide the correction signal to modify the constant input K to the summer 6 in a loop, to lock the NCO 4 to an output frequency equal to N times the required output signal. In lock, the input signal and output signal frequencies and phases are the same. As the input signal is sampled at a rate determined by the output frequency of the NCO 4, only a very limited range of values are necessarily provided in the look-up table of the sinewave generator 5. The size of its accompanying ROM can therefore be reduced. In practice, the number of samples required is equal to the ratio of the AID sampling frequency to the required pilot tone frequency, that is the division ratio of the counter 7. For example, in one realisation, seven eight-bit samples may be required where the output frequency of the NCO 4 is seven times greater than the frequency of the required pilot tone and the counter 7 divides by seven.

The actual samples stored are user defined and hence it is possible to program the phase angle to which the loop locks by simply changing the phase of the samples stored. The stored samples may be provided in ROM, RAM, gates or a PLA and , as desired, the samples may be predetermined or software generated.

Similarly, the constant K, and the divisor of the counter 7 may be software controlled.

Claims

CLAIMS:

1. An all-digital phase locked loop circuit comprising a numerically controlled oscillator, a sinewave generator for generating, from the output of the oscillator, a sinewave of a required frequency, a counter interposed between the oscillator and the sinewave generator, and control means for controlling the output frequency of the oscillator at a multiple of the required frequency, the counter being arranged to divide the output frequency of the oscillator by said multiple.

2. An all digital phase locked loop circuit as claimed in claim 1, wherein the output frequency of the sinewave generator is arranged to be locked to the frequency of an input signal, and further including an analogue to digital converter whereto the input signal is fed and wherein the input signal is sampled, and wherein the output frequency of the numerical controlled oscillator is arranged to be equal to the sampling rate of the A/D converter.

3. A circuit as claimed in claim 2 wherein the most significant bit of the output of the numerically controlled oscillator is used to clock the AID converter.

4. A circuit as claimed in claim 2 or 3 further including a multiplier whereto the digital samples of the input signal and the sinewave generated by the sinewave generator are fed, and a low pass filter for filtering the difference signal and for feeding the same as a correction signal to the control means of the numerically controlled oscillator.

5. A circuit as claimed in any preceding claim wherein the sinewave generator comprises a look-up table in which are stored sinewave values corresponding to the angular values fed thereto from the counter, the stored sinewave values being user definable.

6. An all-digital phase locked loop circuit substantially as hereinbefore described with reference to and as illustrated in Figure 2 of the accompanying drawings.