GB2183947A

GB2183947A - Frequency synthesiser

Info

Publication number: GB2183947A
Application number: GB08530168A
Authority: GB
Inventors: Paul Victor Brennan
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1985-12-06
Filing date: 1985-12-06
Publication date: 1987-06-10
Anticipated expiration: 2005-12-06
Also published as: WO1987003760A1; GB2183947B; EP0248871A1

Abstract

In a digital frequency synthesiser of the kind comprising a phase locked loop which includes a voltage controlled oscillator providing an output frequency, there can be a variation of the loop gain with operating frequency and efforts to avoid this variations can result in the generation of noise contributions in the output signal. The invention provides a phase locked loop having a voltage controlled oscillator (1) with variable divider (4) and phase detector (6). An output from the phase detector (6) is applied to a level shifting buffer amplifier (9) which is controlled by the same digital code as that applied to effect setting of the divider (4). This ensures a constant loop gain and low noise in the frequency output signal.

Description

SPECIFICATION Frequency synthesiser This invention relates to a digital frequency synthesiser of the kind comprising a phase locked loop which includes a voltage controlled oscillator providing an output frequency, the voltage controlled oscillator being controlled by a phase detector in the presence of a phase difference between a reference frequency and a signal derived from the output frequency via a variable divider, in accordance with the setting of which the output frequency is selectable.

In a synthesiser of the aforementioned kind, there can be a variation of the loop gain with operating frequency and this has been compensated for by the inclusion of a non-linear d.c. amplifier in the loop. The amplifier is usually placed between a loop filter and the voltage controlled oscillator and the non-linear characteristic of the amplifier is designed to compensate for a drop in loop gain which occurs with increasing output frequency. However, this solution does have disadvantages since the amplifier can generate excess additional noise and it may also be somewhat inflexible and iikely to be suitable only as a coarse means of compensation. The noise problem is particularly evident when the amplifier operates near to a transition from one gain level to the next.

The present invention was devised to provide a synthesiser having a substantially constant loop gain and where the creation of discontinuities in the loop gain is avoided. This can give a greater accuracy of compensation for any loop gain variation.

According to the present invention, a digital frequency synthesiser comprises a phase detector responsive to a reference signal and to a signal derived via a variable divider from a voltage dependent oscillator which affords an output signal, the phase detector providing a control signal for the voltage controlled osciliator such that the output frequency can be set in dependence upon the setting of the variable divider, wherein the oscillator is fed from the phase detector via a controlled level shifting buffer amplifier, the amplifier gain being set in dependence upon the setting of the variable divider.

The degree of compensation provided by setting of the amplifier gain may be digitally derived from a frequency select code used to control the variable divider.

Preferably, the setting of the amplifier gain is effected by means of a digital-to-analogue converter which is responsive to a digital code applied to effect setting of the variable divider.

One embodiment of the invention will now be described by way of example only with reference to the accompanying drawing which is a block schematic diagram of a frequency synthesiser.

As shown in the drawing, the frequency synthesiser comprises a voltage controlled oscillator 1 which on a line 2 provides an output signal FRO and which on a line 3 is arranged to feed a variable divider 4. The variable divider 4 is arranged to feed a phase detector 6 which is also fed on a line 7 with a reference frequency FR1. A control signal on a line 8 is fed from the phase detector 6 in the presence of a phase difference between the reference frequency FR1 on the line 7 and an output signal from the variable divider 4. The control signal on the line 8 is fed via a level shifting buffer amplifier 9 and a loop filter 10 back to the voltage controlled oscillator 1.

In the absence of the buffer amplifier 9, a digital phase locked loop of the kind just described is well known. However, there is a variation of loop gain with change of operating frequency and attempts have been made to compensate for the variation by using a nonlinear d.c. amplifier. The non-linear characteristic of the amplifier is designed to compensate for a drop in loop gain which occurs with increasing output frequency. This arrangement is not entirely satisfactory particulariy since excess additional noise can be generated at particular points in the output frequencies provided by the synthesiser.

The present invention provides the buffer amplifier 9 which serves to vary the gain of the signal from the phase detector 6. The amount of gain applied by the amplifier 9 needs to be controlled in response to the frequency of operation of the synthesiser, the gain is therefore controlled by a signal from a digital-to-anaiogue converter 11.

The digital-to-anaiogue converter 11 is controlled by digital signals from a digital code generator 12 the signals from which are simultaneously applied to the variable divider 4 in order to set the output frequency FRO of the synthesiser. The digital signals intended for the converter 11 are passed through a logic level control box 13 to effect any weighting that may be necessary for correct operation of the amplifier 9.

In operation of the frequency synthesiser just described, when the digital phase locked loop is in a stable condition, the output signal FRO of the voltage controlled oscillator 1 has a frequency which corresponds to a precise digital code which is applied to the variable divider 4 and similarly through the converter 11 to the amplifier 9. A change of output frequency FRO may be effected by making a change in the digital code and a corresponding modification will be made to the gain of the amplifier 9. This provision serves to ensure that the loop gain is substantially constant over the whole of the operating range of the frequency synthesiser.

The frequency synthesiser of the invention has been found to enable noise contributions to the output frequency of the synthesiser to be substantially reduced. In addition the synthesiser has been found to exhibit considerable fexibility when making frequency changes and to have a high degree of accuracy in the control of loop gain which is afforded.

The foregoing description of an embodiment of the invention has been given by way of example only and a number of modifications may be made without departing from the scope of the invention as defined in the appended claims. For instance, where the frequency synthesiser is intended to be used in a demanding application and where the digital code for controlling the frequency output is generated by an Eprom memory device, each synthesiser unit may be individually calibrated using automatic test equipment to ensure accurate operation.

Claims

1. A digital frequency synthesiser comprising a phase detector responsive to a reference signal and to a signal derived via a variable divider from a voltage dependent oscillator which affords an output signal, the phase detector providing a control signal for the voltage controlled oscillator such that the output frequency can be set in dependence upon the setting of the variable divider, wherein the oscillator is fed from the phase detector via a controlled level shifting buffer amplifier, the amplifier gain being set in dependence upon the setting of the variable divider.

2. A frequency synthesiser as claimed in Claim 1, in which the setting of the amplifier gain is effected by means of a frequency select code applied in digital form to the said variable divider.

3. A frequency synthesiser as claimed in Claim 2, in which the said frequency select code is applied to a digital-to-analogue converter, an output of which converter serves to control said amplifier gain.

4. A frequency synthesiser substantially as hereinbefore described with reference to the accompanying drawing.