GB2259201A - A frequency synthesiser - Google Patents

Abstract

A frequency synthesiser for generating a range of frequencies comprises a phase-locked loop comprising: a variable frequency oscillator (1); a frequency divider (3) for dividing the frequency (fout) of the output of said variable frequency oscillator (1), the divisor (N) of said frequency divider (3) being controllably variable; and a variable gain phase detector (5) for providing a signal (45, 47) indicative of the difference in phase between the output (fdiv) of said frequency divider (3) and a reference frequency signal (fref), the signal (45, 47) provided by the phase detector (5) determining the frequency (Fout) of oscillation of said variable frequency oscillator (1) thereby to control the frequency of oscillation (fout) such that it substantially equals said divisor (N) multiplied by the reference frequency (fref), and a circuit (11) for varying the gain of said phase detector (5) in dependence on the frequency (fout) generated by said synthesiser so as to maintain substantially constant the gain of said phase-locked loop over said range of frequencies generated. <IMAGE>

Description

A Frequency Synthesiser for Generating a Range of Frequencies This invention relates to a frequency synthesiser for generating a range of frequencies.

Frequency synthesisers of the above kind frequently employ a phase-locked loop comprising a voltage controlled oscillator (VCO), a frequency divider for dividing the frequency of the output of the VCO, and a phase detector for providing a signal indicative of the difference in phase/frequency between the output of the frequency divider and a reference frequency, the signal provided by the phase detector being fed via an amplifier and a lowpass filter of the phase-locked loop to the VCO to determine the frequency of oscillation of the VCO. The phase-locked loop therefore controls the VCO oscillation frequency such that it equals the divisor of the frequency divider multiplied by the reference frequency. The divisor of the frequency divider is controllably variable to enable the frequency generated by the frequency synthesiser to be altered over the aforementioned frequency range.

The performance of such frequency synthesisers in various respects, for example the frequency switching speed, phase noise profile, and response to frequency modulation, is determined by the gain of the phase-locked loop. The following equation contains an expression for the loop gain GL(jw) in terms of the gain of the various components of the loop: GL(jw) = GAL (jw) KpKv (1), jwN where GAL(jw) is the gain of the amplifier and lowpass filter, Kp is the yain of the phase detector, KV is the gain of the VCO, N is the divisor of the frequency divider, w is angular frequency and j is the square root of -1. In equation (1) the l/Jw arises due to the integration in the phase-locked loop by the VCO.At lock of the phase-locked loop at each of the frequencies generated by the synthesiser, GAL (jw), Kp and jw each is the same as at other frequencies generated by the synthesiser. However, KV and N each is different KV because the tuning sensitivity of practical VCOs varies with frequency, N of course varies so as to change the frequency generated by the synthesiser. Thus, the performance of such frequency synthesisers is inconsistent over the frequency range generated.

A known attempt to provide consistent performance comprises the inclusion of a variable gain circuit before the VCO and after the loop amplifier and lowpass filter. The gain of the circuit is varied over the frequency range of the synthesiser in such a manner as to keep the loop gain constant. Examples of variable gain circuits used are a diode-resistor shaping network and a digitally controlled amplifier.

Such interposition of a variable gain circuit creates the problem of the introduction of noise to the VCO tuning voltage with a resultant increase in phase noise. Such noise can only be filtered out without upsetting the loop dynamics in certain restricted circumstances.

It is an object of the present invention to provide a frequency synthesiser for generating a range of frequencies which has consistent performance over the range but does not have the above problem.

According to the present invention there is provided a frequency synthesiser for generating a range of frequencies comprising a phase-locked loop comprising: a variable frequency oscillator; a frequency divider for dividing the frequency of the output of said variable frequency oscillator, the divisor of said frequency divider being controllably variable; and a variable gain phase detector for providing a signal indicative of the difference in phase between the output of said frequency divider and a reference frequency signal, the signal provided by the phase detector determining the frequency of oscillation of said variable frequency oscillator thereby to control the frequency of oscillation such that it substantially equals said divisor multiplied by the reference frequency, and means for varying the gain of said phase detector in dependence on the frequency generated by said synthesiser so as to maintain substantially constant the gain of said phase-locked loop over said range of frequencies generated.

A frequency synthesiser in accordance with the present invention will now be described, by way of example, with reference to the accompanying drawing which is a schematic circuit diagram of the synthesiser.

Referring to the drawing, the synthesiser comprises a phase-locked loop comprising a VCO 1, a variable modulus (N) frequency divider 3, a variable gain phase detector 5, a differential amplifier 7, and a lowpass filter 9. The synthesiser further comprises circuitry 11 for varying the gain of the phase detector 5.

The phase detector 5 comprises a digital phase detector 13 and an output stage 14 comprising first and second transistor switches 15, 17, each switch 15, 17 comprising a resistor 19, 21 and a transistor 23, 25. The resistors 19, 21 of the transistor switches 15, 17 are the same, as are the transistors 23, 25. The emitters of the transistors 23, 25 are coupled together by connection 27. The digital phase detector 13 has first and second outputs 29, 31 which are respectively connected to the bases of transistors 23, 25. The collectors of transistors 23, 25 are respectively connected to the Inverting and non-inverting inputs of differential amplifier 7.

The circuitry 11 comprises a shaping circuit 33, a resistor 35, a zener diode 37, and a current mirror 39.

In operation of the synthesiser, the modulus N of divider 3 is set to a value such that N multiplied by a reference frequency fref supplied to the digital phase detector 13 equals the frequency fout it is required that the synthesiser, specifically the VCO 1 of the synthesiser, generate. The digital phase detector 13 compares the frequency fdiv) equalling the frequency fout generated by the VCO 1 divided by N, with the reference frequency fref, and provides at its outputs 29, 31 respectively first and second complementary trains of output pulses 41, 43, the duration of each of which pulses represents the difference in phase/frequency between fdiv and fref.

As explained in more detail below, the output stage 14 of the variable gain phase detector 5 varies by the same amount the amplitude of each output pulse of each train 41, 43. The output stage 14 at the same time inverts the trains 41, 43. The pulse train 45 derived from train 41 is applied to the inverting terminal of differential amplifier 7. The pulse train 47 derived from train 43 is applied to the non-inverting terminal of amplifier 7. The output stage 14 thus varies the gain of phase detector 5. In dependence on the phase difference indicated by the phase detector 5, amplifier 7 applies by way of lowpass filter 9 a tuning voltage Vtun to VCO 1 to tune VCO 1 to oscillate at a frequency fout such that a defined phase difference, the phase-locked loop locking phase difference, exists between fdlv and fref, and fdiv = frets Once fdiv = frets since fdiv = foutiN, fout = Nfref, the frequency required to be generated by the frequency synthesiser.

To keep the performance of the synthesiser consistent over the range of frequencies generated by the synthesiser it is necessary to keep the loop gain of the phase-locked loop of the synthesiser the same over the range of frequencies generated. To do this it is necessary to compensate for variation in KV and N in equation (1) of the introduction over the frequency range. The synthesiser of the drawing achieves such compensation by varying the gain of the variable gain phase detector 5, i.e. the gain Kp in equation (1), in dependence on the frequency generated by the synthesi ser.

The tuning voltage Vtun of the VCO 1 as wt;l as being applied to the VCO 1 is applied to the shaping circuit 33 where the transfer function K(Vtun) of the shaping circuit 33 operates on Vtun to produce a derived voltage Vder = K (Vtun). Further explanation of the operation of the shaping circuit 33 is given later. The derived voltage Vder is applied to resistor 35 and the current 1prog produced fed via the zener diode 37 so as to program the current mirror 39. The programmed current 1'prog produced by the current mirror 39 is applied to the connection 27 coupling the emitters of transistors 23, 25 of the output stage 14 of phase detector 5.

The first and second complementary trains of output pulses 41, 43 provided by the digital phase detector 13 switch the current prog between transistors 23, 25 to produce pulse trains 45, 47 respectively at the collectors of transistors 23, 25. Each pulse train 45, 47 is inverted with respect to its respective pulse train 41, 43 due to the inverting action of the transistors 23, 25.

Since the amplitude of the pulses of pulse trains 45, 47 provided by phase detector 5 is dependent on the current 11prog' varying 11prog varies the gain of phase detector 5. Thus, by choosing the transfer function K(VtUn) of the shaping circuit 33 appropriately, it can be ensured that, at the various frequencies over the range generated by the synthesiser (as indicated by the corresponding tuning voltages Vtun of the VCO 1), the gain of the phase detector 5 is always such as to compensate for KV and N varying in equation (1), such that the loop gain of the phase-locked loop remains the same and hence the performance of the synthesiser is consistent.

In this connection the gain of the phase detector 5 is as given in the following equation: Kp = 1 R19/21 (Vder - Vzen) (2), R 35 where R19/21 is the resistance of resistor 19 equals the resistance of resistor 21, R35 is the resistance of resistor 35, and Yzen equals that voltage of the voltage Vder dropped across the zener diode 37. Vder of course equals K(VtUn).

The transfer function K(VtUn) of the shaping circuit 33 is chosen to provide the accuracy of loop gain compensation required by the application. For a first order compensation of loop gain it may, depending on the application, be sufficient for Vder =Vtun, i.e. to omit the shaping circuit 33.

The synthesiser of the drawing has the advantage that the tuning line of the VCO 1 is isolated by the limiting action of the saturated transistor switches 15, 17 from any noise produced by the shaping circuit 33. Further, since no interpos-ition of additional circuitry between the loop amplifier/filter 7, 9 and the VCO 1 occurs in the synthesiser, the driving impedance seen by the VCO 1 is small, being the output impedance of the loop amplifier/filter 7, 9. Thus, the noise problem mentioned in the introduction with the prior art synthesiser with loop gain compensation is overcome.

Claims (8)

1. A frequency synthesiser for generating a range of frequencies comprising a phase-locked loop comprising: a variable frequency oscillator; a frequency divider for dividing the frequency of the output of said variable frequency oscillator, the divisor of said frequency divider being controllably variable; and a variable gain phase detector for providing a signal indicative of the difference in phase between the output of said frequency divider and a reference frequency signal, the signal provided by the phase detector determining the frequency of oscillation of said variable frequ ,ncy oscillator thereby to control the frequency of oscillation such that it substantially equals said divisor multiplied by the reference frequency, and means for varying the gain of said phase detector in dependence on the frequency generated by said synthesiser so as to maintain substantially constant the gain of said phase-locked loop over said range of frequencies generated.

2. A synthesiser according to Claim 1 wherein: said variable frequency oscillator comprises a voltage controlled oscillator, the signal provided by said phase detector determining the control voltage of the voltage controlled oscillator; and said means for varying comprises means for deriving a current from said control voltage, which current is utilised in an output stage of said variable gain phase detector to vary the gain of the detector.

3. A synthesiser according to Claim 2 wherein: said phase-locked loop further comprises between said phase detector and said voltage controlled oscillator a differential amplifier and between said differential amplifier and said voltage controlled oscillator a lowpass filter; said variable gain phase detector includes a digital phase detector which provides to said output stage of said variable gain phase detector two complementary trains of output pulses, the duration of each of which pulses represents the difference in phase between the output of said frequency divider and said reference frequency signal; and said output stage comprises switch means comprising first and second switches, each said switch being connected to a respective one of the inverting and non-inverting inputs of said differential amplifier, each said train of output pulses being applied to a respective one of said switches thereby to switch said derived current between said switches.

4. A synthesiser according to Claim 3 wherein each said switch comprises a transistor switch, the emitters of the transistors of said transistor switches being coupled together, the collector of the transistor of each transistor switch being connected to a respective one of the Inverting and non-inverting inputs of said differential amplifier, each said train of output pulses being applied to the base cf a respective one of the transistors of said transistor switches, said derived current being applied to the connection of said emitters.

5. A synthesiser according to Claim 2 or Claim 3 or Claim 4 wherein said means for deriving a current comprises: a resistor to which a voltage derived from said control voltage is applied thereby to produce a programming current; and a current mirror programmed with said programming current to produce said current derived.

6. A synthesiser according to Claim 5 wherein said means for deriving a current further comprises a shaping circuit, said shaping circuit deriving said voltage from said control voltage in accordance with the transfer function of said shaping circuit.

7. A synthesiser according to Claim 5 or Claim 6 wherein said programming current is fed to said current mirror via a zener diode.

8. A frequency synthesiser for generating a range of frequencies substantially as hereinbefore described with reference to the accompanying drawing.