GB2237944A

GB2237944A - Analogue to digital converter

Info

Publication number: GB2237944A
Application number: GB8925027A
Authority: GB
Inventors: Leslie Thomas Coutts
Original assignee: GEC Marconi Ltd; Plessey Co Ltd; Marconi Co Ltd
Current assignee: Plessey Co Ltd; BAE Systems Electronics Ltd
Priority date: 1989-11-06
Filing date: 1989-11-06
Publication date: 1991-05-15
Also published as: EP0452450A1; WO1991007017A1; JPH04502840A; GB8925027D0

Abstract

An analogue to digital converter circuit of the kind including an n-bit quantiser (where n > 1) for providing an output signal comprising an n-bit representation of the signal applied to its input, in which the quantiser is replaced by a quantiser element (3) providing an address location and a random access memory (RAM) device (4) at which an accurate representation of the corresponding output signal is stored, thus providing an instantaneous output signal of a predetermined level accuracy.

Description

ANALOGUE TO DIGITAL CONVERTER This invention relates to a analogue to digital converter (ADC).

Some of the problems associated with ADC level inaccuracy noise in a multi-bit feedback coder were discussed in the specification accompanying copending patent application No.

8820878, filed 6th September 1988. Particular techniques to overcome these problems were proposed. The specification explained that a fundamental difficulty with this type of circuit is that a multi-bit digital to analogue converter (DAC) is required at the end of the feedback loop. Any noise associated with level inaccuracy in this DAC is unaffected by the loop action. Thus it is desirable to use only a two-level (one-bit) DAC so that any inaccuracy in the DAC levels can be compensated for by the addition of a small number of external components. The patent specification referred to techniques whereby a multi-bit quantiser could have its output truncated to provide a single-bit feedback signal, and digital signal processing after the coder as a whole, could correct for the effects of this truncation.

As level inaccuracy of the DAC has already been dealt with, these still remains the need to consider level inaccuracy in the quantising element, and techniques by which this may be overcome.

Inaccuracies in the transfer function of the quantising element may be sub-divided into two categories, depending on whether they affect a very small, or a more extensive region of the characteristic.

Local inaccuracies affecting only one (or at most two) of the quantiser levels are known as differential non-linearities. Their spectrum is generally white, similar to the quantisation error, so they add to the latter in an uncorrelated manner and are shaped by the loop action in exactly the same way. In most practical situations, the magnitude of the differential non-linearities is of the same order, or is smaller than the quantisation errors. For this reason these will only add up to around 3dB increase in the in-band noise power and have an essentially white spectrum, so that they are not too significant.

Errors in the quantiser characteristic which extend over a significant number of quantising levels, lead to a distortion of the input signal. The resulting distortion components may occur in-band and so be unaffected by loop action. For example, if the quantiser has n-bit resolution, and the transfer characteristic has a simple quadratic component, resulting in an m-bit deviation at the centre of the transfer curve, then the first harmonic will be approximately 20 log(m/2") down on the fundamental. The existence of such spuriae may limit the usable dynamic range of the coder as a whole.

The present invention was devised in order to reduce these level inaccuracies in the transfer function of the quantising element.

According to the invention. there is provided an analogue to digital converter circuit of the kind including an n-bit quantiser (where n > l) for providing an output signal comprising an n-bit representation of the signal applied to its input, in which the quantiser is replaced by a quantiser element providing an address location and a random access memory (RAM) device at which an accurate representation of the corresponding output signal is stored, thus providing an instantaneous output signal of a predetermined level accuracy.

The RAM device may be arranged such that the stored signal values are of greater accuracy than those output by the quantiser element.

By way of example, some particular embodiments of the invention will now be described with reference to the accompanying drawing, in which: Figures 1 and 2 are block diagrams of different quantisercalibrated feedback coders.

The level accuracy problem may be reduced, according to the present invention, by regarding the quantiser output not as a direct representation of the analogue signal at its input, but rather as an address location at which an accurate representation of the signal is stored. In general, this means that the memory word length will be substantially longer than the quantiser output word length in order that the former can give a more accurate value for the instantaneous signal value. Effectively, using a memory in this way transforms an n-bit resolution, n-bit accurate (more or less) quantising element into an n-bit resolution, m-bit accurate component, where m is the memory word length.

In order that the values stored in RAM may be more accurate than those output by the quantiser, it is necessary that the latter be calibrated, either on power-up, on command, or at suitable working intervals. A typical calibration technique would use an m-bit counter and integrator, in a slope integration method. Since all noise-shaping coders already incorporate analogue integrators the only additional component required is an m-bit counter. The calibration procedure would be as follows: the m-bit counter starts at zero and increments whilst the n-bit output code of the quantiser is monitored. When the quantiser output code changes, the counter value mi is stored in RAM at the location nl. This procedure is repeated for all the 2n quantiser output codes.

Such a procedure will result n an n-bit resolution m-bit accurate quantising element in which the output codes are unlikely to be equally spaced. However, this factor is unimportant provided the values are known. It should be possible to improve the accuracy of a bipolar quantiser from around 8 bits to around 14 bits, and for a CMOS quantiser from around 6 or 7 bits to around 10 or 12 bits. This will have a significant effect on the spurious-free dynamic range of the coder as a whole.

As shown in the drawing, the feedback coder comprises a digital to analogue converter 1 which is connected to a loop with a noise-shaping filter 2 and quantiser element 3. An output from the quantiser element 3 is delivered to a RAM device 4 and from there the output passes to a truncation correction device 6.

In order to permit calibration of the quantiser element 3, a calibration signal produced by a signal generator 7 may be delivered into the loop when required. This signal may be inserted by means of a two way switch located either before (Figure 1) or after (Figure 2) the noise-shaping filter 2.

Claims

CLAIMS:-

1. An analogue to digital converter circuit of the kind including an n-bit quantiser (where n > l) for providing an output signal comprising an n-bit representation of the signal applied to its input, in which the quantiser is replaced by a quantiser element providing an address location and a random access memory (RAM) device at which an accurate representation of the corresponding output signal is stored, thus providing an instantaneous output signal of a predetermined level accuracy.

2. A circuit as claimed in Claim 1, in which the RAM device is arranged such that the stored signal values are of greater accuracy than those output by the quantiser element.

3. A circuit as claimed in Claim 1 or 2, in which the said quantiser element is arranged in a signal loop with a noise-shaping filter and digital to analogue converter.

4. A circuit as claimed in Claim 3, in which the signal loop includes means for introducing a calibration signal from a signal generator for calibrating the quantiser element.

5. A circuit as claimed in Claim 4, in which the calibration signal is introduced by means of a two-way switch in the said signal loop.

6. An analogue to digital converter circuit substantially as hereinbefore described with reference to the accompanying drawing.