GB2250875A

GB2250875A - High-resolution oversampled A/D converter

Info

Publication number: GB2250875A
Application number: GB9125200A
Authority: GB
Inventors: Jerome Johnson Tiemann
Original assignee: General Electric Co
Current assignee: General Electric Co
Priority date: 1990-12-03
Filing date: 1991-11-27
Publication date: 1992-06-17
Also published as: GB9125200D0; JPH04302223A

Abstract

An oversampled analog to digital converter arrangement, typically of the sigma-delta type, comprises an integrator 203 and a multi-bit analog to digital converter 204 with a complementary digital to analog converter 205 in a feedback loop. A table look-up memory 211 is provided to substitute digital values for the digital output signal of the multi-bit analog to digital converter in order to compensate for errors occurring in the feedback path so as to increase accuracy of conversion and allow simplification of the converter arrangement by eliminating sensitivity to errors in the digital to analog converter. <IMAGE>

Description

HIGH-RESOLUTION OVERSAMPLED A/D CONVERTER WITH HIGH OUTPUT SAMPLE RATE BACKGROUND OF THE INVENTION Cross Reference to Related Applications This application is related in subject matter to D.B. Ribner copending U.S. patent application Serial No.

550,763, filed July 10, 1990 entitled "Third Order Sigma Delta Oversampled Analog-To-Digital Converter Network With Low Component Sensitivity Requirements", a continuation-inpart of U.S. patent application serial No. 505,384 filed 6 April 1990, now abandoned, and of U.S. patent application serial No. 513,452 filed 23 April 1990, all assigned to the instant assignee. The subject matter thereof is hereby incorporated by reference.

Field of the Invention The present invention generally relates to oversampled analog to digital converters and, more particularly, to high-speed, high-resolution oversampled analog to digital converters.

Description of the Prior Art Particularly with recent advances in the use of digital signal processing techniques for analog signals, many refinements in the basic and well-known process of analog to digital conversion have been required. Analog to digital converter circuit arrangements have also become very sophisticated for performing such process at high speeds and with increasing accuracy. Oversampling, i.e., operating the modulator of the analog to digital converter at a rate many times greater than the signal Nyquist rate, and the complementary process, decimation, are commonly used in connection with analog integration and digital filtering to increase the resolution of output samples from an analog-todigital converter.Typically this increase is about 1-1/2 bits per octave of oversampling for a first order integrator, 2-1/2 bits of resolution for a second order integrator and correspondingly more bits for higher order integrators. Thus when the oversampling ratio is greater than 16:1, a considerable increase in resolution is achieved. These processes also reduce errors due to component mismatch and thereby insure minimization of information loss during the conversion.

A known type of analog to digital converter uses a feedback loop to increase accuracy in a manner consistent with high speed operation. Such analog to digital (hereinafter A/D) converter uses an internal A/D converter of modest resolution and a complementary digital to analog (hereinafter D/A) converter in a feedback loop. In theory, any error in linearity or resolution caused by the digital to analog converter is effectively added to the input signal and appears at the output without attenuation. In practice, while improving performance of the analog to digital converter, several intractable problems have remained. To achieve correct operation, the requirement for exact complementarity of the D/A and A/D converters has been difficult to satisfy since the D/A converter must be accurate in both linearity and resolution to the required resolution of the output samples.This imposes the requirement that the accuracy and linearity of the D/A converter must equal the resolution of the A/D converter, requiring the conversion of ever larger numbers of bits as the resolution of the A/D converter is increased. This leads to substantial increases in circuit complexity and cost, and may entail encountering a limit to the sampling rate. Accuracy and linearity matching has also been difficult since the D/A converter uses analog circuits which are subject to noise, temperature variation of circuit component values and significant part-to-part variation during manufacture. While feedback circuits provide a low sensitivity to component value variations, accuracy is limited by linearity and complementarity of the circuit forming the feedback path.

Problems of non-linear function in digital or partially digital circuits have been addressed by the use of look-up tables where the digital input or output signals of the device are used to access another digital number which respectively causes the desired result to be produced or supplies the corrected digital value. However, such approach is limited to substitution of a presumably accurate value for a repeatably erroneous digital value.

In summary, A/D conversion and D/A conversion are, electrically, radically different processes and the differences between these processes cause artifacts and errors in different forms in each process which are difficult to duplicate or otherwise compensate in the other process, particularly while being consistent with operation at high speeds.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an A/D converter arrangement having a D/A converter in a feedback loop, in which accuracy of the A/D conversion is largely independent of the accuracy, linearity or resolution of the D/A converter.

Another object is to provide an improved high-speed high-resolution A/D converter which can be manufactured at reduced cost.

Another object is to provide an A/D converter having performance which is relatively insensitive to ambient conditions and manufacturing variation of feedback circuits while providing high-speed, high-resolution operation.

To achieve the above objects of the invention, a circuit arrangement has been provided comprising a forward signal path for providing a digital output signal, a feedback signal path for providing an input signal to the forward signal path, and a translator coupled to the forward signal path. The translator substitutes digital values containing a correction value corresponding to errors in the feedback path for digital values which are produced by the forward signal path.

In accordance with one aspect of the invention, a method is provided for correcting the digital output signal of a circuit having a forward signal path and a feedback signal path. The method comprises the steps of storing digital values corresponding to possible output values of the feedback signal path, and translating digital output values of the forward signal path by substituting the stored digital values corresponding to possible output values of the feedback signal path for the digital output values of the forward signal path.

In accordance with a further aspect of the invention, an A/D converter is provided having a lowresolution D/A converter in a feedback path and a ROM translator containing data corresponding to the states of the D/A converter for each digital output signal of the A/D converter. Errors in both the D/A converter and A/D converter can thereby be simultaneously compensated, including mismatches of resolution and linearity between the two converters.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: Figure 1 is a schematic illustration of the architecture of an A/D converter according to the prior art.

Figure 2 is a schematic illustration of the architecture of an A/D converter according to the invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION Figure 1 illustrates a form of A/D converter arrangement 100 known in the art, as generally discussed above. For simplicity, the A/D converter arrangement 100 is illustrated as a first-order sigma delta A/D converter since it employs a first order modulator 112. The A/D converter 104 and D/A converter 105 employed in modulator 112 may each be of a single bit resolution (e.g., a simple comparator and a pair of switches coupling the comparator output to each of two reference voltages, respectively) or multi-bit circuits.

The following discussion of this circuit will assume the latter for purposes of conveying an understanding of the invention.

An analog input signal, oversampled at a high rate (e.g., greater than 16:1), is applied to input terminal 101 and is differentially summed with a feedback signal at summer 102. This summed signal is applied to an integrator 103.

Because modulator 112 employs but a single integrator 103, the modulator operates as a first order modulator. The output signal of integrator 103 is converted to a multi-bit digital signal by analog to digital converter 104. This multi-bit digital signal is applied to a digital filter 106, and the output signal produced by filter 106 is decimated by a decimator 107 in order to match the desired sample rate at the decimator output 108. The A/D converter output signal is also applied to the input of D/A converter 105 which performs a re-conversion to an analog signal that is ideally complementary to the operation of A/D converter 104. The reconverted analog signal is differentially summed with the input signal to derive the error signal which is integrated with the previous data sample and error values and converted to an updated digital value.This operation is repeatedly performed as long as the circuit is operating.

In the architecture of Figure 1, integrator 103 receives the output signal of differential summer 102 as an error signal. This error signal reflects not only changes in the input signal and aliasing errors due to the limit of resolution of A/D converter 104 (which will be reflected in the D/A converted signal), but also reflects errors due to deviations from complementarity of the output signals produced by each of A/D converter 104 and D/A converter 105.

Integrator 103 accumulates all such errors without regard to their source. Therefore, to avoid discrepancies in the accumulated error value, the resolution and accuracy of the D/A conversion must be at least as great as that of the final decimated A/D conversion. In terms of hardware, D/A converter 105 must process at least as many bits as the overall A/D converter 100 after filtering and decimation at an accuracy not less than the incremental value corresponding to the least significant bit (LSB) of the overall A/D converter 100 after filtering and decimation. This not only presents a severe design constraint and engenders high circuit complexity and expense, but also limits the sampling rate.Furthermore, it is difficult to manufacture circuits which will reliably meet this criterion due to manufacturing variations -from part to part and ambient operating conditions (e.g., thermal drift).

Even if the aforementioned design constraint is scrupulously observed, accuracy of the A/D conversion is less than optimal since any error in the D/A conversion is reflected in the output signal of the A/D converter and is not amenable to correction since the D/A converter adds directly to the input signal.

As shown in Figure 2, the A/D conversion arrangement 200 according to the present invention also includes an input terminal 201, a first order modulator 212 comprising a differential summer 202 having an input of one sign coupled to terminal 201, an integrator 203 coupled to the output of summer 202, an A/D converter 204 coupled to the output of integrator 203, and a D/A converter 205 in a feedback loop coupling the output of A/D converter 204 to an opposite sign input of summer 202. Additional digital processing is added by a digital filter 206 and a decimator 207.The invention differs from the prior art, as represented by the apparatus of Figure 1, by inclusion of translation means 211 which can be any apparatus capable of functioning as a table look-up device, or a computation device including such table look-up device, as described below, and preferably constitutes a read-only memory (ROM).

The digital output signal of A/D converter 204 is used to address the translation means.

The invention takes advantage of the fact that performance of the internal D/A converter will at least be consistent, and therefore a correction signal can be referenced to the input signal. The invention also exploits the disadvantage of the prior art architecture which, as indicated above, does not permit correction of errors in the D/A conversion and directly reflects those errors in the A/D converter output signal.

Accordingly, when translation means 211 is loaded with empirical data reflecting the actual response of D/A converter 205 and which may be generated on a device-bydevice basis, an exact correction can be made for any deviation from ideal performance. The translation means need only be able to translate quantified values, specifically those values corresponding to actual values that are generated in response to particular input states of the D/A converter. Since the digital output codes of translator 211 correspond to the actual levels generate by D/A converter 205 rather than the quantization levels of A/D converter 204, the integration in the digital domain performed during decimation is restored to agree with integration performed in the analog domain by integrator 203.Thus, the digital signals can be made to correspond precisely to what is happening with the analog signals and deviations from complementarity of converters 204, 205 can be fully compensated and corrected.

The actual data stored in translation means 211 will be a digital value corresponding to the actual analog output signal of D/A converter 205 which can be empirically obtained. Alternatively, should it be advantageous, the deviation from complementarity of converters 204, 205 can be quantified and the values calculated as the sum of the A/D converter output signal (the D/A converter input signal) plus the deviation. As another alternative within the scope of the invention, performance of the pair of converters 204, 205 can be measured or otherwise evaluated and a value representing a corrected value for the pair of converters can then be stored in translator 211. In any case, increased accuracy of the overall converter arrangement is obtained by the invention.

This improved performance is also provided by a simplified hardware embodiment enabled by the invention. As noted above, translation means 211 contains digital values which correspond to the actual analog values representing the output states of the D/A converter. Therefore, if the resolution of the D/A converter is reduced, the accuracy and resolution of the overall A/D converter arrangement 200 will not be affected. This is true since any error in the D/A converter output signal will be reflected in the A/D converter output signal. If, for example, the A/D converter output signal has a resolution of sixteen bits and the D/A converter can resolve only four bits, a plurality of digital output signals of the A/D converter, differing in the twelve less significant bits, would correspond to a single output value of the D/A converter.While a different amount of error would be present for each digital value, that amount of error is nevertheless known and can be exactly compensated.

This observation leads to a further possible simplification of the arrangement according to the invention.

In the previous arrangement, where D/A converter 205 has reduced resolution as compared with A/D converter 204, different values would be stored corresponding to only a single value of the D/A converter output. These values would be directly substituted for the raw A/D converter output signal. However, the A/D converter output signal reflects not only errors in the D/A output values, but also reflects the output value of the D/A converter due to the differential summation provided by summer 202. Therefore, the capacity, size and complexity of the memory contained in translation means 211 can be correspondingly reduced and the resulting reduced set of values can be accessed by the most significant bits of A/D converter 204 output signal. A corrected value for the A/D converter output signal can then be computed from the value of the D/A converter response and the actual digital output signal of the A/D converter.

This technique for increasing the speed and accuracy of digital circuits while reducing circuit complexity can potentially be applied to any circuit including a feedback loop and having a digital output signal, and is not limited to A/D conversion arrangements, per se.

However, the invention is particularly applicable to the A/D conversion arrangements which operate in conjunction with a decimator, as pointed out above.

When implementing either of these above simplified forms of the A/D conversion arrangement illustrated in Figure 2, it is important to realize that a practical limit to reduction of resolution of the D/A converter exists.

Consider the case where a monotonically changing analog input signal is applied and a sequence of digital values is being produced by A/D converter 204. when a bit of a significance corresponding to the resolution of D/A converter 205 is reached, a step change in the output signal of the D/A converter will be produced and summed with the input signal.

While this step change will be accurately reflected in the correction value, it will affect the output signal of integrator 203 over some finite interval of time, thus causing a discontinuity in the output digital value and the waveform represented thereby. However, such discontinuities can be minimized by design of the integrator, analog filtering of the output signal of the D/A converter to match the integrator, or even by digital processing of the digital output signal Therefore, as will be apparent to those skilled in the art, the resolution of D/A converter 205 can be reduced to a largely arbitrary extent if other parameters of the circuit design and permissible accuracy of the A/D conversion arrangement are properly observed.

In summary, the invention, as described above, provides increased accuracy of A/D conversion at high resolution and high speed, while enabling such performance to be produced with a simplified structure of reduced cost and less stringent manufacturing tolerances. Moreover, while the invention has been described in the context of a first order analog integrator, it is also applicable to analog integrators of higher order, with a resulting increase of resolution as discussed above.

While only certain preferred features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. A circuit arrangement comprising: a forward signal path for producing a digital output signal; a feedback signal path for providing an analog input signal to said forward signal path; and translation means coupled to said forward signal path for substituting, for digital values which are produced by said forward signal path, digital values containing a correction value corresponding to errors in said feedback path.

2. The circuit arrangement according to claim 1, wherein said translation means includes a look-up table memory containing a digital value corresponding to each possible output value of said feedback signal path.

3. The circuit arrangement according to claim 1, wherein said translation means includes a look-up table memory containing a digital value corresponding to an output value of said feedback signal path in response to each of a plurality of digital output values of said forward signal path.

4. The circuit arrangement according to claim 3, wherein said look-up table memory contains a digital value corresponding to an output value of said feedback signal path produced in response to each possible digital output value of said forward signal path.

5. The circuit arrangement according to claim 1, wherein: said circuit arrangement comprises an analog to digital circuit arrangement; said forward signal path includes an analog to digital converter; and said feedback signal path includes a digital to analog converter.

6. The circuit arrangement according to claim 2, wherein: said circuit arrangement comprises an analog to digital circuit arrangement; said forward signal path includes an analog to digital converter; and said feedback signal path includes a digital to analog converter.

7. The circuit arrangement according to claim 3, wherein: said circuit arrangement comprises an analog to digital circuit arrangement; said forward signal path includes an analog to digital converter; and said feedback signal path includes a digital to analog converter.

8. The circuit arrangement according to claim 4, wherein: said circuit arrangement comprises an analog to digital circuit arrangement; said forward signal path includes an analog to digital converter; and said feedback signal path includes a digital to analog converter.

9. An analog to digital converter arrangement comprising: a forward signal path including an analog to digital converter circuit; a feedback signal path including a digital to analog converter circuit; and translation means coupled to said forward signal path for substituting, for digital values which are produced by said forward signal path, digital values containing a correction value corresponding to errors in said feedback path.

10. The analog to digital converter arrangement according to claim 9, wherein said translation means includes a look-up table memory containing a digital value corresponding to each possible output value of said digital to analog converter.

11. The analog to digital converter arrangement according to claim 9, wherein said translation means includes a look-up table memory containing a digital value corresponding to an output value of said digital to analog converter produced in response to each of a plurality of digital output values of said analog to digital converter.

12. The analog to digital converter arrangement according to claim 11, wherein said look-up table memory contains a digital value corresponding to an output value of said digital to analog converter produced in response to each possible digital output value-of said analog to digital converter.

13. The analog to digital converter arrangement according to claim 9, wherein said translation means includes a read-only memory.

14. The analog to digital converter arrangement according to claim 9, wherein said forward signal path further includes integrator means for providing an input signal to said analog to digital converter circuit, and differential summing means for providing an input signal to said integrator means.

15. The analog to digital converter arrangement according to claim 14, wherein said translation means includes a read-only memory.

16. A method of correcting a digital output signal produced by a circuit having a forward signal path and a feedback signal path, comprising the steps of: storing digital values corresponding to possible output values of said feedback signal path; and translating digital output values of said forward signal path by substituting said digital values corresponding to possible output values of said feedback signal path for said digital output values of said forward signal path.

17. A circuit arrangement substantially as hereinbefore described with reference to the drawings.

18. A method of correcting a digital output signal substantially as hereinbefore described with reference to the drawings.

19. An analog to digital converter arrangement substantially as hereinbefore described with reference to the drawings.