GB2220311A - Electric toaster with electronic timer - Google Patents

Abstract

The timer controls the toasting period in accordance with the immediate previous history of use of the toaster. When a capacitor C2, connected to the threshold pin 6 of a type 555 timer T, has charged to a threshold voltage, the timer T de-energises an electromagnet EM whereupon a toast support tray rises and the heating elements are turned off. Capacitor C2 is discharged relatively slowly via a delay resistor R4 and a resistive path internal to timer T between pin 6 and ground pin 1 (rather than rapidly via the discharge pin 7) so that if a new toasting cycle is initiated closely following a preceding cycle while the toaster is still hot, capacitor C2 reaches the threshold voltage in a shorter time producing a shorter toasting period. A toasting cycle may be terminated manually by a switch SW1. In an alternative embodiment, timing capacitor C2 and an operational amplifier (IC1a), (Fig 2), provide a descending ramp voltage which is compared by a second operational amplifier (IC1b) with a reference set by a resistor chain (R5, VR1, R6) and the discharge path for capacitor C2 includes a delay resistor (R4) and that resistor chain (R5, VR1, R6). <IMAGE>

Description

ELECTRIC TOASTERS This invention relates to electric toasters for bread or the like and in particular to electric toasters having an electronic timer circuit incorporating a timing capacitor for determining the toasting time.

The interior of a toaster warms up in continuous use such that a reduction in the browning period is required to avoid overdone or burnt toast. It is known to provide an N.T.C. (negative temperature coefficient) thermistor for automatically adjusting the timed period, the thermistor being positioned to respond to the warming of the toaster interior. In toasters in which a capacitor is charged through a resistance chain, and the capacitor voltage is used to terminate the timed period when a pre-set threshold voltage is reached, an N.T.C. thermistor included in the resistance chain can produce the required reduction in the timed period when the toaster is used quickly in succession.

However, N.T.C. thermistors are relatively costly and can have a wide tolerance band, so that there is a requirement for better or more cost-efficient means of compensation.

According to the invention an electric toaster for toasting bread or the like comprises a timing circuit arranged to time the period for which an item to be toasted is subjected to heating from an electrical heating means, the timing circuit comprising a timing capacitor which during the timed period is permitted to charge steadily from a first voltage difference to a second voltage difference, and threshold means responsive to the capacitor voltage difference and arranged to terminate a toasting cycle when the capacitor voltage difference reaches the second voltage, and a reset means which is arranged to discharge the capacitor on termination of the toasting cycle, in which the reset means comprises a delay means for reducing the rate of discharging of the capacitor to the first voltage difference.

The time constant of discharge is preferably greater than four seconds and is most preferably greater than six seconds.

The delay means preferably comprises a delay resistor incorporated into the discharge path from the capacitor.

Thus, during the first toasting cycle, when the toaster starts from cold, the timing capacitor will initially be uncharged and will charge up progressively during the timed period until the second voltage is reached to end the browning period. In previously known toasters the capacitor was arranged to be quickly discharged by a suitable low impedance circuit that is made at the end of the timed period, but in accordance with the invention the delay resistor restricts the rate of discharge of the capacitor, such that if a fresh toasting cycle is initiated shortly after the end of a previous cycle, the timing capacitor will not have been fully discharged, and accordingly the capacitor voltage will reach said second voltage in a shorter time, thereby providing a reduction in the timed period for a quickly succeeding cycle of operation of the toaster.

Two toaster timing circuits in accordance with the invention will now be described, by way of example only, with reference to the accompanying circuit drawings in which: Figure 1 is a timing circuit employing a type 555 integrated circuit timer; and Figure 2 is a timing circuit employing an operational amplifier integrated circuit.

With reference to Figure 1, a suitable alternating supply V is obtained from a tapping on the toaster heating elements, and a rectifier D1 and capacitor C1 are used to provided a D.C. supply to a type 555 integrated circuit timer T, the pins of which have been labelled with conventional pin numbers.

Resistors R1, R2 and R3 in combination with a timing capacitor C2 provide, in well known manner, the principal timing function, the resistor R2 being manually adjustable to provide some adjustment of the toasting timing. When the toaster is first switched on timing capacitor C2 is uncharged and when the supply voltage V is established at the commencement of the first cycle the capacitor C2 begins to charge through the resistor network R1, R2, R3. The capacitor voltage is applied to the threshold pin 6 for terminating the timing operation when the voltage across capacitor C2 reaches a predetermined threshold voltage.

The output pin 3 supplies an electromagnet EM which is arranged when energised to support a toast support tray in a lowermost position in the toaster.

At the end of the timed period the pin 3 is de-energised to de-energise the electromagnet EM.

To enable the user to terminate a toasting cycle a normally open switch SW1 and resistor R5 are connected to reset pin 4, operation of switch SW1 resetting the timer T.

Timer T incorporates a flip-flop which switches when the voltage of capacitor C2 reaches the preset voltage to terminate the output at pin 3 thereby de-energising the electromagnet RM to cause the toast support tray to rise. This de-energises in known manner the heating elements, thereby cutting off the supply V to timer T.

The construction of the type 555 timer T is such that a current path exists between the threshold pin 6 and ground. When the voltage V is terminated, the resistance RI of this internal path falls to approximately RI=lOk for pin 6 voltages above about 1.5 volts.

In accordance with the invention a resistor R4, herein termed the "delay resistor", is incorporated in the connection between the timing capacitor C2 and the threshold pin 6. The resistor R4 will restrict the rate of discharge of the timing capacitor C2, the time constant of discharge being C2 (R 4 + RI) A typical value for the time constant is 8 seconds.

It will be appreciated that this discharge method is different from that which is usually employed with such timers, in which pins 6 and 7 are connected together, the discharge pin 7 providing a rapid discharge of the timing capacitor at the end of the timed period.

If, in the circuit of Figure 1, a toasting cycle is initiated immediately following a preceding toasting cycle, the timing capacitor voltage will not have fallen to zero when the voltage V is established, and accordingly the timing capacitor voltage will reach the threshold V2 in a shorter time than in the first toasting cycle, thereby providing a reduced toasting time in the second and any rapidly succeeding cycles.

The value of the resistor R4 is chosen to provide a suitable delay in discharging C2 based upon the average time taken for a person to unload and reload the toaster, and on the required reduction in the toasting time for subsequent cycles. A suitable value for R4 can be determined by experiment.

In the alternative circuit of Figure 2 the timing capacitor C2 is arranged across operational amplifier ICla to provide an integrator which, on establishment of the supply voltage V similarly tapped from the heating elements, provides at its output a descending ramp voltage. The ramp voltage is applied to the non-inverting input of a second operational amplifier IClb arranged as a comparator for comparing the ramp voltage with a predetermined threshold set by resistance chain R5, VR1, R6. Variable resistor VR1 provides a manual browning control.

In this case electromagnet EM is fed by a transistor TR1 controlled by the output of IClb which remains high until switched rapidly by the ramp voltage at the end of the timed period.

The amplifiers ICla and IClb are conveniently provided by a dual operational amplifier integrated circuit such as a MC1458C or equivalent.

At the end of the timed period the de-energisation of the electromagnet EM results in the raising of the toast support tray which de-energises a switch providing power to the heating elements, and accordingly the supply voltage V is lost. The timing capacitor C2 is then able to discharge to earth by way of a delay resistor R4 and resistors R5, VR1 and R6. In this case the time constant for discharging of the capacitor C2 is (R4 + R5 + VRl + R6)C2 and appropriate choice of R4 will provide a suitably restricted discharge.

Suitable values of the components are as follows-: Fig 1 Fig 2 VR1 470K VR1 47K R1 2M2 R1 470R R2 470K R2 2M2 R3 330K R3 4K7 R4 27K R4 33K R5 10K R5 22K R6 10K R6 47K C1 470uF R7 2K2 C2 220uF R8 47K C3 lOuF R9 10K D1 IN4001 C1 47uF D2 . IN4001 C2 47uF D3 IN4148 Dl IN4003 D2 IN4001 D3 IN4149 ZD1 12V ZD2 6V2 TR1 BC182L These component values give a time constant of discharge in the region of 8 seconds for each example.

Claims (12)

1. An electric toaster for toasting bread or the like comprising a timing circuit arranged to time the period for which an item to be toasted is subjected to heating from an electrical heating means, the timing circuit comprising a timing capacitor which during the timed period is permitted to charge steadily from a first voltage difference to a second voltage difference, and threshold means responsive to the capacitor voltage difference and arranged to terminate a toasting cycle when the capacitor voltage difference reaches the second voltage, and a reset means which is arranged to discharge the capacitor on termination of the toasting cycle, in which the reset means comprises a delay means for reducing the rate of discharge of the capacitor to the first voltage difference.

2. An electric toaster according to claim 1, in which the time constant of the discharge is more than four seconds.

3. An electric toaster according to claim 2, in which the time constant is more than six seconds.

4. An electric toaster according to Claim 3, in which the time constant is about eight seconds.

5. An electric toaster according to any preceding claims, in which the delay means comprises a delay resistor incorporated into the discharge path from the timing capacitor.

6. An electric toaster according any preceding claim, in which the timing circuit includes an integrated circuit clip.

7. An electric toaster according to claim 6, in which the timing capacitor applies its output voltage to a pin of the chip and a current path exists in the chip between said pin and ground.

8. An electric toaster according to claim 7, in which the current path has a substantially lower resistance when the toaster is switched off than it does when the toaster is toasting.

9. An electric toaster according to claims 7 or claim 8, in which a resistor is interposed between the timing capacitor and said pin.

10. An electric toaster according to any one of claims 1 to 5, in which the timing circuit comprises a first operational amplifier arranged as a comparitor for producing a high or low voltage signal depending upon whether a control input signal has reached a reference input signal, and a second operational amplifier arranged with the timing capacitor to produce a ramp voltage which comprises the control signal of the first operational amplifier.

11. An electric toaster substantially as herein described with reference to Figure 1 of the accompanying drawings.

12. An electric toaster substantially as herein described with reference to Figure 2 of the accompanying drawings.