GB2192758A - Package for wafer scale integrated circuits - Google Patents
Package for wafer scale integrated circuits Download PDFInfo
- Publication number
- GB2192758A GB2192758A GB08617556A GB8617556A GB2192758A GB 2192758 A GB2192758 A GB 2192758A GB 08617556 A GB08617556 A GB 08617556A GB 8617556 A GB8617556 A GB 8617556A GB 2192758 A GB2192758 A GB 2192758A
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- GB
- United Kingdom
- Prior art keywords
- wafer
- wsi
- package
- spacer
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Packaging Frangible Articles (AREA)
Abstract
Two wafer integrated circuits (5) are attached to respective p.c.b. substrates (4) held apart by a spacer (6) to form a sealed module. The wafers may be arranged so that the bond wires (1) overlap to reduce the thickness of the module. A plurality of modules may be combined to form a stack provided with an external housing or side cheeks. Heat is dissipated through the spacer (6) and through copper heat spreaders formed on the p.c.b. substrates. <IMAGE>
Description
SPECIFICATION
A modular high-density packaging scheme for WSI components 1-.0 - Introduction
Wafer Scale Integration- - (WSI) provides the means to form memory or data processing systems on whole wafers, rather than use the traditional, disintigration of wafers into individual chips that require subsequent packaging and re-connection.
It has been shown in UK Patent Application 85.05191 (Serial number 2173946) [1], that there is method of attaching a whole wafer to a carrier or substrate that p#rovides the means to connect the wafer to the outside world.
Connections (1) are formed between bond pads on the wafer surface and gold plated pads on the surface of the substrate, see Fig.
1.
Furthermore, the wafer (5) is firmly bonded to the substrate (4) by an intermediate adhesive film. This adhesive provides the necessary compliance to allow for differential expansion between wafer (typically Silicon) and the substrate (typically glass fibre).
A connector 2 can be added to the edge of the substrate to connect the wafer to the outside world and the whole assembly placed in a shroud to protect against scratch and environmenal damage.
The- following describes a method for providing a high density packaging scheme intergrating two of the above wafer/substrates into a modular component.
2.0 Prior Art
Val of Cimsa-Sintra [ 2 ] describes a two wafer package with two wafer/substrates mounted back-to-back. The substrate in this case is metal or ceramic. The two wafer package in [2] has been developed for high power, high speed applications.
Disadvantages of the package in [ 2 ] are:
1) the need for a further shroud or can to cover the wafers;
2) as a result-of the architectural approach taken by Val in [ 2 ] ,-high pin-out connectors are required that significantly reduce the packing density achievable by this approach;
3) the physical size of the connectors also result in the need to connect from both sides of the package leading to assembly and cabl- ing difficulties;
4) the connectors have to be attached after the back-to-back sandwich- has been assembled providing no facility to test the wafer/substrate assemblies prior to final assembly (this will lead to major yield losses).
5) high material and assembly costs.
Laermer of Singer-Kerfoot [3] described a package for a single 3" wafer mounted on a ceramic substrate. With similar design goals as [2] this package also suffers from high pinout.
The following packaging scheme described in 3.0 does not exhibit the disadvantages 2.1 through 2.5.
3.0 Details of a Two Wafer Modules
Fig. 1 illustrates a single wafer/substrate connectable to a system via a PCB pin connector. These connectors are used to reduce the pitch of adjacent substrates in a stack since an edge connector of gold plated fingers on a PCB requires a conventional female connector. This female connector has a substantial side wall resulting in a typical pitch of 10mm or more per substrate.
The female receptable (2) of the PCB pin connector is fitted to the substrate to eliminate protruding pins and the risk of transit or handling damage. The male pin of the connector (3) is attached to a backplane allowing many modules to be stacked and connected in parallel.
Two substrates (4) can be combined (wafer face to wafer face) as Fig. 2 using a spacer (6) to hold the PCB apart and prevent access to scratch damage. The spacer can be made from a variety of materials depending on power dissipation (and hence temperature excursions) of the application. Thermosetting plastic is a low cost example for low power 250mW per substrate.
An extension of the technique relates to achieving a low cost hermetic module. A die cast (zinc or aluminium) spacer has provision for a sealing gasket to take up surface irregularities, see Fig. 3. This seal faces a metal pattern on the PCB. This seak cab be an 0ring or a curled formulation applied in liquid form. The PCB uses a multilayer construction to provide hermeticity through the PCB. Screw or adhesive fixing outside the seal hold the piece parts together.
A cast metal spacer offers a further advantage of maintaining the flatness of the two
PCBs.
The distance- between wafers (as defined by the spacer thickness) is fixed by three parameters; wafer and adhesive thickness (8), bondwire profile, and connector height. The bondwire profile is defined by wire length and height above wafer (9). Height above wafer has been found empirically to be approx 1 mum, see Fig. 4. If the bond pattern (plan view) is symetrical, then a spacer thickness of 4mm is practical. This is consistent with the height of commercial PCB pin connectors.
However, if the wafer and therefore the bond pattern is rotated through half the arc between adjacent bond pads then bond wires on each PCB do not oppose one another leading to a reduced spacer thickness. Combined with a single rank connector, a total module thickness of 6.7mm can be achieved, see Fig.
5. If bonds do oppose then a practical value for module thickness is 8mm.
The symmetry of the package connectors eliminates module insertion errors since the module cannot be inserted the 'wrong way round'. This is a major advantage for manufacturing quality and field repair.
A further provision for hermeticity can be provided by a metal foil (10) soldered around the perimeter of the module sandwich to the outside surface of the PCBs see Fig. 6. This provision allows the non-hermetic package variant (no gasket) to be rendered hermetic for little added cost.
Combining several modules into a stack requires the non-wafer side of the PCBs not to have conductors printed, or more practically, a screen printed film on the non wafer side of the substrate to insulate conductor tracks.
This prevents short circuits between modules.
Using a metal spacer and a provision on the
PCBs for heat spreaders (11) formed from a copper conductor pattern underneath the wafer, see Fig.7, then the thermal resistance from semiconductor junctions in the surface of the wafer to the ambient a round the module is between 10 and 20 deg C per Watt. the conductor pattern (11) makes provision for bond pad regions (12).
The thermal model for a single module is shown in Fig. 8. The surface of each wafer is at temperature (17) and heat is conducted to the body of the spacer through two thermal resistances (14) and (15). Resistance (14) represents the vertical conduction through the wafer and adhesive to the collecting pattern (11). Heat then flows horizontally through the copper plane of region (13) into the spacer.
This horizontal resistnace #is represented by (15). The series resistance of (14) and (15) is less than 0.5 deg C per Watt.
The heat from both wafers is convected from the spacer into the local ambient at temperature (18) through resistance (16). This resistance can vary from 10 to 20 deg C per
Watt depending on texture, finish and area of the spacer side wall.
4.0 Combining Modules into a Stack
The modules (20) described in 3.0 can be stacked on top of one another to form a highly dense structure. This 'stack' connects to a backplane from one side and convects heat from the other three sides. Stacking can achieved by an external housing (19) that provides grooves (21) to guide individual modules into the backplane, see Fig. 9. This provides a simple means of adding further modules. Alternatively for a more rugges application, the modules (2) can be plugged into the backp#lane and then side cheeks (22), located by pegs (23) and screws, are attached to consolidate the whole assembly, see Fig. 10.
These side cheeks can be moulded from plastic or cast in metal depending on the power dissipation required.
5.0 Achieving Magnetic Disk Packing Densities
Such is the packing desity achievable by stacks of modules that it now becomes possible to integrate the same storage capacity of solid state memory into the same form factor as the same amount of hard disk, magnetic storage.
Fig. 10 illustrates a half height 5.25" form factor package capable of storing 70M byte to 220M byte depending on the size of the wafers used in their photolithographic dimensions.
For the very first time in the history of semi-conductor devices and packages there is a method of equalling storage densities previously only achievable by Winchester disk technology. The inventions described above therefore provide a unique, cost effective, high-density and reliable packaging scheme.
6.0 References
[ 1 ] 'Method of locating an integrated circuit on a substrate member', Wilkinson, J.M., UK
Patent Application 85.05191, February 1985.
[2] 'Wafer Scale Integration (WSI) Packaging' Val, C., Proceddings l.F.l.P. Workshop on
Wafer Scale Integration, March 1986.
[3] 'Air through hollow cards cools high power LSI' Laermer, L., Electronics Vol. 47,
No. 12, p114-p118, June 1974.
Claims (6)
1. A WSI package consisting of two whole or part wafer integrated circuits, each attached to a substrate member, with two substrates held apart by a spacer that provides mechanical strength and a path to conduct heat away from the integrated circuits.
2. A substrate member that provides a thermal conducting plane underneath the attached wafer integrated circuit, that conducts heat from the wafer to surface area of a spacer in contact with the plane.
3. A WSI package according to claims 1 and 2 that has minimum thickness due to non opposing wire bonds made possible by rotating individual wafers, prior to attachment to substrates, through half the arc between bond positions.
4. A WSI package according to claims 1, 2 and 3 that is tendered hermetic by a metal foil, soldered around the perimeter of the package.
5. A WSI package according to claims 1, 2 and 3 that can be combined with packages of the same type into a stack of minimum volume be the provision of side cheeks, located by pegs and attached by screws.
6. A stack of WSI packages according to claim 5 that can achieve the same physical dimensions as a half height 5.25" Winchester disk.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8617556A GB2192758B (en) | 1986-07-18 | 1986-07-18 | A modular high-density packaging scheme for wsi components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8617556A GB2192758B (en) | 1986-07-18 | 1986-07-18 | A modular high-density packaging scheme for wsi components |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8617556D0 GB8617556D0 (en) | 1986-08-28 |
| GB2192758A true GB2192758A (en) | 1988-01-20 |
| GB2192758B GB2192758B (en) | 1990-03-28 |
Family
ID=10601278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8617556A Expired - Fee Related GB2192758B (en) | 1986-07-18 | 1986-07-18 | A modular high-density packaging scheme for wsi components |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2192758B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2282486A (en) * | 1993-09-30 | 1995-04-05 | Mitsubishi Electric Corp | Semiconductor module and ic package used for the semiconductor module |
| GB2296604A (en) * | 1994-12-24 | 1996-07-03 | Bosch Gmbh Robert | Electric device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1201452A (en) * | 1968-02-29 | 1970-08-05 | Telefunken Patent Verwertungsg | Improvements in or relating to stacked electric circuit constructions |
| GB1326972A (en) * | 1972-03-16 | 1973-08-15 | Elliott Brothers London Ltd | Electrical circuit assemblies |
| GB1365877A (en) * | 1971-10-19 | 1974-09-04 | Sperry Rand Ltd | Electronic circuit assemblies |
| GB2033668A (en) * | 1978-11-11 | 1980-05-21 | Ferranti Ltd | Circuit assemblies |
| GB2145571A (en) * | 1983-08-23 | 1985-03-27 | Standard Telephones Cables Ltd | Electronic component module |
-
1986
- 1986-07-18 GB GB8617556A patent/GB2192758B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1201452A (en) * | 1968-02-29 | 1970-08-05 | Telefunken Patent Verwertungsg | Improvements in or relating to stacked electric circuit constructions |
| GB1365877A (en) * | 1971-10-19 | 1974-09-04 | Sperry Rand Ltd | Electronic circuit assemblies |
| GB1326972A (en) * | 1972-03-16 | 1973-08-15 | Elliott Brothers London Ltd | Electrical circuit assemblies |
| GB2033668A (en) * | 1978-11-11 | 1980-05-21 | Ferranti Ltd | Circuit assemblies |
| GB2145571A (en) * | 1983-08-23 | 1985-03-27 | Standard Telephones Cables Ltd | Electronic component module |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2282486A (en) * | 1993-09-30 | 1995-04-05 | Mitsubishi Electric Corp | Semiconductor module and ic package used for the semiconductor module |
| US5521786A (en) * | 1993-09-30 | 1996-05-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module and IC package used for the semiconductor module |
| US5583748A (en) * | 1993-09-30 | 1996-12-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module having multiple circuit boards |
| GB2296604A (en) * | 1994-12-24 | 1996-07-03 | Bosch Gmbh Robert | Electric device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2192758B (en) | 1990-03-28 |
| GB8617556D0 (en) | 1986-08-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920718 |