GB2191633A - Radiation hardened semiconductor devices - Google Patents

Description

1 GB 2 191 633 A 1

SPECIFICATION Radiation hardened semiconductor devices

Background of the invention 5

Thisinvention relates generallyto semiconductor devices and, more particularly,to radiation hardened semiconductor devices.

As is known in the art, many military communication and space based systems have system requirements for survivability and operation during and after a variety of radiation environments. There are generally recognized four types of radiation exposures. 10 The first exposure is neutron exposure. Neutron exposure occurs from neutrons which emanate from a nuclear explosion or reaction. The effect of neutrons on semiconductor materials is to produce lattice dam age in the crystal structure of the semiconductor. This lattice damage generally decreases the mobility and lifetime of carriers in the semiconductor material and degrades or destroys the operating performance of semiconductor devices fabricated from those materials. This problem is particularly important in bipolar 15 silicon technologywhich relies upon minority carrier lifetimes for operation. In gallium arsenide, the damage thresholds are substantially higherthan silicon.

The second type of exposure is total dose exposure orthe integration overtime of all types of radiation sources such as gamma, x-rays, and cosmic rays. At very high total dose exposures, bulk damage occurs as with neutron exposure. Again, with gallium arsenide, the threshold atwhich gallium arsenide bulk damage 20 occurs is generally very high and total dose exposure is generally not a problem in gallium arsenide. In MOS technologies which use an oxide layer underneath a gate region, total dose exposure can result in trapped charge within the oxide layerthereby preventing or inhibiting performance of MOS transistors.

The third type of radiation exposure is generally referred to as transient ionizing radiation. Transient ioniz ing radiation is dependent upon the dose rate of short pulses of high radiation exposures of 20 to 1,000 rads 25 over a pulse duration period of 5 nanoseconds to 3 microseconds, for example. Generally, transient ionizing radiation is a problem in analog devices since exposure will cause errors ortemporary inoperativeness of such circuits, although such exposure generally will not cause any permanent damage to the circuit.

However, for semiconductor devices such as random access memories which require storage of data in terms of states of transistors being on or off, transient ionizing radition is a very serious problem because 30 exposure to such radiation can result in permanent loss of data. Loss of data occurs as follows. The ionized charges which are generated during transient ionization in the semiconductor material move towardsthe electrodes of the device, creating a primary photocurrent. Primary photocurrent refers to the photocurrent produced in response to the ionizing radiation. Secondary photocurrent results from the effects of primary photocurrent, for example electron or hole traps which become ionized in response to the primary photo- 35 current. After cessation of the primary photocurrent and transient ionizing radiation these traps may mod ulate the current in the channel of the device. The primary photocurrent if sufficient can change or "upset" the state of the transistor. In digital storage devices, when the state of the transistor is upset, the data in the storage device, random access memory (RAM), for example, is lost. In gallium arsenide, for example, the rate of transient ionization is 50% higherthan the rate in silicon. However, the lifetime of these ionized carriers in 40 gallium arsenide is 1 % of the lifetime of the carriers in silicon.

Gallium arsenide, accordingly, is less sensitive to transient ionizing radiation than silicon and generally has an order of magnitude improvement over silicon without any special precautions being taken. However, for some applications, for example random access memories to replace plated wire memories in ballistic missile systems, a typical system dose rate of 1012 rads/second, for 5 to 100 nanosecond exposures, is 45 beyond the present capabilities of gallium arsenide.

Thefourth type of radiation exposure is generally referred to as single event upset. Single event upset is a problem believed similarto transient ionizing radiation exposure except that it occurs on a single event basis where random particles such as a neutron, alpha, beta or cosmic ray strikes the semiconductor material causing a transient generation of photocurrent. This problem is particularly important in highly dense ran50 dom access memories wherein the transistor structures are very small and the amount of charge stored in each junction is relatively small. To some extentthe problem is solved in earth based applications by apply ing a coating of material overthe semiconductor. This coating is selected to absorb alpha and beta particles.

However, in space since there is no atmosphere to filter cosmic rays, and their energy is much higherthan that of alpha and beta particles, the coating alone is generally not sufficientto reduce the occurrence of the 55 single event upset radiation problem.

Several solutions are known in the art to overcome thetransient ionizing problem for certain types of semiconductor devices. For example, as described in an article entitled "Computer Modelling and Radiation Testing of A1GaAs Photodiodes Structures", Osbourne et al, lEEE Transactions in Nuclear Science, Vol. NS 28, No. 6, December 1981, pgs. 4342-4345, photodiodes were fabricated including a gallium arsenide sub- 60 strate and an aluminum gallium arsenide barrier layer disposed on the substrate with a second gallium arsenide active region disposed overthe aluminum gallium arsenide barrier layer. The gallium arsenide active region and the aluminum gallium arsenide barrier layer are each doped to provide a P-N junction at their interface. The difference in the band gaps between the aluminum gallium arsenide and the gallium arsenide provides a barrier against minority carrier flow from either the gal] W m arsenide active region orthe 65 2 GB 2 191 633 A 2 gallium arsenide substrate into the aluminum gallium arsenide barrierlayer. Ifthis barrier is sufficiently large minority carriers generated inthesubstrateare preventedfrom crossing the aluminum galliumarsenide barrierlayerand being collected as current in thejunction. Osbourne describes the use of a single, nonabrupt layer of A1GaAs which results in abouta 2timesto3times improvementin radiation tolerance. SinceOs bourne is collecting chargefrom a PN junctionformed bytheGaAs andAIGaAs layers, the amount of sub- 5 strate contribution is relatively small because Osbournecan collect charge only from about one diffusion length distance from the junction. A diffusion length is related to the square rootofthe product of the mob ilityof carriers in the semiconductor material andthe lifetime of the carriers in such material.

A second technique known in the art particularly with respectto bipolar transistors is generally referred to astheso-called "dielectric isolation" process whereby a tub of silicon expitaxial material issurroundedand 10 isolated from the substrate bya layerof silicon dioxide (Si02). With this arrangement during transient ioniza tion, carriers generated in the polycrystalline silicone substrate are isolated by the insulator provided bythe silicon dioxide. While this provides some degree of additional hardness to silicon devices,such atechnique cannot successfully be usedwith materiaissuch asgallium arsenide since there is no known nativeoxideof gallium arsenide. Further, the dielectric isolation technology is generally a flip/chip technology meaningthat 15 processing occurson both sides of the silicon wafer. This technology is relatively expensive often having low yieldsand providesdevices having low transistor densities.

Summary of the invention

In accordance with the present invention, a semiconductor device includes a substrate comprising afirst 20 Group 111-V semiconductor material, and a radiation barrier layer disposed over said substrate comprising at leasta layerof said Group Ill-Vrnaterial of said substrate disposed between a pairof layers comprising a second, different Group 111-V material. The second material hasa largerband gapthanthatof thefirstmat erial having aconduction band energy higher than the conduction band energyof said first material anda valence band energy lower than the valence band energy of said first material. Means are disposed overthis 25 barrierlayerto providethe metal semiconductor field effect transistor. The means may include a suitable doped crystalline layer of the first Group 111-V material having disposed on portionsthereof ohmiccontact regions for source and drain electrodesand a gate regionformed in Schottky barrier contact with the semi conductor region to providea metal semiconductorfield effect transistor.

With this arrangement, the alternating layers of first and second materials providea plurality& potential 30 barriers to carriers generated in responseto radiation exposure. The carriers generated inthesubstrate during exposure to transient ionizing radiation mustsurmounta barrier height related to the difference in bandenergies between the first and second materials. The electrons and holes presentinthe barrierlayer will bereduced by a factor proportional to exp(E/kT) where E isthevalence band orconduction banddis- continuity,kis Boltzmans constant, and T is the temperature of the semiconductor material expressedin 35 degrees Kelvin ('K). The carriers that do notsurmountthe potential barrierwill recombine and, accordingly, will not contribute to the generation of a primary photocurrent in the active region of the device. Therefore, the largepotential numberof carrierswhich maybe generated from the substrate in response to radiation exposure are substantially isolated from active regionsof thefield effect transistor and, accordingly, sub stantiallyno primary photocu rrent will becollected intheactive regionthus preventing an upset,forex- 40 ample, in the logic state of afield effect transistor or a transient error in an analog circuit employing sucha field effect transistor.

In accordancewith an additional aspect ofthe present invention, a metal semiconductor field effecttransis tor includes a substrate comprising gallium arsenide and a radiation barrier layercomprising at leastan undoped layerof gallium arsenide disposed between a pairof undoped layers of aluminum gallium arsenide 45 (AI.Gal,As) having an alloy compositional ratio xwhere x isthe ratio of AI to As and is in the range of 0.1 to 1.0. Overthe last layer of the barrier layer, an active layer comprising a doped gallium arsenide crystalline layer is disposed. Source and drain electrodes are disposed in ohmic contact over portions of this active layer with a gate electrode including a Schotty barrier contact metal disposed in Schottky barrier contact with the active region between said source and drain electrodes. With this arrangement, carriers generated in re- 50 sponseto ionizing radiation from the substrate are isolated from the active layers of thefield effect transistor.

Accordingly, substantially no substrate photocurrent is collected thereby increasing the radiation threshold level which can cause upset in the state of thefield effect transistor when provided in a digital logiccircuit such as a random access memory or provide an increased threshold to prevent a transient error in an analog circuit employing such a transistor. 55 Brief description of the drawings

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which:

Figure 1 is a block diagram showing a typical configuration of memory cells for a random access memory; 60 Figure2 is a schematic diagram of a typical memory cell used in buffered FET (13FT) logic; Figure 3 is a plan view of a field effect transistor used in a portion of the buffered FET logic memorycell shown in Figure 2; Figure4 is a cross-sectional view along line 3-3 of Figure 4; Figure 5is a blown-up view of a portion of Figure 4 showing in detail the structure of the radiation barrier; 65 3 GB 2 191 633 A 3 and Figureffis a graphical representation of an energyband diagram of the heterostructure shown inconjunc ti o n with Fig u re 3.

Figure 7 is a plot of photocurrentvs bias voltage at a dose rate of 9X 109 rads(GaAs)/sec. forthree semi conductor structures which shows the reduction in photocurrent using a a barrier layer as described in 5 conjunction with Figures 3-6.

Figure 8 is a plot of photocurrentvs dose rate fora conventional structure and structure fabricated in accordance with Figures 3-6.

Description of the preferred embodiments 10

Referring now to Figures land 2, atypical array 10 of memory cells 12jj fora random access memory is shown. Each of the memory cel Is 12q are fed by lines BLj and BLj which are respectively the ith bit line and jth bit complement line for the jth bit position of the memory cell 12jj. Each of the cells 12ii of the ith and ith memory cell 12jj are also fed by one of a predetermined number of word lines Wi. Therefore, as shown in Figure 1, and as will be described in further detail in conjunction with Figure 2, a one or a zero can be is selectively written into and then read from each one of the memory cel Is 12jj. A one or zero is written into all the bits forword 12i by placing the logic level "0" or M "to be written to each cell 12ii onto the respective bit lines, BLi and the complement of the logic level to be written on the respective bit line BLj. The word line Wi is then raised to a logic "1 "state and the cells in word line ith are written into each ith bit position. All the bit positions of the ith word are read by raising the word line Wi and sensing the voltage levels coupled from the 20 memory cell to each of the bit lines BL and BL. Not shown in Figure 1 are necessary, but conventional, address decoders, read/write circuits, and buffer interface circuits which are used to interface the memory cell array 10 to external devices.

Referring now to Figure 2, a memory cell 12ii where i refers to the memory cell in the ith word line and j refers to the lth bit position of the cell, is shown to include a plurality of transistors, here metal semiconductor 25 field effect transistors (MESFETS). Detai Is of construction of such transistors in accordance with the present invention will be described in conjunction with Figures 3-6. The memory cell 12jj includes a pair of buffered logic elements 13 and 33. Each logic element, for example, logic element 13 includes a pair of transistors, here 16 and 18 connected to provide an inverter, a buffer transistor FET 14 connected between a bit line BLj and interconnection of the transistors 16 and 18, and a level translator comprising transistors 20 and 24 and a 30 plurality of diodes generally denoted as 22 disposed between the connection of transistors 20 and 24, as shown. Furthermore, transistor 16 of the inverter and transistor 24 of the level shifter are each connected in a resistive mode configuration by connecting the gate electrode thereof to the source electrode thereby provid ing a predetermined resistance or load related to the width and length of the gate electrode of thetransistor.

Transistor 18 of the inverter and transistor 20 of the level shifter are connected as the switch elements of each 35 of the respective circuits.

In a similar manner, logic element 13 includes an inverter comprising transistors 36 and 38 connected as shown, a buffer transistor 34 connected between the common connection of transistors 36 and 38 and bit line BLj and a level translator comprising transistors 40 and 44 and diodes generally denoted as 42 disposed between interconnection of transistors 40 and 44 as shown. Similarly, transistors 36 and 44 are connected in 40 a resistive mode to provide a load and transistors 38 and 40 are connected in a switching mode.

In this configuration, the transistors 16,20,36 and 40 have their drain electrodes connected to a voltage source VDD which is generally in the range of 2 to 2.5 volts. The source electrodes of transistors 24 and 44 are connected to a voltage source Vss generally equal to -1.0 volts. To provide a memory cell configuration for the combination of the logic elements 13 and 33, the gate electrode of transistor 18 is connected to the drain 45 electrode of transistor 44 and the gate electrode of transistor 38 is connected to the drain electrode of transis tor 24, thereby providing a flip/flop configuration to the interconnection of the pair of logic elements 13 and 33.

The memory cell operates to store either a logic "0" or a logic" 1 "on transistors 24 or44 as follows. A voltage signal generally between - 1 volts fora logic "0" and+ 1 voitfor a logic" 1 "is provided to the switch 50 transistor 18 or 38 of each one of the logic elements. Responsive to such a voltage level excursion, an output voltage atthe drain electrodes of transistors 18 or 38 between 0.2 volts (logic "0") and 2.5 volts (logic" 1 ")is provided. -9-L-and a logic 1 is placed on line BL and word lineWi More particularly, when a logic 0 is placed on line selectstransistors 14 and 34 by placing a logic leveV 1 "on line Wi, a M " iswritten into memory cell 12jj.A 55 logic leveP 1 "on line Wi allows transistors 14 and 34to be placed in an "on" state. If the corresponding bit lineB L or BL is atthe logic" 1 "state, then this voltage level will be transferred to junction 15 orjunction causing transistor 18 and transistor 38 to change state and store the logic" 1 "on transistor 18 and logic "0" on transistor 38 which would correspond to the logic "0" state on BLj. In a similar manner, logic "0" is written into cell 12jj by placing a logic "0" on line BLand a logic "1 "on line BL. 60 When memory cell 121j is interrogated to read the contents of the memory cell, the word line will go to a logic M " statethus selecting all the bits in the ith word. If a logic M "is stored in the cell then BLwill gotoa M "state and BLwill go to a zero state. Read circuits such as a switched comparator (not shown) orFET buffers (not shown) maybe used to read the contents of the bit cells in the jth word out of the memoryto buffer circuits (not shown). 65 4 GB 2 191 633 A 4 Then memory cells 12 are used to store either a logic 0 or a logic 1. Disruption or a loss of contents of the memory cells could result in severe errors for instruments or systems which rely upon the contents of the memory.

As mentioned in the Background of the Invention section, one of the problems encountered in using trans istortype random access memories in a high radiation environment is the loss of information resulting from 5 transient ionizing radiation. If the transient ionizing radiation is sufficient to change the state of thetrans istors in the array and therefore switch the state of the contents of the memory cells, the contents of the memory cells are permanently lost.

Moreover, analog circuits which are exposed to such radiation may be susceptible to transient errors, as well as lingering effects of primary photocurrent charging electron or hole traps in thesemiconductor. 10 Accordingly, by providing a field effect transistor structure as nowto be described in conjunction with

Figures 3-6 having a high degree of resistance to collection of primary photocurrent in response to pulsed ionizing radiation, the upset events generally associated with such memory cells ortransient errors in analog A circuits are reduced and accordingly,the ionizing radiation threshold level at which upset ortransient errors occur is increased. 15 Referring nowto Figures 3 and 4, field effect transistor 18 is shown formed on a substrate 52 comprising gallium arsenide orother suitable Group 111-V material having disposed on a first surface thereof a ground plane conductor 51 and having disposed over a second surface thereof a barrier layer 54, as will be described in conjunction with Figure 4. Disposed on a barrier layer 54 is an active region 56 comprising gallium arsenide or other suitable Group M-V material which is epitaxially grown or implanted with a speciesto 20 provide the desired doping level in the channel region about 1017 carrierslcc. The active region may be isolated into individual semiconductors by boron or oxygen implants, as shown, or alternatively by etching individual mesas. Disposed on the active region 56 are contact regions 58a and 58b comprising heavily doped gallium arsenide orothersuitable Group 111-V materials overwhich are disposed source and drain electrodes 60a and 60b. Contact regions 58a, 58b generally having a doping density of a about 1 018atoms 25 perlcc are disposed underlying source and drain contacts 60a, 60bto provide a low resistance ohmictype contact between the metal forming contacts 60a, 60b and the semiconductor 58a, 58b. A gate electrode 62 is disposed between the source and drain electrodes 60a, 60b as shown. Gate electrode 62 comprises a Schottky barrier contact metal disposed on the active layer 56, as shown.

Referring nowto Figure 5, the barrier layer 54 is shown to comprise a plurality of alternating layers 54a, 54b 30 of a low band gap material disposed between regions of high band gap material. More particularly, forthe transistor 18 as shown in Figure 3 for a substrate 52 comprising gallium arsenide, the periods 54a comprise regions of aluminum gallium arsenide (ALGal-,As) having a composition ratio x of aluminum to arsenic of about at least 0.1 to 1.0. Preferably x is in the range of 0.3 to 0.5. Higher concentrations of AI may increasethe carrier lifetime in the Al>,Gal,As which could slightly degrade radiation hardness because some photo- 35 current generated in the A[GaAs layer may be collected by the transistor. Disposed between the layers of aluminum gallium arsenide are layers of gallium arsenide 54b. This arrangement provides a superlattice heterostructure comprising alternating periods of aluminum gallium arsenide and gallium arsenide pre ferrably each having a thickness typically in the range of 50Ato 500Awith 1 OOA being a typical preferred thickness. In general, it is preferable thatthe A1GaAs adjacentthe active layer be relativelythin comparedto 40 thethickness of the active regions, butshould have a minimum thickness of about 50a to preventtunnelling of carriersthrough the layer. Preferablythe alternating layers 54a, 54b are disposed overthe substrate 52 by molecular beam epitaxy. This deposition technique is preferable because it allows for relativelythin layersof uniform thicknessto be deposited and in particular because of the necessity of using differences in band gap energies it allowsthe layersto be deposited with abrupt interfaces between the alternating layersthus pre- 45 venting significant interdiffusion or alloying of the heterostructure.

The barrier layer54 acts as a barrier between the substrate and active region 56forcarriers generated in responseto exposure of thetransistor 18to ionizing radiation. During ionizing radiation, gamma rays or cosmic rays, for example, are directed towards the gallium arsenide substrate 52. When such radiation strikesthe gallium arsenidethere is created in responsethereto hole and electron carriers. The holes and 50 electrons created in the gallium arsenide substrate 52 will tend to movetowards the respectively mostnega tive or most positive of electrodes 60a or 60b. That is, electrons will movetowardsthe electrode with the more positive potential and holeswill movetoward the electrodewith the more negative potential.

By interposing the barrier layer 54 between the active region 56 of thetransistor 18 and the substrate52, both the electrons and holes generated in responseto transient ionizing radiation must surmount a series of 55 potential barriers, as shown in Figure 6, created bythe band gap differences between each of the alternating layers of aluminum gallium arsenide and gallium arsenide. The conduction band discontinuity (for A10.3Ga03As) is LE, = 235 millivolts and the valence band discontinuity is LE, = 155 millivolts. Therefore, assuming Boltzman statistics applyto the electrons and holes present in the heterostructure, each timethat the carriers surmounta potential barriertheir concentration will be reduced by a factor related to exp(AE/kt) 60 where k is Boltzman's constant and T is the temperature of the material expressed in degrees Kelvin. Those carriersthatdo notsurmountthe potential barrierwill recombine and, accordingly, will not contributetothe generation of a photocurrent. Those carrierswhich are generated in the aluminum gallium arsenide layerwill gain energy astheyfall within the potential well resulting from the difference in band gap energies between GaAs and ALGaAs. However, within the 50Ato 500A distance in the aluminum gallium arsenide layer, such 65 GB 2 191 633 A 5 carriers will reach thermal equilibrium and are also not expected to contribute to the collection of a primary photocurrent. Furthermore, since the lifetime of electrons and holes in the aiuminum gal I ium a rsenide is shorter in comparison to gallium arsenide, there is a higher rate of recombination of holes and electrons in aluminu m gal liu m a rsenide and accordingly, a further reduction in the contribution of carriers generated in aluminum gal I W m arsenide to collection of a primary photocurrent. 5 To further reduce the photocurrent generated in response to ionization radiation, the photocurrentgenerated in the active region portion of the transistor itself maybe m in imized. Since some of the collected photocurrent is multiplied by the photoconductive gain of the channel of the FET 18, the primary photocurrent can be reduced by increasing the active channel doping and concominantly reducing the channel thicknessto maintain the requisite threshold voltage and thus reduce the amount of gallium arsenide present in the active 10 region 56. Moreover, the ratio of the photocurrent generated to thetotal currentthatthe MESFETcan provide may also be reduced by reducing the channel length.

Referring nowto Figure 7 a series of teststructures, (notshown) werefabricated to obtain a quantative estimate of the amount of reduction in collected substrate photocurrent. Figure 7 is a plot of photocurrentvs.

bias voltage at dose rate of 9x 109 rads(GaAs)/sec. 15 Each of the test structures werefabricated on a semi-insulated GaAs substrate. A pair of ohmiccontacts having a length of 30ORm, a width of 30Rm and spaced 61.Lm apart (representative of source and drain electro des) were provide on N+ regions disposed overthe semiconductor substrate. Boron was inplanted to isolate the ohmic contacts, such that any collected photocurrent would befrom the substrate only.

For curve 72 the N+ regions were disposed directly on the substrate. Forcurve 74a 0.5lim thickAIGaAs 20 layerwas interposed between the N+ layer and the substrate. Forcurve 76 a heterostructure as described above comprising five layers A10.3GaMAs alternating with five layers of GaAswere interposed betweenthe N+ regions and the substrate. Comparison of curves 72,74and 76 showthatthe single 0.5lim layerprovides a factorof about4 improvement overthe conventional approach represented by curve 72 whereas, curve 76 provided an improvement of a factor of about 100. A more definitive reading forcurve 76was not possible 25 becausethe photocurrent collected was nearly indiscernible from the noise level in thetest apparatus (not shown).

Figure 8 is a plot of photocurrentvs. dose ratefora conventional structure (curve 82) and a structure fabricated in accordancewith Figures 3-6 (curve 86). Comparison of curve 82 and 86 showthat as a function of dose ratethe heterostructure device has a factor of at least 100 improvement and further that this device 30 can be operated at significafly higher dose rate levelsthan the conventional structure.

Having described preferred embodiments of this invention, itwill now be apparentto one of skill in theart that other embodiments incorporating its concept may be used. It is felt, therefore, thatthis invention should notbe limited to the disclosed embodiments, but rathershould be limited only bythe spirit and scope of the appended claims. 35

Claims (18)

1. A semiconductor device comprising:

a substrate comprising a first Group 111-V material; 40 a radiation barrier disposed overthe substrate comprising a plurality of alternating layers of said first Group NW material and a second Group 111-V material and a second Group 111-V material having a conduction band energy higherthan that of the first material and a valence band energy lower than that of thefirst material; and means disposed oversaid barrierfor providing the semiconductor device. 45

2. The semiconductor as recited in claim 1 wherein the second Group 111-V material isAI,,Gal-,Aswherex is the composition ratio of Alto As.

3. The semiconductor as recited in claim 2 wherein xis in the range of 0. 1 to 1.0.

4. The semiconductor as recited in claim 2 wherein xis in the range of 0. 3 to 0.5.

5. The semiconductor as recited in claim 4 wherein the thickness of the A1GaAs layer most adjacent tothe 50 means disposed over the barrier is in the range of 50Ato 500A.

6. The semiconductor as recited in claim 4 wherein the thickness of each GaAs and A1GaAs layer is in the range of 50Ato 500A.

7. The semiconductor as recited in claim 4 wherein the thickness of each layer in the barrier is about 1 OOA.

8. A metal sem iconductorf ield effect transistor comprising: 55 a substrate comprising a first Group 111-V material; a radiation barrier layer disposed overthe substrate comprising at least one layer of said first material disposed between two layers of a second, different Group 111-V material having a conduction band energy higher than the conduction band energy of said first material and a valence band energy lower than the valence band energy of said first material; and 60 means disposed over said barrier layer for providing said metal semiconductor field effecttransistor.

9. The metal electrode field effecttransistor as recited in claim 8 wherein the substrate comprises gallium arsenide and the barrier layer comprises at least a pair of layers of aluminum gallium arsenide and a iayerof gallium arsenide disposed between said pair of layers of aluminum gallium arsenide.

10. The MESFETas recited in claim 9 wherein the layer of aluminum gallium arsenide has a composition 65 6 GB 2 191 633 A 6 ratio of aluminum to arsenic in the range of 0.1 to 1.

11. The MESFET as recited in claim 3 wherein each one of the layers of said barrier has a thickness of about 100 Angstroms.

12. The MESFET as recited in claim 10 wherein the larger of said barrier have a thickness of about 1 OOA.

13. A random access memory comprising: 5 a substrate comprising a Group 111-V material; a plurality of metal semiconductor field effect transistors disposed over said substrate comprising a first Group 111-V material; and a radiation barrier layer disposed between said substrate and said plurality of transistors comprising a layer of said first Group 111-V material disposed between two layers of a second, different Group 111-V material, 10 said second, different Group 111-V material having a conduction band energy higherthan the conduction band energy of said first material and a valence band energy lowerthan the valence band energy of saidfirst material.

14. The metal electrode field effect transistor as recited in claim 8 wherein the substrate comprises gal Hum arsenide and the barrier layer comprises at least a pair of layers of aluminum gallium arsenide and a 15 layer of gallium arsenide disposed between said pair of layers of aluminum gallium arsenide.

15. The MESFET as recited in claim 14 wherein the layer of al uminum gallium arsenide has a composition ratio of aluminum to arsenic in the range of 0.1 to 1.

16. The MESFET as recited in claim 14 wherein the layers of aluminu m gallium arsenide has a compositional ratio of aluminum to arsenic in the range of 0.3to 0.5. 20

17. The MESFET as recited in claim 15 wherein each one of the layers of said barrier has a thickness in the range of about 100 Angstroms to 500 Angstroms.

18. The MESFET as recited in claim 15 wherein each layer of said barrier have a thickness of about 1 OOA.

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Published by The Patent Office, 25 Southampton Buildings, London WC2MAY, from which copies maybe obtained.