GB2178593A

GB2178593A - Transistor manufacture

Info

Publication number: GB2178593A
Application number: GB08519488A
Authority: GB
Inventors: Roger Leslie Baker; Colin Nicholas Duckworth; David William Mcneill
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1985-08-02
Filing date: 1985-08-02
Publication date: 1987-02-11
Also published as: JPS6336563A; GB8519488D0; DE3625723A1; GB2178593B; FR2585880A1

Abstract

In integrated circuits which include both CMOS and bipolar transistors it is desirable to have PNP transistors available, for convenience in circuit design. To provide lateral PNP transistors for this purpose, a polysilicon strip (4, 11, 22) is used by its location to define the edges of the collector and emitter. The polysilicon is also in some embodiments used as a base electrode. The polysilicon strip can also be the gate for one or more CMOS devices. <IMAGE>

Description

SPECIFICATION Transistor manufacture This invention relates to semiconductor devices, and in particular to bipolar transistors in which polycrystalline silicon (polysilicon) is used.

In our Patent Appln. No. 8507602 (P. D.

Scovell et al 16-14-9-5), we have described a method of manufacturing a bipolar transistor including the steps of defining a polycrystalline silicon emitter mesa on an unoxidised surface of a base region disposed in a semiconductor substrate, oxidising side walls of the mesa and the exposed unoxidised surface of the base region, and implanting a base contact region into the substrate in contact with the base region using at least one oxidised side wall of the mesa as part of the implantation mask whereby the base contact region is selfaligned with the emitter.

The present invention has as its object extensions of the principle of self-alignment used in the above-described application.

According to the present invention there is provided a method of providing a lateral PNP transistor in a semiconductor chip made by a CMOS process, in which polysilicon is deposited on the surface of the semiconductor material over the oxide layer thereon, in which the polysilicon area encroaches on the edge of the areas at which the emitter and the collector are to be produced, so that when the emitter and the collector are produced the oxidised side walls of the polysilicon function as part of the implantation mask in the formation of the emitter and the collector p + wells, thus also defining the base width.

Embodiments of the invention will now be described with reference to the accompanying drawing, in which Figure 1 shows schematically and in crosssection a first embodiment of the invention.

Figure 2 is a view similar to Fig. 1 of a second embodiment of the invention.

Figure 3 is a plan view of a third embodiment of the invention.

Figure 4 is a cross-section along the line X X' of Fig. 3.

Figure 5 is a cross-section along the line Y Y' of Fig. 3.

When merging bipolar transistors with a CMOS process, it is desirable to have both NPN and PNP bipolar transistors available for convenience of circuit design. We have already described the manufacture of an NPN transistor in the above-mentioned application.

In the present application we describe a method of making lateral PNP bipolar transistor using a CMOS process with the addition of one masking step. The technique uses the CMOS gate polysilicon, which is formed as a strip or the like for aligning the emitter and collector contacts, and also as a base contact.

In Fig. 1, we see a substrate in which a region 1 is doped to n type, and has two p+ wells 2 and 3, which are for the emitter and the collector respectively. Between the emitter and the collector there is a gap in the oxide layer so that an n+ type polyosilicon mesa 4 thereon is in engagement with the n region 1.

This polysilicon mesa has its sides and top covered by oxide, with a gap 5 in the top for a contact. This mesa can be part of a strip of polysilicon which forms a gate contact for an FET on the same substarate. By virtue of its contact with the region 1, the mesa 4 also acts as a base contact for the bipolar transistor.

During this process, no holes are cut in the oxide layer before formation of the p+ emitter and collector wells. The oxide layer is thin enough to allow the p+ implant into the silicon. The polysilicon and the "cap" oxide on it keep the p+ implant out. The contact holes are cut later, and their position has substantially no effect on device characteristics or base width.

In the arrangement of Fig. 2, the base contact is provided by an n+ type well 8, the emmiter by a p+ well 9 and the collector by another p+ well 10. Here it will be seen that the n+ type polysilicon 11, with its oxide coating, only defines the emitter and collector contacts, and thus the base width. This arrangement reduces the base width at the expense of increased base spreading resistance.

We now turn to Figs. 3 to 5, in which there is a base contact 20 under a contact window 21 in the oxide layer. This is overlaid by a roughly T-shaped polysilicon mesa 22 which is used as a base contact. The leg of the T crosses a rectangular area 23 with a p+ implant to define the emitter 24 and collector 25.

This gives the same base width as the arrangement of Fig. 2, but still has the problem of base spreading resistance albeit less severe than in the arrangement of Fig. 2.

In the above-described arrangements, the p+ wells form the entire emitter and collector, wherein the n+ well is in an n-type base, and thus is a base contact.

Claims

1. A method of providing a lateral PNP transistor in a semiconductor chip made by a CMOS process, in which polysilicon is deposited on the surface of the semiconductor material over the oxide layer thereon, in which the polysilicon area encroaches on the edge of the areas at which the emitter and the collector are to be produced, so that when the emitter and the collector are produced the oxidised side walls of the polysilicon function as part of the implantation mask in the formation of the emitter and the collector p + wells, thus also defining the base width.

2. A method as claimed in claim 1, and in which the polysilicon area is so located as to fit over the base region, with which it is in electrical contact, so that it forms a base contact.

3. A method of providing a lateral PNP transistor in a semiconductor device, substantially as described with reference to Fig. 1, Fig. 2, or Figs. 3 to 5 of the accompanying drawings.

4. A semiconductor device with a transistor made by the method of claims 1, 2 or 3.

CLAIMS Amendments to the claims have been filed, and have the following effect: New or textually amended claims have been filed as follows:

5. A method of providing a lateral bipolar PNP transistor in a semiconductor chip which is made by a CMOS process and which includes one or more MOS transistors, in which a polysilicon mesa forming one of the electrodes of a said MOS transistor is deposited on the surface of the semiconductor material over an oxide layer on that surface, in which the polysilicon area of the mesa encroaches on the edges of the areas at which the emitter and the collector are to be produced, in which the mesa and the surface not covered by the mesa have oxide coatings applied to them, and in which when the emitter and the collector are produced the oxidised side walls of the mesa function as part of an implantation mask in the formation to p+ wells in the n-type substrate, which p+ wells form the emitter and the collection of the bipolar lateral transistor.