GB2175443A - Bipolar semiconductor device - Google Patents
Bipolar semiconductor device Download PDFInfo
- Publication number
- GB2175443A GB2175443A GB08512341A GB8512341A GB2175443A GB 2175443 A GB2175443 A GB 2175443A GB 08512341 A GB08512341 A GB 08512341A GB 8512341 A GB8512341 A GB 8512341A GB 2175443 A GB2175443 A GB 2175443A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- base region
- dopant
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 239000002019 doping agent Substances 0.000 claims abstract description 120
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000009877 rendering Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The carrier concentration 30 of the base region has a humped profile with a maximum 35 within the bulk of the base region and separated from the p-n junctions 32 and 34 with the emitter and collector regions of the device. The humped profile may be provided by either the partial compensation of the dopant characteristic of the required a conductivity type of the base region by dopant characteristic of the opposite conductivity type or by the reverse diffusion of dopant characteristic of the required conductivity type of the base region from the surface of the semiconductor body. The humped profile renders the average resistivity of the base region substantially independent of the position of the emitter region-base region junction which is of particular advantage in the manufacture of gate turn-off thyristors and transistors which have shallow (0.5 to 5 micron depth) emitter regions. <IMAGE>
Description
SPECIFICATION
Bipolar semiconductor device and method of manufacturing same
The invention relates to bipolar semiconductor devices, particularly but not exclusively to transistors and gate turn-off thyristors in which a conductivity determining dopant concentration of a base region varies within said region, and further relates to methods of manufacturing such semiconductor devices.
The applicant has found that one of the factors which affects the gain of a bipolar transistor is the sub-emitter sheet resistivity (pse) of the base region of the transistor and that known methods of making bipolar transistor structures have compromised the control of pse because in those methods pse was dependent on the position of the p-n junction between the base region and an emitter region.
Figure 1 (Prior Art) shows graphically a known transistor structure which has an emitter region E and a base region B in which the desired dopant concentration profiles for the emitter region and base region are as indicated by curves 1 and 2 respectively. The vertical axis of the graph represents the logarithm of the dopant concentration, logN(cm 3) and the horizontal axis represents depth D from a surface of the transistor structure.
The dopant may be introduced by implantation or by some other known means. The sub-emitter sheet resistivity pse and hence the average resistivity of the base region of the desired transistor structure is substantially controlled by the maximum dopant concentration of the base which occurs at the intersection J1 of curves 1 and.2. Changes in the depth of the emitter-base junction J1 which occur as a result of changes in the emitter region dopant concentration profile as marked by dashed lines A (shallower) and B (deeper) lead to a corresponding shift indicated by AD on the horizontal axis of the intersection on the curve 2 as indicated by J1A (shallower) and JiB (deeper).With even a relatively small shift of the intersection on curve 2 comes a corresponding change, indicated by AN on the vertical axis, in the maximum dopant concentration of the base region, which results in a corresponding change in pse and the average resistivity of the base region, noting that the vertical scale is logarithmic.
Tolerances in the manufacturing processes
of transistors have thus been found by the
applicant to lead to transistors of nominally the same characteristics having a wide variation in gain as a result of large changes in pse
brought about by relatively small changes in the depth of the junction between the emitter
and base regions, this effect being particularly
noticeable when a transistor having a shallow
emitter region with a thickness in the range 0.5 micron to 5 microns and a corresponding shallow base region is manufactured.
Although the preceding discussion is limited to bipolar transistors for the sake of clarity it is applicable mutatis mutandis to other bipolar semiconductor devices, for example gate turnoff thyristors.
According to the invention there is provided a bipolar semiconductor device having a base region adjacent an emitter region to control current flow from the emitter region, the base region having a first conductivity type opposite to a second conductivity type of the emitter region and forming a p-n junction with the emitter region, and having a conductivity determining dopant concentration varying with position within the base region, characterised in that the conductivity determining dopant concentration of the base region exhibits a maximum within the bulk of the base region separated from said p-n junction with the emitter region.
The base region of a semiconductor device according to the invention thus exhibits a maximum of the conductivity determining dopant concentration which is separated from and so is substantially independent of the position of the p-n junction with the emitter region and hence the average resistivity of such a base region is also substantially independent of the position of the p-n junction with the emitter region.
The maximum of the conductivity determining dopant concentration may be provided by either a difference between a concentration of dopant characteristic of the first conductivity type and a concentration of dopant characteristic of the second conductivity type which decreases with distance from the emitter region, in which case the conductivity determining dopant concentration is a nett concentration, or by a concentration of dopant characteristic of the first conductivity type alone.
The semiconductor device may be a silicon semiconductor device and the dopant associated with the first conductivity type may be boron, aluminium or gallium separately or in some combination and that associated with the second conductivity type may be phosphorus or arsenic.
According to the invention there is also provided a method of manufacturing a bipolar semiconductor device having a base region adjacent an emitter region to control current flow from the emitter region, the base region
having a first conductivity type opposite to a
second conductivity type of the emitter region
and forming a p-n junction with the emitter
region, including the steps of introducing do
pants characteristic of both the first and the
second conductivity type into a portion of a
semiconductor body via a surface of the body
to provide a dopant concentration of the first
conductivity type for the base region and a
dopant concentration of the second conductiv ity type for the emitter region, the base region extending deeper into the body from said surface than the emitter region, characterised by the step of modulating the conductivity determining dopant concentration in the base region below where the emitter region is to be or is formed such that the conductivity determining dopant concentration of the base region exhibits a maximum within the bulk of the base region separated from said p-n junction with the emitter region.
The method of forming a semiconductor device according to the invention provides a semiconductor device in which the maximum of the conductivity determining dopant concentration of the base region and hence the average resistivity of the base region is substantially independent of the position of the pn junction with the emitter region.
The modulation of the conductivity determining dopant concentration of the base region may be accomplished either by introducing into a region below where the emitter is to be or is formed a dopant characteristic of the second conductivity type in a concentration which decreases with distance from the emitter region to provide a conductivity determining nett dopant concentration in this region or by a reverse diffusion of dopant characteristic of the first conductivity type to reduce the concentration of dopant of the first conductivity type from the bulk of the base region to the surface of the body.
The bipolar semiconductor device may be a silicon semiconductor device and the dopant characteristic of the first conductivity type may be boron or aluminium or gallium separately or in some combination and the dopant characteristic of the second conductivity type may be either arsenic or phosphorus or both.
Semiconductor devices including transistors and gate turn-off thyristors having an emitter region thickness in the range 0.5 micron to 20 microns and a base region thickness in the range 3 microns to 60 microns may be manufactured by a method according to the invention. The method is of advantage when used in the manufacture of devices particularly transistors having a shallow emitter region of thickness in the range 0.5 micron to 5 microns.
In the drawings:
Figure 1 illustrates dopant concentration profiles in a prior art method of manufacturing a bipolar semiconductor device.
Embodiments of the invention will now be described by way of example only, with reference to the remaining drawings, in which Figures 2A-D and 3A-C show graphically the dopant and carrier concentration profiles at stages in a first method and a second method respectively in accordance with the invention for manufacturing a bipolar semiconductor device in accordance with the invention.
Figures 4 and 5 show in schematic section a bipolar transistor and a gate turn-off thyristor incorporating the invention.
In Figures 2A-C the steps included in a first method of making a semiconductor device in accordance with the invention are shown with reference to diagrams in which the dopant concentration profiles ofan emitter region a base region and a third region of the device are displayed graphically, and in Figure 2D carrier concentration profiles of an emitter region a base region and a third region of the device are displayed graphically. In all four Figures 2A-D the horizontal axis represents depth from a semiconductor body surface which corresponds to the line of the vertical axis, in
Figures 2A-C the vertical axis, logN(cm-3) represents the logarithm of the dopant concentration and in Figure 2D the vertical axis, log(n,p)(cm -3)represents the logarithm of the carrier concentration, n and p type.
Figure 2A represents dopant concentration profiles during the manufacture of a semiconductor device in which 22' and 25' are the dopant concentration profiles characteristic of p-type and n-type doping respectively introduced by implantation into a portion of a semiconductor body via a surface of the body and 23' is the dopant concentration profile characteristic of uniform background n-type doping pre-existing in the semiconductor body.
Figure 2B represents the dopant profiles after thermal treatment of the device to drive in and activate the dopant atoms and anneal the implantation damage. 22, 25 and 23 are the dopant concentration profiles characteristic of p-type and n-type doping respectively after the thermal treatment. The dopant concentration profiles 22 and 25 overdope the concentration profile 23. The dopant concentration profiles assumed by the implanted dopants after thermal annealing will depend on the rate of diffusion of those dopants at the temperature of the thermal treatment. The temperature of the thermal treatment is chosen to ensure that the dopant characteristic of the required conductivity type of the base layer diffuses more rapidly in the semiconductor device at the thermal treatment temperature than the dopant associated with the opposite conductivity type. For example, where a p-type base region is required in a silicon semiconductor device the dopant could be either boron or aluminium or gallium the thermal treatment temperature being chosen to ensure that these dopants diffuse more rapidly in silicon than either phosphorus or arsenic dopants characteristic of n-type conductivity. A conductivity determining nett dopant concentration profile resulting from the compensation of the dopant effect of the dopant profiles 22, 23 and 25 is shown by the dashed line 24 in Figure 2B. It will be seen that this dopant concentration profile has a maximum 26 at some distance into the semiconductor body. The actual effect of the dopant concentration profile 23 will be negligible as it has a concentration approximately two orders of magnitude below the maximum 26, and is of constant concentration throughout the semiconductor body.
In Figure 2C a profile 27 of concentration of dopant characteristic of n-type conductivity of an emitter region of the semiconductor device is shown. This dopant concentration overdopes that of the nett dopant concentration of the base region. A p-n junction 28 between the emitter region and the base region is formed in the device where the dopant concentration profile of the n-type emitter intersects the conductivity determining nett dopant concentration profile of the p-type base region.
In Figure 2D the carrier concentration profile 30 of the base region, and the carrier concentration profile 31 of the emitter region are shown. The carrier concentration profile of each region of the device will have a one to one correspondence with the dopant concentration profile or nett dopant concentration profile of each region, if each dopant contributes either one n or one p type carrier. The emitter region and third region n-type carrier concentration profiles are shown as curves 31 and 33 and the base region p-type carrier concentration profile is shown as curve 30. pn junctions 32 and 34 are between the emitter and base and base and third regions respectively. The maximum 35 of the base region carrier concentration profile is thus situated in the bulk of the base region separated from p-n junction with the emitter region.This maximum value of p type carrier concentration substantially controls the sub emitter sheet resistivity of the base region, thus rendering the average resistivity of the base region substantially independent of the position of the p-n junction 32 with the emitter region.
In Figures 3A and B the steps included in a second method of making a semiconductor device in accordance with the invention are shown with reference to diagrams in which the dopant concentration profiles of a base region and a third region of the device are displayed graphically and in Figure 3C carrier concentration profiles of an emitter region a base region and a third region of the device are displayed graphically. Figure 3A represents a dopant concentration profile during the manufacture of a device in which 36' is the concentration profile of dopant characteristic of ptype doping introduced by implantation into a surface of the semiconductor body and 39' is the dopant concentration profile characteristic of uniform background n-type doping preexisting in the semiconductor body.
Figure 3B shows the dopant concentration profile 36 after thermal treatment of the device to drive in and activate the implant. The dopant concentration profile 36 overdopes the concentration profile 39. The thermal treatment is also used to anneal the implantation damage and grow an oxide layer 37 signified by the dashed outline over the implanted region for the purpose of reverse diffusing dopant during this or further thermal treatment.
The reverse diffusion of dopant is to reduce the concentration of dopant from the bulk of the base region to the surface of the semiconductor body. After the reverse diffusion the dopant characteristic of p-type conductivity within the semiconductor body assumes a concentration profile 36 which increases with distance within the base region from where the emitter region is or is to be formed to a maximum 38 within the semiconductor device.
The dopant concentration profile 37' within the oxide layer results from the increased solid solubility of the dopant within the oxide layer, there being a concentration discontinuity at the semiconductor body oxide interface.
The effect of the uniform background dopant concentration 39 will, as in the previous embodiment, be negligible.
Removal of the oxide layer 37 and the provision of an n-type emitter region in known manner by overdoping the dopant concentration profiles 36 and 39 results in the regions of the device having a carrier concentration profile as represented by Figure 3C, in which the carrier concentration profiles of the emitter region 40, the base region 42 and the third region 390 are shown. The maximum 43 of the base region carrier concentration profile is thus situated in the bulk of the base region separated from the p-n junction 44 with the emitter region and from the p-n junction 441 with the third region. This maximum value of the p type carrier concentration substantially controls the sub-emitter sheet resistivity of the base region thus rendering the average resistivity of the base region substantially independent of the position of the p-n junction with the emitter region.This method utilising a reverse diffusion of providing a base region having a doping profile which has a maximum within a bulk of the base region may be most suitable when used in the manufacture of a semiconductor device having a shallow emitter region and such a device may be a transistor.
In a semiconductor device in accordance with the present invention the extent within the base region of the zero bias depletion region of the p-n junction between the emitter and base regions and the p-n junction between the base and third regions may be excluded from the bulk of the base region in which the maximum of the conductivity determining dopant concentration and carrier concentration occurs.
In the embodiments described with respect to and shown in Figures 2A-D and 3A-C only the dopant and carrier concentration profiles of the emitter and base regions of a semiconductor device have been considered in relation to a third region having a uniform dopant and carrier concentration. It will be understood that the semiconductor body, into which the dopant or dopants are introduced to form the base region of a semiconductor device according to the invention, may have different characteristics depending on the type of device being manufactured.For example, where such a base region is incorporated in a transistor or a gate turn-off thyristor, the dopant for the collector region or the n-type base region re spectively may provide a non uniform background concentration of dopant in an epitaxially grown layer into which the base region dopant or dopants are introduced. Thus dopants pre-existing or previously introduced into the semiconductor body may be overdoped by the dopant or dopants introduced to form the base region of a semiconductor device incorporating the invention. Where such dopants form a uniform background they will have no effect on the position of the maximum dopant concentration within the base.However, where the background dopants are non-uniform, the profiles of dopants introduced to form the base region, or the profiles resulting from the dopant introduction and reverse diffusion step may be adjusted by varying the implantation, the thermal treatment or by some other means to allow for the presence of the non-uniform background and ensure the correct placement of the carrier concentration maximum.
Two examples are now given in Figures 4 and 5 which show schematically a part section of a transistor structure and a gate turnoff thyristor structure respectively both being semiconductor devices incorporating the invention.
The transistor structure, Figure 4 is of substantially known construction, having interdigitated emitter 45 and base 46 regions and corresponding emitter 47 and base 48 metallisations separated by oxide isolations 50. The collector 51 region is divided into two sub regions 51A and 51B and the collector metallisation 52 is provided on the exterior surface of sub region 51B. The base region 46 is formed in accordance with the present invention in the collector sub region 51A. The dashed line 53 within the base region indicates a position of the maximum of the conductivity determining nett carrier concentration (see reference numerals 33 and 43 in Figures 2D and 3C respectively above) within the bulk of the base region separated from the p-n junction with the emitter region and the p-n junction with the collector region.For an n-p-n transistor structure an n emitter and and n 51A and n 51B collector regions may be doped with phosphorus and the p base region with boron and arsenic, with boron predominant to give p-type conductivity to the base.
With such a transistor structure the emitter region 45 may have a thickness E, in the range 0.5 to 20 microns and the base region 46 may have a thickness B in the range 3 to 60 microns. A transistor structure having an emitter thickness in the range 0.5 to 5 microns may be considered as having a shallow emitter.
The gate turn-off thyristor structure, Figure 5 is of substantially known construction having interdigitated emitter and base regions, metallisations and isolations similar to those shown in Figure 4, and hence given the same reference numerals. A gate turn-off thyristor is a four layer device usually of n-p-n-p construction, n-type regions being the emitter region 45 and an n-type base region 56. P-type regions are a p-type base region 46 situated between the emitter region 45 and the n-type base region 56 and a p-type anode region 57.
The anode region may have nt type inclusion regions 58, the regions 57 and 58 contact the anode metallisation 59. The base region 46 is formed in accordance with the present invention in the n-type base region 56. The dashed line 53 within the base region 46 indicates a position of the maximum of the conductivity determining nett carrier concentration (see reference numerals 33 and 43 in Figure 2D and 3C respectively above) within the bulk of the base region separated from the p-n junction with the emitter region and the p-n junction with the n-type base region. The doping of the n-type emitter region and p-type base region may be made with the same dopants as the transistor structure above.
With such a gate turn-off thyristor structure, the emitter region 45 may have a thickness E', in the range 0.5 to 20 microns and the base region 46 may have a thickness B', in the range 3 to 60 microns.
Claims (12)
1. A bipolar semiconductor device having a base region adjacent an emitter region to control current flow from the emitter region, the base region having a first conductivity type opposite to a second conductivity type of the emitter region and forming a p-n junction with the emitter region, and having a conductivity determining dopant concentration varying with position within the base region, characterised in that the conductivity determining dopant concentration of the base region exhibits a maximum within the bulk of the base region separated from said p-n junction with the emitter region.
2. A bipolar semiconductor device as claimed in Claim 1, in which said conductivity determining dopant concentration of the base region between said maximum and the p-n junction with the emitter region is a nett dopant concentration formed of the difference between a concentration of dopant characteristic of the first conductivity type and a concentration of dopant characteristic of the second conductivity type which decreases with distance from the emitter region.
3. A bipolar semiconductor device as claimed in Claim 1, in which the conductivity determining dopant concentration of the base region is formed of a concentration of dopant characteristic of the first conductivity type which increases with distance from the emitter region to said maximum.
4. A bipolar semiconductor device as claimed in any preceding claim in which the device is a transistor having an emitter region thickness in the range 0.5 micron to 20 microns and a base thickness in the range 3 microns to 60 microns.
5. A bipolar semiconductor device as claimed in Claims 1 to 3, in which the device is a gate turn-off thyristor having a cathode region thickness in the range 0.5 microns to 20 microns and a gate region thickness in the range 3 microns to 60 microns.
6. A method of manufacturing a bipolar semiconductor device having a base region adjacent an emitter region to control current flow from the emitter region, the base region having a first conductivity type opposite to a second conductivity type of the emitter region and forming a p-n junction with the emitter region, including the steps of introducing dopants characteristic of both the first and the second conductivity type into a portion of a semiconductor body via a surface of the body to provide a dopant concentration of the first conductivity type for the base region and a dopant concentration of the second conductivity type for the emitter region, the base region extending deeper into the body from said surface than the emitter region, characterised by the step of modulating the conductivity determining dopant concentration in the base region below where the emitter region is to be or is formed such that the conductivity determining dopant concentration of the base region exhibits a maximum within the bulk of the base region separated from said p-n junction with the emitter region.
7. A method of manufacturing a bipolar semiconductor device as claimed in Claim 6, in which the step of modulating the conductivity determining dopant concentration fncludes introducing dopant characterfstic of the second conductivity type into a region below where the emitter region is or is to be formed to provide a conductivity determining nett dopant concentration in said region.
8. A method of manufacturing a bipolar semiconductor device as claimed in Claim 6, in which the step of modulating the conductivity determining dopant concentration includes a reverse diffusion of dopant characteristic of the first conductivity type to reduce the dopant concentration of dopant of the first conductivity type from the bulk of the base region to said surface of the body.
9. A method of manufacturing a bipolar semiconductor device as claimed in Claim 7, in which the dopant characteristic of the first conductivity type provided for the base region diffuses more rapidly in the semiconductor body than the dopant characteristic of the second conductivity type introduced in the dopant concentration modulating step.
10. A method of manufacturing a bipolar semiconductor device as claimed in Claim 9, in which the device is a silicon semiconductor device and the dopant characteristic of the first conductivity type is boron or aluminium or gallium and the dopant characteristic of the second conductivity type is arsenic or phosphorus.
11. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to Figures 2A-D or Figures 3A-C.
12. A semiconductor device substantially as hereinbefore described with reference to Figure 4 or Figure 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08512341A GB2175443A (en) | 1985-05-15 | 1985-05-15 | Bipolar semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08512341A GB2175443A (en) | 1985-05-15 | 1985-05-15 | Bipolar semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8512341D0 GB8512341D0 (en) | 1985-06-19 |
| GB2175443A true GB2175443A (en) | 1986-11-26 |
Family
ID=10579193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08512341A Withdrawn GB2175443A (en) | 1985-05-15 | 1985-05-15 | Bipolar semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2175443A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931001B (en) * | 2009-06-24 | 2012-05-30 | 湖北台基半导体股份有限公司 | Asymmetrical fast thyristor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1117766A (en) * | 1964-07-18 | 1968-06-26 | Fujitsu Ltd | A method of manufacturing superhigh-frequency transistors |
| GB1297089A (en) * | 1970-01-30 | 1972-11-22 | ||
| GB2135118A (en) * | 1983-02-09 | 1984-08-22 | Westinghouse Brake & Signal | Thyristors |
-
1985
- 1985-05-15 GB GB08512341A patent/GB2175443A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1117766A (en) * | 1964-07-18 | 1968-06-26 | Fujitsu Ltd | A method of manufacturing superhigh-frequency transistors |
| GB1297089A (en) * | 1970-01-30 | 1972-11-22 | ||
| GB2135118A (en) * | 1983-02-09 | 1984-08-22 | Westinghouse Brake & Signal | Thyristors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931001B (en) * | 2009-06-24 | 2012-05-30 | 湖北台基半导体股份有限公司 | Asymmetrical fast thyristor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8512341D0 (en) | 1985-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5656514A (en) | Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile | |
| US4357622A (en) | Complementary transistor structure | |
| EP0481153B1 (en) | Process for the accomplishment of power MOS transistors with vertical current flow | |
| US5620907A (en) | Method for making a heterojunction bipolar transistor | |
| US4920062A (en) | Manufacturing method for vertically conductive semiconductor devices | |
| US5770503A (en) | Method of forming low threshold voltage vertical power transistor using epitaxial technology | |
| US4862238A (en) | Transistors | |
| US5569612A (en) | Process for manufacturing a bipolar power transistor having a high breakdown voltage | |
| US6781156B2 (en) | Recombination center diffusion controlled by carbon concentration | |
| EP0552561A2 (en) | Method of fabricating an ultra-thin active region for high speed semiconductor devices | |
| US4178190A (en) | Method of making a bipolar transistor with high-low emitter impurity concentration | |
| US4669179A (en) | Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions | |
| EP0166923A2 (en) | High performance bipolar transistor having a lightly doped guard ring disposed between the emitter and the extrinsic base region | |
| US6271061B1 (en) | Fabrication of insulated gate bipolar devices | |
| JPH08195399A (en) | Insulated vertical pnp transistor dispensing with embedded layer | |
| US4151009A (en) | Fabrication of high speed transistors by compensation implant near collector-base junction | |
| WO1997017726A1 (en) | Low collector resistance bipolar transistor compatible with high voltage integrated circuits | |
| GB2175443A (en) | Bipolar semiconductor device | |
| US6642096B2 (en) | Bipolar transistor manufacturing | |
| EP0779652A2 (en) | Method for making a heterojunction bipolar transistor | |
| US3443174A (en) | L-h junction lateral transistor | |
| US5285101A (en) | Semiconductor device | |
| GB2056165A (en) | Hot-electron or hot-hole transistor | |
| JPH0574800A (en) | Silicon hetero-junction bipolar transistor | |
| JPH06224213A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |