GB2173956A - Integrated electrical transformer - Google Patents
Integrated electrical transformer Download PDFInfo
- Publication number
- GB2173956A GB2173956A GB8508332A GB8508332A GB2173956A GB 2173956 A GB2173956 A GB 2173956A GB 8508332 A GB8508332 A GB 8508332A GB 8508332 A GB8508332 A GB 8508332A GB 2173956 A GB2173956 A GB 2173956A
- Authority
- GB
- United Kingdom
- Prior art keywords
- primary
- turns
- gallium arsenide
- conductor turns
- conductorturns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 16
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000001465 metallisation Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 17
- 238000010168 coupling process Methods 0.000 abstract description 17
- 238000005859 coupling reaction Methods 0.000 abstract description 17
- 230000005291 magnetic effect Effects 0.000 abstract description 7
- 230000006872 improvement Effects 0.000 abstract description 3
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0086—Printed inductances on semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A planar transformer comprises an insulating or semiconductor substrate 1, such as gallium arsenide, in which the primary and secondary conductor turns of spiral configuration are formed at different levels within a dielectric layer 2,3 applied to the substrate. This configuration enables the primary and secondary conductor turns to be located in closer proximity than known co-planar designs, thereby providing improved magnetic coupling between the conductors. Furthermore, the width of the conductor turns can be increased, thereby providing a further improvement in the magnetic coupling and enabling a reduction in the resistive loss of the conductor turns. <IMAGE>
Description
SPECIFICATION
Improvements relating to electric transformers
This invention relates to electric transformers and relates more specificallyto planar transformers which may be embodied in integrated circuits including other passive and/or active circuitcomponents.
Such planartransformers embodied in gallium arsenide monolithic microwave integrated circuits for performing given microwave functions may comprise co-planar interwound primary and secondary conductorturns (metallisation) of rectangular spiral configuration providing an approximate 1:1 transformer turns ratio. These transformers, the interwound metallised turns of which lie side-by-side on the dielectric coated surface of a gallium arsenide subs- trate, only occupy small surface areas but they can perform several important electronic functions. Firstly, the planartransformer can be designed to provide over a relatively narrow bandwidth an efficient interstage impedence matching element two replace the traditional larger area multi-element matching circuit.
Secondly, the inherent isolation ofthetransformer permits the straightforward introduction of d.c. bias withoutthe need for large area MIM decoupiing capacitors.
However, the transformer action in these small area planartransformers relies upon magnetic coupling between the co-planar primary and secondary metallised turns lying side-by-side on the dielectric coated gallium arsenide substrate. With typicalmetallisation thickness of about 3 microns and minimum line separations of between 3-5 microns being presently achievable in gallium arsenide integrated circuit production processes the coupling factor (K) ofthe transformer may be 0.8 at best against the ideal transformer coupling factor of unity.As a direct consequence of its low coupling factorthe planar transformer with co-planar interwound primary and secondary conductorturns will have high insertion loss and it will also provide a poor impedance matching element thereby limiting the application of this otherwise useful small area circuit component.
The present invention seeks to improve the magne tic coupling between the primaryand secondary conductorturns of a planartransformer and thereby inter alia reduce the insertion loss of the transformer.
According to the present invention there is provided a planartransformercomprising an insulating or semiconductor substrate (e.g. gallium arsenide), in which primary and secondary conductorturns of spiral configuration are formed at slightly different levels within the dielectric layer material applied to the semiconductor substrate.
Since the dielectric layers normally applied to the gallium arsenide substrate in gallium arsenide integrated circuits are between 1 and 2 microns thick it will be apparent that the primary and secondary conductorturns ofthe planartransformer may be in significantly closer proximity to provide better magnetic coupling than in the co-planar interwound construction previously referred to. Sincethe primary and secondary conductors are at different levels in the circuitthewidth of the conductorturns can be increased and thereby provide further improvement in the coupling factor whilst reducing the resistive loss.
The primary and secondary spiral conductors which may be formed be metallisation techniques may be located in vertical alignment or they may be displaced from each other in the horizontal direction so as effectively to provide interwound primary and secon dary turns at different levels in the insulating or dielectric material. The latter construction may enable a high coupling factor and reduced parasitic interspiral capacitance to be achieved.
The widths of the primary and secondary conductor turns may be the same or different widths of conductorturns may be provided in order to reduce the separation between the primary and secondary conductorturns.
By way of example the present invention will now be described with reference to the accompanying drawings in which:
Figures 1 and 2 show diagrammatic plan and part cross-sectional views of a known interwound planar transformerforming part of a monolithic microwave gallium arsenide integrated circuit;
Figures 3 and 4 show diagrammatic plan and part cross-sectional views of a planartransformeraccord- ing to the present invention as part of an integrated circuit; and
Figure 5 shows a cross-sectional view of an alternative form of planartransformerto that shown in
Figures 3and 4.
Referring to Figures 1 and to Figure 2 which is a cross-sectional view taken along the line A-A in Figure 1 a gallium arsenide monolithic microwave integrated circuit comprises a gallium arsenide substrate 1 provided with super-imposed dielectric layers 2 and 3.
After application to the sg Bqtrate 1 of the first dielectric layer 2 primary and secondary connecting strips4and 5Ofthe planartransformerareformed on the dielectric layer 2 by means of a metallisation process. Afterthe application of the outer dielectric layer 3 co-planar interwound primary and secondary conductorturns 6 and 7 of rectangular spiral configuration are formed on the dielectric layer 3 by a further metallisation process step.As will best be appreciated from Figure 1, the inner ends of the metallised primary and secondary conducutorturns are electrically connected to the respective connecting strips 4 and 5 while the outer ends of the primary and secondary conductorturns are electrically connected to further metallised connecting strips 8 and 9 which may, like the strips 4 and 5, also be provided on the dielectric layer 2 by a metallisation process before application of the second dielectric layer 3.
The planartransformer depicted has a turns ratio of approximately 1:1 and the transformer action relies upon the magnetic coupling between the primary and
secondary turns as illustrated in Figure 2. Since the
minimum separation "x" that can be provided between the metallised primary and secondary conductors using existing gallium arsenide techniques is between 3 to 5 microns the transformer coupling factor (K) may only be as high as 0.8. Consequently, the planartransformerwill have a relatively high insertion loss and it will also provide a poor input impedance match which accordingly limits the ap- plication ofthetransformer.
Referring now to Figures 3 and 4 of the accompany- ing drawings these show a planartransformerconstructed according to the present invention. It will be seen that primary a nd secondary conducto r tu rns 10 and 11 of generally rectangularspiral configuration are vertically aligned with one another at slightly different levels in the circuit. Unlike the case of Figures 1 and 2 transformer primary and secondary winding connecting strips 12 and 13 are formed on the surface ofthe gallium arsenide substrate 1 by a suitable metallisation process before the first dielectric layer 2 is applied.The rectangular spiral turns ofthe primary winding are then produced by a metallisation process on the dielectric layer2 following which the second dielectric layer 3 is applied. The secondary winding comprising spiral turns 11 arethenformedbya metallisation technique on the surface ofthe outer dielectric layer3 so that the secondary conductor turns 11 are located directly overthe primary conductor turns 10. Atypical spacing between the primary and secondaryconductorturns 10 and 11 will be less than 1 micron (i.e.typical thickness ofthe dielectric
layers 2 and 3).As a consequence the reduced spacing
between the primary and secondary conductorturns contributes to significantly improved magnetic cou pling and thus the coupling factor (K) between the
primary and secondary is nearer two unity. This tighter coupling resultsin lower insertion lossofthe transfor- mer and better matching capabilities. Since the
primary and secondaryconductorturns areatdiffe
rent levels the width oftheturns may be increased to reduce the resistive loss of the transformer.
In an alternative embodiment shown in crosssection in Figure 5the primary and secondary conductorturns 14 and 15 are effectively interwound atdifferentlevels but the reduced spacing between the primary and secondary conductorturns compared with the known construction of Figures 1 and 2 provides a significantly tighter coupling and thus provides a h igher ( K) factor. The relative displacement ofthe primary and secondary may also serve to
reduceparasiticinterspiral capacitance.
Although in the particular embodiments illustrated the conductors of the primary and secondary windings are substantially equal width is should be understood thatconductors of differentwidth could be used without departing from the spirit ofthe invention and may in fact serve to reduce still further theseparation between the turns ofthe primary and secondary and thus improve the coupling factor of the transformer.
In the embodiments shown a back metallisation
layer 16 is also provided.
Claims (6)
1. Aplanartransformercomprising an insulating or semiconductor substrate (e.g. gallium arsenide) in which primary and secondary conductorturns of spiral configuration are formed atslightly different levels within the dielectric layer material applied to the semiconductor substrate.
2. A planartransformeras claimed in claim 1, in which the primary and secondary spiral conductors are located in vertical alignment.
3. A planartransformeras claimed in claim 1, in which the primary and secondary spiral conductors are displaced from each other in the horizontal direction so as effectively to provide interwound primary and secondary turns at different levels in the insulating or dielectric material.
4. A planartransformer as claimed in any preceding claim, in which the spiral conductors are formed by metallisation techniques.
5. Aplanartransformer as claimed in any preceding claim, in which the primary and secondaryturns are ofdifferentwidths in order to reduce the separation between the primary and secondary conductor turns.
6. A planartransformer substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8508332A GB2173956B (en) | 1985-03-29 | 1985-03-29 | Improvements relating to electric transformers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8508332A GB2173956B (en) | 1985-03-29 | 1985-03-29 | Improvements relating to electric transformers |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8508332D0 GB8508332D0 (en) | 1985-05-09 |
| GB2173956A true GB2173956A (en) | 1986-10-22 |
| GB2173956B GB2173956B (en) | 1989-01-05 |
Family
ID=10576931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8508332A Expired GB2173956B (en) | 1985-03-29 | 1985-03-29 | Improvements relating to electric transformers |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2173956B (en) |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987007074A1 (en) * | 1986-05-08 | 1987-11-19 | American Telephone & Telegraph Company | Transformer structure |
| EP0413348A2 (en) * | 1989-08-18 | 1991-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| EP0506362A2 (en) * | 1991-03-25 | 1992-09-30 | Satosen Co., Ltd. | Coil |
| GB2269057A (en) * | 1992-05-27 | 1994-01-26 | Fuji Electric Co Ltd | Thin film transformer |
| EP0713229A1 (en) * | 1994-11-17 | 1996-05-22 | International Business Machines Corporation | Planar transformer and method of manufacture |
| WO2001053748A1 (en) * | 2000-01-24 | 2001-07-26 | Ronald Kevin Fricker | A lighting assembly |
| DE10100282A1 (en) * | 2001-01-04 | 2002-07-18 | Infineon Technologies Ag | Transformer comprises a first coil and a second coil formed in displaced surfaces of a semiconductor device |
| US6927662B2 (en) | 2002-07-18 | 2005-08-09 | Infineon Technologies Ag | Integrated transformer configuration |
| US7302247B2 (en) | 2004-06-03 | 2007-11-27 | Silicon Laboratories Inc. | Spread spectrum isolator |
| US7683654B2 (en) | 2003-04-30 | 2010-03-23 | Analog Devices, Inc. | Signal isolators using micro-transformers |
| US7719305B2 (en) | 2006-07-06 | 2010-05-18 | Analog Devices, Inc. | Signal isolator using micro-transformers |
| US7971340B2 (en) | 2008-06-30 | 2011-07-05 | Alpha & Omega Semiconductor, Ltd | Planar grooved power inductor structure and method |
| US8058960B2 (en) * | 2007-03-27 | 2011-11-15 | Alpha And Omega Semiconductor Incorporated | Chip scale power converter package having an inductor substrate |
| US9293997B2 (en) | 2013-03-14 | 2016-03-22 | Analog Devices Global | Isolated error amplifier for isolated power supplies |
| US9660848B2 (en) | 2014-09-15 | 2017-05-23 | Analog Devices Global | Methods and structures to generate on/off keyed carrier signals for signal isolators |
| US9998301B2 (en) | 2014-11-03 | 2018-06-12 | Analog Devices, Inc. | Signal isolator system with protection for common mode transients |
| US10270630B2 (en) | 2014-09-15 | 2019-04-23 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
| US10290608B2 (en) | 2016-09-13 | 2019-05-14 | Allegro Microsystems, Llc | Signal isolator having bidirectional diagnostic signal exchange |
| US10419251B2 (en) | 2002-09-18 | 2019-09-17 | Infineon Technologies | Digital signal transfer using integrated transformers with electrical isolation |
| US10536309B2 (en) | 2014-09-15 | 2020-01-14 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
| US11115244B2 (en) | 2019-09-17 | 2021-09-07 | Allegro Microsystems, Llc | Signal isolator with three state data transmission |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198951B2 (en) | 2004-06-03 | 2012-06-12 | Silicon Laboratories Inc. | Capacitive isolation circuitry |
| US7737871B2 (en) | 2004-06-03 | 2010-06-15 | Silicon Laboratories Inc. | MCU with integrated voltage isolator to provide a galvanic isolation between input and output |
| US7821428B2 (en) | 2004-06-03 | 2010-10-26 | Silicon Laboratories Inc. | MCU with integrated voltage isolator and integrated galvanically isolated asynchronous serial data link |
| US7902627B2 (en) | 2004-06-03 | 2011-03-08 | Silicon Laboratories Inc. | Capacitive isolation circuitry with improved common mode detector |
| US8049573B2 (en) | 2004-06-03 | 2011-11-01 | Silicon Laboratories Inc. | Bidirectional multiplexed RF isolator |
| US7447492B2 (en) | 2004-06-03 | 2008-11-04 | Silicon Laboratories Inc. | On chip transformer isolator |
| US8169108B2 (en) | 2004-06-03 | 2012-05-01 | Silicon Laboratories Inc. | Capacitive isolator |
| US7738568B2 (en) | 2004-06-03 | 2010-06-15 | Silicon Laboratories Inc. | Multiplexed RF isolator |
| US8441325B2 (en) | 2004-06-03 | 2013-05-14 | Silicon Laboratories Inc. | Isolator with complementary configurable memory |
| US8451032B2 (en) | 2010-12-22 | 2013-05-28 | Silicon Laboratories Inc. | Capacitive isolator with schmitt trigger |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB770166A (en) * | 1951-05-31 | 1957-03-20 | Standard Telephones Cables Ltd | Microwave radio receiver |
| GB845352A (en) * | 1958-03-05 | 1960-08-17 | Standard Telephones Cables Ltd | Dipole-antenna element for connection to coaxial lines |
| GB1116161A (en) * | 1964-10-21 | 1968-06-06 | Sperry Rand Ltd | Improvements relating to electrical coils |
| GB1116117A (en) * | 1966-09-27 | 1968-06-06 | Standard Telephones Cables Ltd | A tuning arrangement |
| GB1180923A (en) * | 1966-02-21 | 1970-02-11 | Plessey Co Ltd | Improvements relating to Electric Coil Assemblies. |
| GB1494087A (en) * | 1975-10-22 | 1977-12-07 | Data Recording Instr Co | Magnetic recording and reproducing transducers and methods of manufacture thereof |
| GB2087656A (en) * | 1980-11-14 | 1982-05-26 | Analog Devices Inc | Miniaturized transformer construction |
-
1985
- 1985-03-29 GB GB8508332A patent/GB2173956B/en not_active Expired
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB770166A (en) * | 1951-05-31 | 1957-03-20 | Standard Telephones Cables Ltd | Microwave radio receiver |
| GB845352A (en) * | 1958-03-05 | 1960-08-17 | Standard Telephones Cables Ltd | Dipole-antenna element for connection to coaxial lines |
| GB1116161A (en) * | 1964-10-21 | 1968-06-06 | Sperry Rand Ltd | Improvements relating to electrical coils |
| GB1180923A (en) * | 1966-02-21 | 1970-02-11 | Plessey Co Ltd | Improvements relating to Electric Coil Assemblies. |
| GB1116117A (en) * | 1966-09-27 | 1968-06-06 | Standard Telephones Cables Ltd | A tuning arrangement |
| GB1494087A (en) * | 1975-10-22 | 1977-12-07 | Data Recording Instr Co | Magnetic recording and reproducing transducers and methods of manufacture thereof |
| GB2087656A (en) * | 1980-11-14 | 1982-05-26 | Analog Devices Inc | Miniaturized transformer construction |
Cited By (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987007074A1 (en) * | 1986-05-08 | 1987-11-19 | American Telephone & Telegraph Company | Transformer structure |
| EP0643403A3 (en) * | 1989-08-18 | 1995-10-25 | Mitsubishi Electric Corp | Inductive structures for semiconductor integrated circuits. |
| EP0413348A2 (en) * | 1989-08-18 | 1991-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| EP0413348A3 (en) * | 1989-08-18 | 1993-03-24 | Mitsubishi Denki Kabushiki Kaisha | Inductive structures for semiconductor integrated circuits |
| EP0643403A2 (en) * | 1989-08-18 | 1995-03-15 | Mitsubishi Denki Kabushiki Kaisha | Inductive structures for semiconductor integrated circuits |
| EP0643404A2 (en) * | 1989-08-18 | 1995-03-15 | Mitsubishi Denki Kabushiki Kaisha | Inductive structures for semiconductor integrated circuits |
| EP0643404A3 (en) * | 1989-08-18 | 1995-11-08 | Mitsubishi Electric Corp | Inductive structures for semiconductor integrated circuits. |
| EP0506362A2 (en) * | 1991-03-25 | 1992-09-30 | Satosen Co., Ltd. | Coil |
| EP0506362A3 (en) * | 1991-03-25 | 1994-05-18 | Satosen Co Ltd | Coil |
| US5402098A (en) * | 1991-03-25 | 1995-03-28 | Satosen Co., Ltd. | Coil |
| GB2269057A (en) * | 1992-05-27 | 1994-01-26 | Fuji Electric Co Ltd | Thin film transformer |
| US5420558A (en) * | 1992-05-27 | 1995-05-30 | Fuji Electric Co., Ltd. | Thin film transformer |
| GB2269057B (en) * | 1992-05-27 | 1996-05-01 | Fuji Electric Co Ltd | Thin film transformer |
| US5572179A (en) * | 1992-05-27 | 1996-11-05 | Fuji Electric Co., Ltd. | Thin film transformer |
| EP0713229A1 (en) * | 1994-11-17 | 1996-05-22 | International Business Machines Corporation | Planar transformer and method of manufacture |
| US5754088A (en) * | 1994-11-17 | 1998-05-19 | International Business Machines Corporation | Planar transformer and method of manufacture |
| WO2001053748A1 (en) * | 2000-01-24 | 2001-07-26 | Ronald Kevin Fricker | A lighting assembly |
| DE10100282A1 (en) * | 2001-01-04 | 2002-07-18 | Infineon Technologies Ag | Transformer comprises a first coil and a second coil formed in displaced surfaces of a semiconductor device |
| DE10100282B4 (en) * | 2001-01-04 | 2005-10-13 | Infineon Technologies Ag | Electric transformer |
| US6927662B2 (en) | 2002-07-18 | 2005-08-09 | Infineon Technologies Ag | Integrated transformer configuration |
| DE10232642B4 (en) * | 2002-07-18 | 2006-11-23 | Infineon Technologies Ag | Integrated transformer arrangement |
| US10419251B2 (en) | 2002-09-18 | 2019-09-17 | Infineon Technologies | Digital signal transfer using integrated transformers with electrical isolation |
| US8736343B2 (en) | 2003-04-30 | 2014-05-27 | Analog Devices, Inc. | Signal isolators using micro-transformers |
| US7683654B2 (en) | 2003-04-30 | 2010-03-23 | Analog Devices, Inc. | Signal isolators using micro-transformers |
| US7692444B2 (en) | 2003-04-30 | 2010-04-06 | Analog Devices, Inc. | Signal isolators using micro-transformers |
| US7920010B2 (en) | 2003-04-30 | 2011-04-05 | Analog Devices, Inc. | Signal isolators using micro-transformers |
| US7302247B2 (en) | 2004-06-03 | 2007-11-27 | Silicon Laboratories Inc. | Spread spectrum isolator |
| US7719305B2 (en) | 2006-07-06 | 2010-05-18 | Analog Devices, Inc. | Signal isolator using micro-transformers |
| US8058960B2 (en) * | 2007-03-27 | 2011-11-15 | Alpha And Omega Semiconductor Incorporated | Chip scale power converter package having an inductor substrate |
| US7971340B2 (en) | 2008-06-30 | 2011-07-05 | Alpha & Omega Semiconductor, Ltd | Planar grooved power inductor structure and method |
| US9293997B2 (en) | 2013-03-14 | 2016-03-22 | Analog Devices Global | Isolated error amplifier for isolated power supplies |
| US9660848B2 (en) | 2014-09-15 | 2017-05-23 | Analog Devices Global | Methods and structures to generate on/off keyed carrier signals for signal isolators |
| US10270630B2 (en) | 2014-09-15 | 2019-04-23 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
| US10536309B2 (en) | 2014-09-15 | 2020-01-14 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
| US9998301B2 (en) | 2014-11-03 | 2018-06-12 | Analog Devices, Inc. | Signal isolator system with protection for common mode transients |
| US10290608B2 (en) | 2016-09-13 | 2019-05-14 | Allegro Microsystems, Llc | Signal isolator having bidirectional diagnostic signal exchange |
| US10651147B2 (en) | 2016-09-13 | 2020-05-12 | Allegro Microsystems, Llc | Signal isolator having bidirectional communication between die |
| US11115244B2 (en) | 2019-09-17 | 2021-09-07 | Allegro Microsystems, Llc | Signal isolator with three state data transmission |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8508332D0 (en) | 1985-05-09 |
| GB2173956B (en) | 1989-01-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |