GB2168857A - Method and structure for interconnecting high frequency components - Google Patents

Method and structure for interconnecting high frequency components Download PDF

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Publication number
GB2168857A
GB2168857A GB08527977A GB8527977A GB2168857A GB 2168857 A GB2168857 A GB 2168857A GB 08527977 A GB08527977 A GB 08527977A GB 8527977 A GB8527977 A GB 8527977A GB 2168857 A GB2168857 A GB 2168857A
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Prior art keywords
layer
conductor
conductive
shield
conductive strips
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GB08527977A
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GB8527977D0 (en
Inventor
Richard Charles Landis
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International Standard Electric Corp
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International Standard Electric Corp
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Priority claimed from US06/671,276 external-priority patent/US4673904A/en
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of GB8527977D0 publication Critical patent/GB8527977D0/en
Publication of GB2168857A publication Critical patent/GB2168857A/en
Withdrawn legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A support board or substrate (20) is disclosed for interconnecting various electronic components (56, 58). One or more conductors (26) are embedded within the substrate for interconnecting the components. Each conductor is provided with shielding (40) to permit the exchange of high frequency signals between the components without cross-coupled interference. A structure is also disclosed for mounting and connecting an integrated circuit to a circuit board. The board has a plurality of embedded shielded conductors for interconnecting the integrated circuit to other devices on the board. In order to limit the capacitance and inductance of the connection, the integrated circuit is mass bonded directly, to the conductors and to their coaxial shields. The substrate or circuit board is composed of a plurality of planar layers each having conductive portions and dielectric areas, the conductive portions of successive layers being arranged to form an elongate conductor (26) within and spaced from an elongate coaxial shield (40). <IMAGE>

Description

SPECIFICATION Method and structure for interconnecting high frequency components This invention relates to a method and structure for interconnecting high frequency components and integrated circuits and more particularly to a method of forming a micro-coaxial substrate and connecting components and integrated circuits to a substrate.
Typically miniaturised electronic circuits comprise several components such as transistors, resistors, capacitors, as well as various integrated circuits (I.C.'s) which are mounted on a board. Interconnection between the different components is accomplished by providing a preselected strip pattern on the board by photomasking or other methods. However it is well-known that at high frequencies (i.e. in the Megahertz or Gigahertz range), the inductive and capacitance losses in these wires are prohibitive and furthermore the cross-coupling therebetween cause unacceptable distortions in the signals.
Heretofore, it has been proposed that the components be interconnected by conductors imbedded in the board disposed between two parallel ground planes. However it is found that even with this configuration, cross-coupling between adjacent conductors occurs unless the conductors are spaced far apart. This spacing in turn required a proportionate increase in the size of the boards.
Another proposed solution was to use optical fibres as the transmission means between integrated circuits. However this approach has two major disadvantages: first the electrical signals must be converted into optical signals, and then back to electrical signals, thus requiring additional components. Second, optical fibres must be aligned very carefully with the optical signal transmitters or receivers to ensure maximum signal transfer therebetween.
The present invention seeks to provide a means for interconnecting high frequency electronic components which has a minimum size.
The invention also seeks to provide an interconnecting means, and a method of producing such interconnecting means, in which capacitive, and inductive losses are minimised and cross-coupling is eliminated.
According to one aspect of the invention there is provided a method of forming a substrate for supporting electronic components and having a conductor formed therein, comprising the steps of providing a conductive strip in a first layer, forming a first pair of spaced conductive strips, and, in a second layer overlaying the first layer, each of the pair of conductive strips being in electrical contact with the conductive strip in the first layer and coextensive therewith, the pair of conductive strips defining a channel therebetween, providing dielectric material in the second layer filling the channel, forming three spaced conductive strips in a third layer overlying the second layer and coextensive therewith, two outermost of the three conductive strips each being in electrical contact with a different one of the first pair of conductive strips, providing dielectric material between the conductive strips in the third layer, forming a second pair of spaced conductive strips, in a fourth layer overlaying the third layer, each of the second pair of conductive strips each being in electrical contact with a different one of the outermost conductive strips in the third layer and coextensive therewith, providing dielectric material between the conductive strips in the fourth layer, and forming a conductive strip in a fifth layer overlaying the fourth layer, the conductive strip being in electric contact with the second pair of conductive strips and coextensive therewith, the conductive strips being arranged to form an elongate coaxial conductor in which the centre conductive strip of the third layer provides a conductor, the conductive strips in the first and fifth layers, the first and second pairs of conductive strips and the outermost conductive strips in the third layer form a shield for the conductor whilst the conductive strips and dielectric material form a substrate.
According to a second aspect of the invention there is provided a substrate for supporting electronic components and having a conductor embedded therein, comprising a first planar layer forming a base, an elongate conductive strip disposed in a second layer on the base, dielectric material disposed in the second layer over portions of the base not covered by the first elongate conductive strip, a pair of spaced elongate conductive strips disposed in a third layer and defining a channel therebetween, each of the pair of conductive strips being in electrical contact with the first elongate conductive strip and coextensive therewith, dielectric material disposed in the third layer filling the channel and portions of the third layer overlying the dielectric material of the second layer, at least three spaced and elongate conductive strips disposed in a fourth layer and being coextensive with the pair of conductive strips, the outermost of the conductive strips being in electrical contact with the first pair of conductive strips, the third conductive strip being disposed between the outermost conductive strips and forming the conductor of the substrate, dielectric material disposed in the fourth layer between the elongate conductive strips and over the dielectric material of the second and third layer, a pair of spaced elongate conductive strips disposed in a fifth layer, each of the pair of conductive strips being in electrical contact with the outermost two of the conductive strips of the fourth layer and coextensive therewith, dielectric material disposed in the fifth layer between the pair of conductive strips and over the dielectric material of the fourth layer, an elongate conductive strip disposed in a sixth layer overlying and coextensive with the other conductive strip and in electrical contact with the second pair of conductive strips, and dielectric material disposed in the sixth layer in portions of the layer not occupied by the second elongate conductive strips, whereby the conductive strips of the second and sixth layers, the first and second pair of conductive strips and the outermost conductive strips in the fourth layer form a shield disposed about and coaxial with the conductor formed by the centre conductive strip in the fourth layer, the shield being in contact with the planar base layer.
The present invention may enable the connection of ICto a coaxial conductor embedded in a substrate in which the length of the connecting unshielded conductor is minimised to reduce its high frequency impedance.
All the connections to the IC may be made simultaneously and may enable high speed automation.
Figure 1 is a cross-sectional view of a prior art board having imbedded conductors interposed between two parallel ground planes, Figure 2 is an isometric cross-sectional view of a board having shielded conductors constructed in accordance with the invention, Figure 3 is a cross-sectional view of a typical conductor and its shield constructed in accordance with the invention, Figures 4 to 8 show how successive substrates are layered to form the board of Figure 2, Figure 9 is an enlarged sectional view of a shielded conductor imbedded in a board substrate, Figure 10 shows a board having a plurality of parallel conductors, each of which is individually shielded, Figure 11 illustrates wire bonding to an integrated circuit in a manner known to us, Figure 12 illustrates a high frequency connection using optical fibres by a technique known to us, Figure 13a is a plan view of an connection between a shielded conductor and an integrated circuit, Figure 13b is an end view of the shielded conductor of Figure 13a, Figures 14 and 15 show enlarged views of a shielded conductor connection to an integrated circuit, Figure 16 shows a circuit board prepared for an embedded integrated circuit, Figure 17 is a cross-sectional view of the circuit board prepared in accordance with Figure 16, Figure 18 is a plan view of the board of Figure 17, Figure 19 shows a bumped chip positioned for compression bonding to embedded conductors in the board of Figure 18, Figure 20 shows a completed IC chip after thermal compression bonding to conductors embedded in the circuit board, and Figure 21 shows an alternate embodiment of the invention.
As shown in Figure 1 a prior art board 10 comprised two parallel metallic sheets 12 and 14 which established two ground planes with a dielectric material 16 extending therebetween. A plurality of conductors, such as 18 are disposed between the two sheets as shown. As previously mentioned, at high frequencies capacitive-coupling between adjacent conductors causes signal interference. Thus a trade-off must be made between the maximum operation frequency of the board and the spacing between the conductors. This problem is obviated by the present invention, which, as shown in Figure 2, provides an individual shield for each conductor.
The board 20 of Figures 2 and 3 comprises a metallic base 22, of for example copper, and a layer of dielectric material 24. Imbedded in the dielectric layer 24 are a plurality of conductors 26, 28, 30, 32, 34, 36 and 38. Depending on the required degree of isolation, some of the conductors such as 26 and 28 are completely shielded by tubular shields 40 and 42 respectively, having a rectangular crosssection. These shields are formed on the copper base 22 so that they are electrically connected to the ground plane. The remaining conductors are partially shielded by U-shaped shield 44, or merely decoupied by the I-shaped isolating walls 46, 48.
For terminating purposes, the two extreme portions of each conductor comprise a vertical section 50 which ends in a square pad 52 flush with the top surface 54 of the board as shown in Figure 3.
Obviously connecting pads similar to pad 52 may be provided at intermediate locations as necessary.
Thus the conductors may be readily used for interconnecting two or more devices. For example, two high frequency devices, such as GaAs l.C.'s 56, 58, may be affixed to top surface 54 of board 20 as shown in Figure 3 so that shielded conductor 26 extends therebetween. These devices are provided with pads 60, 62 respectively. Device pads 60, 62 may be then connected to pads 52 by any wellknown means in the art. In Figure 3 for example, wires 64 and 66 are bonded to the respective pads as shown using the technique commonly known as wire bonding.
A method of producing a board with a shielded conductor is illustrated in Figures 4 to 8. First a relatively wide metallic strip 68 is deposited on a copper base 67. As will become apparent later, this first strip will become the bottom wall of the shield. An appropriate material 70 with low dielectric constant such as polyimide is applied to the base to form a smooth, continuous surface with metallic strip 68. Strip 68 is deposited either directly on base 67, or, as shown in Figures 4 to 8, an insulating layer 69 may be disposed between the base 67 and layer 68 as shown. Next, (Figure 5) two relatively narrow strips 72, 74 are deposited on strip 68, each strip having an outer edge 76 which is continuous with a corresponding outer edge of strip 68. A shallow channel 78 is thus defined by the strips 68, 72 and 74 as shown. The dielectric is then built up to be even with the top surfaces of strips 72 and 74. Channel 78 is also filled up with dielectric.
Next, (Figure 6) three metallic strips are deposited on the assembly of Figure 5, with two of the strips 80, 82 being disposed in a substantially overlapping position, on top of strips 72, 74 respectively and a third strip 84 being deposited above the channel 78 and evenly spaced from strips 80 and 82. Dielectric is again built up across the width of the assembly and in between strips 80, 84 and 84, 82 respectively.
The steps of Figure 5 are then repeated as shown in Figure 7 with two additional strips 86, 88 being deposited over strips 80, 82 as shown. The dielectric applied in this step effective buries the central strip 84 with the shield.
Finally a last, relatively wide metallic strip 90 (Figure 8) is deposited on top of strips 86, 88 thereby completing the shield around central strip 84 which then may act as a conductor, for high fre quency signals. For the sake of simplicity the verti cal leg 50 and connecting tab 52 have been omitted from these Figures. However obviously they are made by appropriate masking techniques prevalent in the art.
While in Figures 4 to 8 the formation of a rectan gular shield is illustrated, it is clear that the same principles may be used to build shields having other cross-sections such as square, circular, trian gular, etc. For example a simulated circular shield may be made of a plurality of layers staggered in the horizontal direction. Furthermore, while a typi cal rectangular shield with at least five layers are necessary (or four if base forms the bottom wall of the shield), it is obvious that more layers may be used as required by the desired configuration. The technique described above may also be used to make partial shields such as the I-shaped shields 46, 48 or U-shaped shield 44.
In Figures 4 to 8, the successive layers are shown as being perfectly deposited and aligned with the adjacent layers. It is well known that in practice such an alignment is virtually impossible.
In Figure 9, the cross-section of an actual shielded conductor made in accordance with the above de scribed method is shown. It can be seen from this Figure that slight misalignment errors between successive layer cause the side walls to waiver slightly, however the integrity of the shield is maintained. The cavity within the shield illustrated in Figure 9 measures 20 x 20 mils; however, a smaller size cavity may be used.
If necessary, a plurality of conductors may be in dividually shielded as shown in Figure 10. In this Figure a continuous top 90 and bottom 92 shield ing surfaces are formed and the space therebe tween is partitioned by side walls 94 extending perpendicularly between these surfaces. Conductors 96 are disposed between walls 94 so that each conductor 96 is individually shielded.
Typically, integrated circuits are interconnected by wire bonding as shown in Figure 3 at 64 and 66 using a printed metal strip as opposed to the coax ial connection of the present invention. As shown in Figure 11, wire bonding involves forming a ball of molten metal 12' on the end of a wire 14' and then applying the ball and wire to a bonding pad 16'. The pad is usually an aluminium metalised area on the surface of an integrated circuit board.
However, as previously mentioned, at high fre quencies this type of interconnecting is undesirable because of its high inductance and capacitance as well as cross-coupling.
An alternate method, illustrated in Figure 12, comprises the use of an optical fibre 18'. Signals are passed to or from the fibre through an appro priate opto-electronic device 20' which may be a phototransistor (for receiving signals) or an LED or laser diode (for transmitting). However this interconnection requires a precise alignment. More particularly end 22' of fibre 18' must be positioned and oriented in a preselected spacial relationship with respect to device 20' by turning adjusting screws 24' and 26' or other mechanical means for alignment. These adjustments require great dexterity on the part of the personnel making the installation. Furthermore, very slight angular misalignments are deleterious to signal strength and the whole progress is expensive and time consuming. Obviously this interconnection method is not suitable for automation.For the reasons outlined above it would be very advantageous to have a miniaturised shielded conductor arranged and constructed so that, as shown in Figures 13a and 13b, the conductor 30' could be electrically connected to one of the pads 32' of an l.C. 34' while its shield 36' could be connected to another pad 38', of the l.C., which may comprise, for example, the ground terminal of the l.C.
As shown in more detail in Figure 14, the shield 36' is perfectly coaxial around conductor 30'. A dielectric material 40' is provided within the shield to support the insulate conductor 30'. This type of connection is advantageous over the prior art connections in that the actual conductor can be made relatively short and the shield reduces its parasitic capacitance, and cross-coupling.
Furthermore, as shown in Figure 15, a shielded conductor 41' may be provided with a pair of terminals 42' and 44' and may have several other branches such as 46' and 48' electrically connected to the conductor and designed in different shapes as required for intermediate connections to other devices.
If the shielded conductors such as the ones shown in Figures 14 and 15 are to be made very thin they may not be self supporting and could be rather difficult to handle. However these problems can be obviated when these shielded conductors are embedded in the substrate of the circuit board, used to support the different electronic devices as described in connection with Figures 2 to 10. Portions of the layers formed.comprise conductive strips which are arranged and constructed so that a preselected pattern of shielded conductors is formed in the board. This configuration is particularly suitable for interconnecting electronic devices by using shielded coaxial conductors. Furthermore the configuration may also be used for automatic installation of integrated circuits on'circuit boards as shall be described below.
An advantageous refinement of the invention is the thermal-compression bonding of one or more chips directly to conductors embedded in the circuit substrate.
Referring now to Figures 16 to 18, the printed circuit substrate conductors and shields are fabricated according to the method described in connection with Figures 2 to 10. A cavity 50' is created in substrate 100' to expose a portion of conductor 60' to form a connecting pad 118' and to expose tab 112' connected to corresponding shield 120'.
The conductor 60' is supported by and completely isolated from the shield 120' by a dielectric material 102'. The dielectric material has been completely removed from the cavity area 50'. Figure 17 shows the resulting cross-sectional view of the cavity 50' and exposed connecting pad 118' suspended by dielectric 102'.
The bonding is accomplished in an automated manner similar to a method commonly referred to as tape automated bonding (TAB). A full description of this method for bonding unshielded conductors on the surface of a flexible tape may be found in the October 20, 1974 issue of EDN in the -article entitled "Tape-Carrier Packaging Boasts Almost Unlimited Potential", by Walt Palstone. In the present invention the single layer TAB tape has been replaced by a multi-layer substrate having buried conductors completely shielded and designed as previously described. The semiconductor IC is then TAB bonded to the internal buried conductors.
In Figure 19, a semiconductor chip 52' having a plurality of connecting bumps 54' plated onto the IC bonding pad sites is supported on a lower bond tool 56'. The bond tool 56' is accurately aligned such that the connecting bumps fall directly under the connecting pads 118' and shield tabs 112' (not shown). An upper bond tool 58' then comes down into cavity 50' to apply heat and pressure to a plurality of connecting pads 118' and shield tabs 112' each aligned with an associated connecting bump 54' on IC 52'. The heat and pressure thus applied effects a mass bonding of all conductors and shields at the same time. Such a simultaneous mass bonding is highly suited for automatic assembly.
In Figure 20, the resulting TAB bonded IC 52' is shown completely attached to the buried and shielded conductor 60'. IC 52' itself may likewise be embedded in the multi-layer substrate. Of course the thickness of the IC could vary so that it may extend beyond the surface of the substrate as illustrated.
Afurther embodiment is shown in Figure 21. In this embodiment substrate 70' is formed with one or more shielded conductors 72'. Insulated pads 74' are formed on the surface of the substrate and connected to conductors 72' by vertical portions 76' as shown. The top or outer surface of pads 74' is substantially coplanar or flush with the outer surface of the substrate.
An integrated circuit or chip 78' for mounting on the substrate is provided with connected bumps 80' plated on the circuit connecting pads. The chip is then connected to the substrate by compression bonding as described above. As shown in Figure 21, some of the bumps 80' are bonded to conductor 74' while other bumps are bonded directly to the conductor shields.

Claims (39)

1. A method of forming a substrate for supporting electronic components and having a conductor formed therein, comprising the steps of providing a a conductive strip in a first layer, forming a first pair of spaced conductive strips, and, in a second layer overlaying the first layer, each of the pair of conductive strips being in electrical contact with the conductive strip in the first layer and coextensive therewith, the pair of conductive strips defining a channel therebetween, providing- dielectric material in the second layer filling the channel, forming three spaced conductive strips in a third layer overlying the second layer and coextensive therewith, two outermost of the three conductive strips each being in electrical contact with a different one of the first pair of conductive strips, providing dielectric material between the conductive strips in the third layer, forming a second pair of spaced conductive strips, in a fourth layer overlaying the third layer, each of the second pair of conductive strips each being in electrical contact witha different one of the outermost conductive strips in the third layer and coextensive therewith, providing dielectric material between the conductive strips in the fourth layer, and forming a conductive strip in a fifth layer overlaying the fourth layer, the conductive strip being in electric contact with the second pair of conductive strips and coextensive therewith, the conductive strips being arranged to form an elongate coaxial conductor in which the centre conductive strip of the third layer provides a conductor, the conductive strips in the first and fifth layers, the first and second pairs of conductive strips and the outermost conductive strips in the third layer form a shield for the conductor whilst the conductive strips and dielectric material form a substrate.
2. A method as claimed in claim 1, including the steps of, forming in the fourth layer conductive portions overlaying portions of the centre conductive strip of the third layer and in electrical contact therewith, forming the conductive strip of the fifth layer with openings disposed over the conductive portions formed in the fourth layer, forming within the opening- in the fifth layer conductive portions overlaying and in electrical contact with the conductive portions of the fourth layer and spaced from the conductive strip of the fifth layer, and providing dielectric material in the spaces between the conductive portions and the conductive strip in the fifth layer, whereby the conductive portions in the fourth and fifth layers provide contact means to the coaxial conductor.
3. A method of forming a conductor embedded in a planar substrate, comprising the steps of, providing a planar layer having a first elongate conductive portion, forming a plurality of successive planar layers disposed over the planar layer, each layer of the plurality having conductive portions, and forming another planar layer having a second elongate conductive portion disposed over the plurality of successive planar layers, the first and second elongate conductive portions and the conductive portions of the plurality of successive planar layers being formed and arranged into an elongate coaxial shield and a conductor formed within and spaced from the shield.
4. A method as claimed in claim 3, wherein the conductive portions of the successive planar layers include elongate conductive portions coextensive with the elongate conductive portion of the first layer and in electrical contact therewith to form the shield and an elongate conductive portion forming the conductor.
5. A method as claimed in claim 3, wherein additional conductive portions of the plurality of successive planar layers are formed to provide ends for the shield of the coaxial conductor.
6. A method as claimed in any one of claims 3 to 5, wherein additional conductive portions are formed in the plurality of planar layers and are arranged to provide means for contacting the conductor of the coaxial conductor.
7. A method as claimed in any one of claims 3 to 6, in which dielectric material is provided between the conductor and the shield of the coaxial conductor.
8. A method of forming a substrate substantially as described herein with reference to the drawings.
9. A substrate for supporting electronic components and having a conductor embedded therein, comprising a first planar layer forming a base, an elongate conductive strip disposed in a second layer on the base, dielectric material dipsosed in the second layer over portions of the base not covered by the first elongate conductive strip, a pair of spaced elongate conductive strips disposed in a third layer and defining a channel therebetween, each of the pair of conductive strips being in electrical contact with the first elongate conductive strip and coextensive therewith, dielectric material disposed in the third layer filling the channel and portions of the third layer overlying the dielectric material of the second layer, at least three spaced and elongate conductive strips disposed in a fourth layer and being coextensive with the pair of conductive strips, the outermost of the conductive strips being in electrical contact with the first pair of conductive strips, the third conductive strip being disposed between the outermost conductive strips and forming the conductor of the substrate, dielectric material disposed in the fourth layer between the elongate conductive strips and over the dielectric material of the second and third layer, a pair of spaced elongate conductive strips disposed in a fifth layer, each of the pair of conductive strips being in electrical contact with the outermost two of the conductive strips of the fourth layer and coextensive therewith, dielectric material disposed in the fifth layer between the pair of conductive strips and over the dielectric material of the fourth layer, an elongate conductive strip disposed in a sixth layer overlying and coextensive with the other conductive strips and in electrical contact with the second pair of conductive strips, and dielectric material disposed in the sixth layer in portions of the layer not occupied by the second elongate conductive strip, whereby the conductive strips of the second and sixth layers, the first and second pair of conductive strips and the outermost conductive strips in the fourth layer form a shield disposed about and coaxisl with the conductor formed by the centre conductive strip in the fourth layer, the shield being in contact with the planar base layer.
10. A substrate as claimed in claim 9, wherein the base layer is formed of a conductive material and the shield is in electrical contact therewith.
11. A substrate for supporting electronic components substantially as described herein, with reference to the drawings.
12. A method of securing a device having a plurality of connecting means to a circuit board, the board comprising a plurality of embedded shielded conductors, for interconnecting the device with other elements, comprising positioning the device adjacent a preselected location on the board, the location being defined by conductor terminations corresponding to the device connecting means, and forcing the device against the board to form compression bonding between the device connecting means and the terminations.
13. A method as claimed in claim 12, wherein the conductor terminations comprise pads disposed on the surface of the board.
14. A method as claimed in claim 12 or 13, wherein the device is an integrated chip having a plurality of connecting bumps.
15. A method as claimed in claim 12, 13 or 14, wherein the conductors are connected to other elements disposed on the board.
16. A method as claimed in any one of claims 12 to 15, wherein the board is provided with shield terminations connected to the respective shields of the shielded conductors.
17. A method as claimed in claim 16, wherein the shield terminations are positioned to contact some of the connecting means as the device is forced against the board.
18. A method of securing a device having a plurality of connecting means to a circuit board for interconnection with other devices, comprising providing a circuit board with a plurality of embedded shielded conductors and a cavity with conductor terminations, positioning the device adjacent to the cavity with the device connecting means being aligned with the conductor terminators, and moving the device to make contact with the conductor terminators.
19. A method as claimed in claim 18, wherein the cavity is formed with shield terminations for connection to corresponding connecting means.
20. A method as claimed in claim 19, wherein the connecting means are connected to the connector and shield terminations by compression bonding.
21. A method as claimed in claim 19 or 20, wherein the cavity extends through the board and the device is moved from one side of the board into the cavity until the connecting means contact the terminations.
22. A method as claimed in claim 21, comprising the step of introducing bonding means into the cavity from another side of the board to bond the terminations and the connecting means.
23. A method as claimed in claim 22, comprising applying pressure to the terminating and the connecting means for compression bonding.
24. A method as claimed in claim 23, comprising applying heat to the terminating and connecting means.
25. A method as claimed in any one of claims 19 to 24, wherein the terminations are formed by extending the respective conductors and shields into the cavity.
26. A method as claimed in claim 25, wherein the terminations are colinear with the respective conductors and shields.
27. A method of securing a device having a plurality of connecting means to a circuit board for connection with other devices which method is substantially as described herein with reference to the drawings.
28. A method of connecting a device having a plurality of connecting means to a conductor shielded by a conductor shield comprising provid ing a conductor termination for the conductor, providing a shield terminator for the conductor shield, the conductor and shield terminators being ar ranged and spaced to correspond to the respective connecting means, and bonding the conductors and shield terminators to the respective connecting means.
29. A method as claimed in claim 28, wherein the terminators and connecting means are bonded by compression bonding.
30. A method of connecting a device having a plurality of connecting means to a conductor shielded by a conductor shield which method is substantially as described herein with reference to the drawings.
31. A conductor comprising a conducting ele ment, a conductor terminator connected to the conducting element, a shield surrounding the con ductive element, and a shield terminator connect ing to the shield, the conductor and shield terminators being spaced at a preselected distance.
32. A conductor as claimed in claim 31, com prising a dielectric material disposed between the conductor and the shield.
33. A conductor as claimed in claim 32, wherein the conductor terminator comprises a linear extension of the conducting element
34. A conductor as claimed in claim 33, wherein the shield terminator is disposed in parallel to the conductor terminator.
35. A conductor substantially as described herein with reference to the drawings.
36. A substrate, comprising a dielectric layer, a conductor embedded in the layer, and a coaxial shield substantially coextensive with and surrounding the conductor, the substrate being formed with a a cavity for housing a device with connecting means, and the conductor and shield being provided with terminating means disposed within the cavity for interconnections with the device connecting means.
37. A substrate as claimed in claim 36, wherein the terminating means comprise pads for compression bonding to the device.
38. A substrate as claimed in claim 37, wherein the pads are axially aligned with the conductor and shield respectively.
39. A substrate substantially as described herein with reference to the drawings.
GB08527977A 1984-11-14 1985-11-13 Method and structure for interconnecting high frequency components Withdrawn GB2168857A (en)

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US67134784A 1984-11-14 1984-11-14
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GB2277832A (en) * 1993-04-27 1994-11-09 British Aerospace Thin film multi-layer interconnect
EP0903780A2 (en) * 1997-09-19 1999-03-24 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits
EP0940849A1 (en) * 1998-03-05 1999-09-08 Interuniversitair Micro-Elektronica Centrum Vzw A low-loss conductive pattern on a substrate and a method for fabrication thereof
EP1145317A1 (en) * 1998-12-28 2001-10-17 Telephus, Inc. Coaxial type signal line and manufacturing method thereof

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GB2277832A (en) * 1993-04-27 1994-11-09 British Aerospace Thin film multi-layer interconnect
EP0903780A2 (en) * 1997-09-19 1999-03-24 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits
EP0903780A3 (en) * 1997-09-19 1999-08-25 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits
EP0940849A1 (en) * 1998-03-05 1999-09-08 Interuniversitair Micro-Elektronica Centrum Vzw A low-loss conductive pattern on a substrate and a method for fabrication thereof
EP1145317A1 (en) * 1998-12-28 2001-10-17 Telephus, Inc. Coaxial type signal line and manufacturing method thereof
EP1145317A4 (en) * 1998-12-28 2006-07-26 Telephus Inc Coaxial type signal line and manufacturing method thereof

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FR2573272A1 (en) 1986-05-16
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