GB2277832A - Thin film multi-layer interconnect - Google Patents
Thin film multi-layer interconnect Download PDFInfo
- Publication number
- GB2277832A GB2277832A GB9308677A GB9308677A GB2277832A GB 2277832 A GB2277832 A GB 2277832A GB 9308677 A GB9308677 A GB 9308677A GB 9308677 A GB9308677 A GB 9308677A GB 2277832 A GB2277832 A GB 2277832A
- Authority
- GB
- United Kingdom
- Prior art keywords
- electrically conductive
- interconnect
- layer
- channels
- conductive member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
- H05K1/0221—Coaxially shielded signal lines comprising a continuous shielding layer partially or wholly surrounding the signal lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0039—Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09981—Metallised walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/467—Adding a circuit layer by thin film methods
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A thin film multi-layer interconnect (7) is made by forming around an elongated electrically conductive member (11) which extends in an interconnect made up of a plurality of layers of insulating material (9, 10 and 12), an electrically conductive shield which encases at least substantially along its length the member (11) and surrounding insulating material (10 and 12). The shield is preferably made up by forming channels on either side of the member 11 and depositing an electrically conductive material layer (14) on the side walls, top and base of the channels into contact with an underlying electrically conductive shielding member (8). <IMAGE>
Description
THIN FILM MULTI-LAYER INTERCONNECT
This invention relates to a process for manufacturing a thin film, multi-layer interconnect and to such an interconnect.
Thin film interconnects are used in a wide variety of electrical, electronic, radio frequency and microwave technologies. Conventional tri-level plate structure interconnects, such as shown in Figure 1 of the accompanying drawings, may take the form of multi laminar structures made up of metal clad dielectric layers. In such a conventional structure metallic conductors are usually shielded by being placed between two parallel layers of electrically conductive material. This conventional construction gives rise to a risk of electro-magnetic interference and relatively poor signal to noise ratio due to the lack of full shielding for the conductors. Additionally it is difficult to pack a plurality of conductors close together in such a construction without giving rise to even more risk of electro-magnetic interference and a poorer signal to noise ratio.
There is thus a need for a process for manufacturing a thin film multi-layer interconnect and to the interconnect itself which at least minimises the aforegoing difficulties and reduces the risk of electro-magnetic interference whilst improving the signal to noise ratio.
According to a first aspect of the present invention there is provided a process for manufacturing a thin film multi-layer interconnect, including the steps of applying at least one elongated strip-like first electrically conductive shielding member to an electrically insulating base layer, applying at least one first electrically insulating layer to the base layer and first shielding member, applying at least one elongated electrically conductive member to said first insulating layer to extend at a spacing from said first shielding member, applying at least a second electrically insulating layer to said electrically conductive member and first insulating layer, forming at least two channels through said second and first insulating layers, one on each side of the electrically conductive member, to a depth sufficient to expose part of said first shielding member and applying an electrically conductive shielding coating to the channelled region of the interconnect to cover the side walls of said channels, the bases of said channels into contact with the exposed parts of the first shielding member and over the surface of said second insulating layer extending between the two channels, thereby to encase with said first shielding member and shielding coating, said at least one electrically conductive member and surrounding electrically insulating layer material along substantially the length of the electrically conductive member.
Preferably the base layer and first and second insulating layers utilised are made of a low loss dielectric material.
Conveniently the shielding member, electrically conductive member and shielding coating utilised are made of metallic material.
Advantageous the metallic material utilised is copper.
Preferably outlines of said channels are defined photolithographically or by laser ablation and the insulating layer material is removed from within said outlines to provide said channels by wet chemical etching or by plasma processing.
Conveniently said shielding coating is of metallic material which is applied by physical vapour deposition, chemical vapour deposition or electro chemically.
According to a second aspect of the present invention there is provided a thin film, multi-layer interconnect, having at least one elongated electrically conductive member embedded in electrically insulating material, with said insulating material and conductive member being encased at least substantially along its length, by an electrically conductive shield at least partially embedded in electrically insulating material.
Conveniently the electrically conductive member and shield are made of metallic material, preferably copper.
Advantageously the insulating material is a polyimide or a polytetrafluoroethylene and glass composite.
For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings in which:
Figure 1 is a diagrammatic cross sectional view through a conventional thin film interconnect of tri-level plate structure format not according to the present invention,
Figure 2 is a cross sectional view similar to that of
Figure 1 through part of an interconnect according to the present invention showing a stage in the manufacture thereof,
Figure 3 is a cross sectional view of the interconnect of Figure 2 at a further stage in the construction thereof in which channels have been formed, and
Figure 4 is a cross sectional view through the interconnect of Figures 2 and 3 showing it in final form according to the present invention.
A conventional thin film multi-layer interconnect as shown in Figure 1 of the accompanying drawings utilises a series of electrically insulating layers 1, 2 3 and 4 located one on top of each other, with the layer 1 being a base layer and with the layr 2 being optional. One or more electrically conductive members 5 extend through the interconnect in the insulating layers 3 and 4 and are laterally spaced from one another. A degree of screening is provided by means of screening strips 6 made of electrically conductive material and located one above and one below each member 5 at a spacing therefrom which spacing is filled by the intervening electrically insulating layers 3 and 4. In this way a degree of screening is provided for the conductors 5 to reduce electro magnetic interference but of course as can be seen from Figure 1, this screening is only partial.
Thus, as can be seen from Figure 1, there is no screening provided laterally of each conductor 5 and there can thus be interference laterally of each conductor 5 and particularly between each conductor 5 laterally. However such a conventional interconnect is relatively simple to construct by a multi-layer deposition technique.
Nevertheless because of the risk of interference between the two or more electrically conductive members 5 it is advisable to space them apart laterally as much as is feasible. This considerably increases the size of interconnect needed or reduces the number of electrically conductive members 5 which can be employed within a given width of interconnect.
Figures 2, 3 and 4 of the accompanying drawings show successive stages in a process for manufacturing a thin film, multi-layer, interconnect 7 according to the present invention. Taking Figure 2 first, the process includes applying at least one elongated strip like first electrically conductive shielding member 8 to an electrically insulating base layer 9. At least one first electrically insulating layer 10 is applied to the base layer and shielding member 8. This layer 10' can be a single layer or made up of any number of part layers as required such as the illustrated two layers 10. At least one elongated electrically conductive member 11, in this case two such members 11, is applied to the first insulating layer 10 to extend at a spacing from the shielding member 8.
A second electrically insulating layer 12, which once again may be made up of any desired number of sublayers, is applied to the or each conductive member 11 and first insulating layer 10 to form the first stage interconnect of Figure 2.
The next stage is as shown in Figure 3 in which at least two channels 13 are formed through the insulating layers 10 and 12, one n each side of the conductive member 11. In the illustrated example, as there are two members 11 there are three such channels 13 provided. The channels 13 are formed through the insulating layers 10 and 12 to a depth sufficient to expose part of the shielding member 8 as can be seen in Figure 3.
An electrically conducting shielding coating 14 is then applied to the channels region at the interconnect 7 to cover the side walls 13a of the or each channel 13, the bases 13b of the or each channel 13 into contact with the exposed parts 8a of the shielding member 8 and over the surface of the second insulating layer 12 extending between the two channels. In this way the shielding coating 14 co-operates with the shielding member 8 to encase the or each conductive member 11 and surrounding insulating layer material 12 and 10 along substantially the length of the electrically conductive member. This construction according to the process of the present invention, as best illustrated in Figure 4 of the accompanying drawings, results in all sides of the electrically conductive member or members 11 being shielded rather than only the top and bottom planes as in the conventional construction of Figure 1. This results in a higher degree of shielding and allows a higher packing density of electrically conductive members 11 to be employed on an interconnect without any risk of cross talk interference between laterally adjacent members 11.
Additionally the interconnect 7 so produced is relatively thin in profile and thus remains pliable and amenable to conformal surface mounting or embedding requirements.
In the construction of interconnect 7 of Figure 4 the base layer 9 and first and second insulating layers 10 and 12 are made of a low loss dielectric material such as a polyimide or a polytetrafluoroethylene and glass composite material. A suitable polyimide is PYRALUX which is a registered trade mark of Du Pont Limited and a suitable composite is DUROID which is a registered trade mark of
The Rodgers Corporation. The shielding member 8, the or each electrically conductive member 11 and shielding coating 13 are made of metallic material, preferably copper. As illustrated in Figure 4 the coating layer 13 may be lipped over the edge of the channel 13 remote from the base 13b.
In the process of the present invention outlines of the channels 13 are defined in any convenient manner such as by laser ablation or photolithographically on the insulating layer 12 and the insulating layer material removed from within the outlines to provide the channels 13 in any convenient manner, such as by wet chemical etching or by plasma processing. Preferably the channels 13 extend substantially parallel to the members 11. The channels 13 may have any desired cross sectional shape such as the tapered side walls construction illustrated in
Figures 3 and 4 or a parallel side wall construction.
The shielding coating 14 preferably is of metallic material such as copper which is applied in any convenient way such as by physical vapour deposition, chemical vapour deposition or electro chemically. A suitable physical vapour deposition technique is by sputtering.
Thus in essence the process of the present invention provides a thin film multi-layer interconnect 7 which has at least one elongated electrically conductive member 11 embedded in electrically insulating material 10 and 12 with the insulating material 10 and 12 and member 11 being encased at least substantially along its length, by an electrically conductive shield at least partially embedded in electrically insulating material 9, 10 and 12. The electrically conductive shield preferably is made up from a channel coating 14 and a shield layer 8.
Claims (12)
1. A process for manufacturing a thin film multi-layer interconnect, including the steps of applying at least one elongated strip-like first electrically conductive shielding member to an electrically insulating base layer, applying at least one first electrically insulating layer to the base layer and first shielding member, applying at least one elongated electrically conductive member to said first insulating layer to extend at a spacing from said first shielding member, applying at least a second electrically insulating layer to said electrically conductive member and first insulating layer, forming at least two channels through said second and first insulating layers, one on each side of the.electrically conductive member, to a depth sufficient to expose part of said first shielding member, and applying an electrically conductive shielding coating to the channelled region of the interconnect to cover the side wells of said channels, the basis of said channels into contact with the exposed parts of the first shielding member and over the surface of said second insulating layer extending between the two channels, thereby to encase, with said first shielding member and shielding coating, said at least one electrically conductive member and surrounding electrically insulating layer material along substantially the length of the electrically conductive member.
2. A process according to claim 1, in which the base layer and first and second insulating layers utilised are made of a low loss dielectric material.
3. A process according to claim 1 or claim 2, in which the shielding member, electrically conductive member and shielding coating utilised are made of metallic material.
4. A process according to claim 3, in which the metallic material utilised is copper.
5. A process according to any one of claims 1 to 4, in which outlines of said channels are defined photolithographically or by laser ablation and in which the insulating layer material is removed from within said outlines to provide said channels, by wet chemical etching or by plasma processing.
6. A process according to any one of claims 1 to 5, in which said shielding coating is of metallic material which is applied by physical vapour deposition, chemical vapour deposition or electro chemically.
7. A processing for manufacturing a thin film, multi-layer interconnect, substantially as hereinbefore described and as illustrated in Figures 2 to 4 of the accompanying drawings.
8. A thin film, multi-layer interconnect, having at least one elongated electrically conductive member embedded in electrically insulating material, with said insulating material and conductive member being encased at least substantially along its length, by an electrically conductive shield at-least partially embedded in electrically insulating material.
9. An interconnect according to claim 8, wherein the electrically conductive member and shield are made of metallic material.
10. An interconnect according to claim 9, wherein the metallic material is copper.
11. An interconnect according to any one of claims 8 to 10, wherein the insulating material is a polyimide or a polytetrafluoroethylene and glass composite.
12. A thin film, multi-layer interconnect, substantially as hereinbefore described and as illustrated in Figure 4, as modified or not by Figures 2 or 3 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9308677A GB2277832B (en) | 1993-04-27 | 1993-04-27 | Thin film multi-layer interconnect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9308677A GB2277832B (en) | 1993-04-27 | 1993-04-27 | Thin film multi-layer interconnect |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9308677D0 GB9308677D0 (en) | 1993-06-09 |
| GB2277832A true GB2277832A (en) | 1994-11-09 |
| GB2277832B GB2277832B (en) | 1997-01-15 |
Family
ID=10734544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9308677A Expired - Fee Related GB2277832B (en) | 1993-04-27 | 1993-04-27 | Thin film multi-layer interconnect |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2277832B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998006243A1 (en) * | 1996-07-31 | 1998-02-12 | Dyconex Patente | Process for producing connecting conductors |
| WO2001031706A1 (en) * | 1999-10-28 | 2001-05-03 | Koninklijke Philips Electronics N.V. | Methods for forming co-axial interconnect lines in a cmos process |
| EP1139353A2 (en) * | 2000-03-30 | 2001-10-04 | Victor Company Of Japan, Ltd. | Production method of thin film resistance element formed on printed circuit board, and thin film resistance element employing the method |
| EP1196013A2 (en) * | 2000-10-03 | 2002-04-10 | Victor Company Of Japan, Ltd. | Printed circuit board and manufacturing method of the printed circuit board |
| GB2379089A (en) * | 2001-08-21 | 2003-02-26 | Ubinetics Ltd | RF screening for printed circuit boards |
| GB2382231A (en) * | 2001-11-01 | 2003-05-21 | Motorola Inc | Isolator device for RF radiators |
| US6569757B1 (en) | 1999-10-28 | 2003-05-27 | Philips Electronics North America Corporation | Methods for forming co-axial interconnect lines in a CMOS process for high speed applications |
| FR2849346A1 (en) * | 2002-12-20 | 2004-06-25 | Thales Sa | Avionics/telecommunications hyperfrequency units having volume outer Faraday cage formed surface conductor and outer connection point with input/output across face with face outer surface forming mounting surface |
| EP2573865A1 (en) * | 2010-06-29 | 2013-03-27 | Huawei Technologies Co., Ltd. | Feed network and antenna |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112373077B (en) * | 2020-10-22 | 2022-05-06 | 江苏南锦电子材料有限公司 | Assembling method of electromagnetic shielding heat-conducting adhesive tape |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0163795A2 (en) * | 1983-12-13 | 1985-12-11 | Fairchild Semiconductor Corporation | A method and means for reducing signal propagation losses in very large scale integrated circuits |
| GB2168857A (en) * | 1984-11-14 | 1986-06-25 | Int Standard Electric Corp | Method and structure for interconnecting high frequency components |
| GB2255235A (en) * | 1991-04-27 | 1992-10-28 | Murata Manufacturing Co | Shielding strip-line oscillators |
-
1993
- 1993-04-27 GB GB9308677A patent/GB2277832B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0163795A2 (en) * | 1983-12-13 | 1985-12-11 | Fairchild Semiconductor Corporation | A method and means for reducing signal propagation losses in very large scale integrated circuits |
| GB2168857A (en) * | 1984-11-14 | 1986-06-25 | Int Standard Electric Corp | Method and structure for interconnecting high frequency components |
| GB2255235A (en) * | 1991-04-27 | 1992-10-28 | Murata Manufacturing Co | Shielding strip-line oscillators |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486394B1 (en) | 1996-07-31 | 2002-11-26 | Dyconex Patente Ag | Process for producing connecting conductors |
| WO1998006243A1 (en) * | 1996-07-31 | 1998-02-12 | Dyconex Patente | Process for producing connecting conductors |
| US6569757B1 (en) | 1999-10-28 | 2003-05-27 | Philips Electronics North America Corporation | Methods for forming co-axial interconnect lines in a CMOS process for high speed applications |
| WO2001031706A1 (en) * | 1999-10-28 | 2001-05-03 | Koninklijke Philips Electronics N.V. | Methods for forming co-axial interconnect lines in a cmos process |
| KR100742023B1 (en) * | 1999-10-28 | 2007-07-23 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Methods for forming co-axial interconnect lines in a cmos process |
| US6545338B1 (en) | 1999-10-28 | 2003-04-08 | Koninklijke Philips Electronics N.V. | Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications |
| EP1139353A2 (en) * | 2000-03-30 | 2001-10-04 | Victor Company Of Japan, Ltd. | Production method of thin film resistance element formed on printed circuit board, and thin film resistance element employing the method |
| EP1139353A3 (en) * | 2000-03-30 | 2004-01-21 | Victor Company Of Japan, Ltd. | Production method of thin film resistance element formed on printed circuit board, and thin film resistance element employing the method |
| EP1196013A3 (en) * | 2000-10-03 | 2003-06-18 | Victor Company Of Japan, Ltd. | Printed circuit board and manufacturing method of the printed circuit board |
| EP1196013A2 (en) * | 2000-10-03 | 2002-04-10 | Victor Company Of Japan, Ltd. | Printed circuit board and manufacturing method of the printed circuit board |
| GB2379089A (en) * | 2001-08-21 | 2003-02-26 | Ubinetics Ltd | RF screening for printed circuit boards |
| GB2382231B (en) * | 2001-11-01 | 2003-12-24 | Motorola Inc | Isolator devices for current suppression |
| GB2382231A (en) * | 2001-11-01 | 2003-05-21 | Motorola Inc | Isolator device for RF radiators |
| FR2849346A1 (en) * | 2002-12-20 | 2004-06-25 | Thales Sa | Avionics/telecommunications hyperfrequency units having volume outer Faraday cage formed surface conductor and outer connection point with input/output across face with face outer surface forming mounting surface |
| EP2573865A1 (en) * | 2010-06-29 | 2013-03-27 | Huawei Technologies Co., Ltd. | Feed network and antenna |
| EP2573865A4 (en) * | 2010-06-29 | 2013-06-05 | Huawei Tech Co Ltd | Feed network and antenna |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2277832B (en) | 1997-01-15 |
| GB9308677D0 (en) | 1993-06-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100427 |