GB2166613A

GB2166613A - Digital-analog conversion

Info

Publication number: GB2166613A
Application number: GB08524299A
Authority: GB
Inventors: Joji Nagahira
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1984-10-02
Filing date: 1985-10-02
Publication date: 1986-05-08
Also published as: GB2166613B; DE3535021A1; DE3535021C2; GB8524299D0

Abstract

Digital-analog converting apparatus selects pulse signals from a plurality of pulse signals having a predetermined pulse width and different in period, Fig. 3, in accordance with input digital data, thereby producing a signal, Fig. 4, which is filtered. <IMAGE>

Description

SPECIFICATION Digital-Analog Converting Apparatus Background of the Invention Field of the Invention This invention relates to an apparatus for converting digital data into analog data.

Description of the Prior Art Heretofore, the apparatus of this type has converted digital data into an analog value (hereinafter referred to as the D/A conversion) by changing the operating pulse width relative to a predetermined period T, that is, by the pulse width modulating system.

According to this system where, for example, an analog value of a half value is to be put out, the ON period and the OFF period of the pulse become equal to each other, thus resulting in a square wave form signal of a frequency 1/T.

This signal of a frequency 1/T is a low frequency signal and therefore, to eliminate this AC component, the filter effect must be increased, and this has led to a disadvantage that the response speed is low. Also, to increase the response speed, it is necessary to decrease the filter effect, and this has caused the ripple component to be increased.

Summary of the Invention The present invention has been made in view of the above-noted points and an object thereof is to provide an improved digital-analog converting apparatus.

A further object of the present invention is to provide a digital-analog converting apparatus which is high in response speed and can decrease ripples.

Still a further object of the present invention is to provide a digital-analog converting apparatus in which the number of ports necessary for digitalanalog conversion can be reduced.

The above and other objects of the present invention will become apparent from the following detailed description.

Brief Description of the Drawings Figures 1,8, 10, 14 and 16 are block diagrams conceptionally showing embodiments of the present invention.

Figures 2,9 and 11 are block diagrams of D/A converting apparatuses.

Figure 3 shows a clock pulse input to MPU and the wave forms of signals prodused by the MPU.

Figure 4 shows an example of the digital pattern obtained by composing various wave forms.

Figure 5 shows the relation between DAC and M,.

Figures 6, 7, 12, 13, 15 and 17-19 are flow charts for DIA conversion processing.

Description of the Preferred Embodiments The present invention will hereinafter be described in detail by reference to the drawings.

Figure 1 conceptionally shows an embodiment of the present invention. With a time corresponding to a clock pulse input from clock generating means 2 to a digital computer 1 being used as a minimum fundamental time, n wave forms with weights are produced by wave form producing means 3, and predetermined ones of said wave forms are selected and composed by wave form selection means 8 and wave form composition means 9 in accordance with a digitial data 7 of n bits obtained by switch input means 4, communication means 6, etc., whereby the thus obtained digital pattern is input to filter means 10, thereby obtaining an analog value.

Figure 2 is a block diagram showing a control circuit for carrying out the embodiment shown in Figure 1. Reference numeral 100 designates a digital computer-(hereinafter referred to as MPU) which puts out various pulse wave forms as shown in Figure 3. The MPU 100 is comprised chiefly of a well-known microcomputer containing ROM, RAM, etc. therein. Reference numeral 102 denotes a circuit which generates a clock pulse as shown in Figure 3 and puts out a clock pulse signal of pulse width t/2 to the MPU 100.Reference numeral 104 designates a switch for inputting various data, reference numeral 105 denotes a display device for displaying various data, reference numeral 106 designates a digital computer for effecting communications with the MPU 100 and transmitting data for D/A conversion to the MPU 100, and reference numerals 110-1 and 110-2 denote filters for converting a digital data put out from the MPU 100 into an analog data. The filter 110-1 is comprised of a resistor R1 and a capacitor C1, and the filter 110-2 is comprised of a resistor R2 and a capacitor C2.

Description will now be made by taking as an example a case where a data of 4 bits is D/Aconverted.

In Figure 3, wave form 1 is a signal in which the ratio of high level (H) and low level (L) is 1:1, and by this signal passing through the filter 110-1 or 110-2, there is obtained a DC value of 1/2. Wave form 2 is a signal in which the ratio of H level and L level is 1:3, and by this signal passing through the filter 110-1 or 110-2, there is obtained an analog value of 1/4. Wave form 3 is a signal in which the ratio of H level and L level is 1:7, and by this signal passing through the filter 110-1 or 110-2, there is obtained an analog value of 1/8. Wave form 4 is a signal in which the ratio of H level and L level is 1 :15, and by this signal passing through the filter 110-1 or 110-2, there is obtained a DC value of 1/16. These signal wave forms are made to correspond to the respective bits of the digital data for D/A conversion.

That is, the wave form 1 is produced by the most significant bit 3 of the digital data for D/A conversion stored in a predetermined area in the RAM of the MPU 100, the wave form 2 is produced by the bit 2 of said digital data, the wave form 3 is produced by the bit 1 of said digital data, and the wave form 4 is produced by the least signficant bit 0 of said digital data, whereby the DC values correspond to the respective bits and can be composed to thereby obtain sixteen stages of analog values.

For example, where the digital data is 1010, a digital pattern in which the wave forms 1 and 3 corresponding to the bits 3 and 1 of the digital data as shown in Figures 4(1) are composed together can be produced to thereby obtain an analog value 10/16.

Also, where the digital data is 0110, a digital pattern in which the wave forms 2 and 3 corresponding to the bits 2 and 3 as shown in Figure 4(2) are composed together can be produced to thereby obtain an analog value 6/16.

Reference is now had to the flow charts of Figures 6 and 7 to further describe the D/A conversion by the present invention.

First, at step 1 (S1), the data from the switch 104 is input and processed. Also, a display data is put out to the display device 105.

At step 2 (S2), communication is effected with the digital computer 106 and the data for D/A conversion is obtained and set to a predetermined area in the RAM in the MPU 100.

At step 3(S3), a data to be set to the output port of D/A is obtained from the D/A data of the predetermined RAM.

The details of this will hereinafter be described by reference to Figure 7.

At step 10 (S10), increment of the content of a D/A counter (DAC) set in the RAM is done. An accumulator is loaded with the content of DAC. At step 11 (S11), 1000 (a binary value) is set in a memory (M1) set in the RAM. At step 12 (S12), a carry flag is reset and the content of the accumulator is shifted to the right. The least significant bit of the content of the accumulator is transferred to the carry. The content of the carry is set to the most significant bit of the accumulator.

At step 13 (S13), whether the carry flag is set is judged and, if there is the carry flag, the program proceeds to step 16 (S16). If there is notthe carry flag, the program proceeds to step 14(S14). At step S14, the carry flag is reset and the content of the memory (M1) is shifted to the right. The least significant bit of the content of the memory M1 is transferred to the carry. The content of the carry is set to the most significant bit of the memory M1.

At step 15 (S15), whether the carry flag is set is judged and, if there is the carry, the program proceeds to step 16 (S16). If there is not the carry, the program proceeds to step 12 (S12).

By the steps from S10 to S15, the value of M1 shown in Figure 5 is obtained from the counter (DAC). The time series at which the data of Ml by the increment operation of the counter (DAC) is produced correspond to the wave forms of Figure 3.

Next, at step 16 (S16), the content of a register (P1R) for securing the data to be put out to an output port 1 (P1) is reset. At step 17 (S17), AND is taken between the data of M1 and the conversion data (DAD1 ) of D/A put but to the port 1, and when the value of the result is 0, the program proceeds to step 195(319), and when the value of the result is not 0, the program proceeds to step 18 (S18). At step S18, the register Pi R is set. At step 19 (S19) the data to be put out to an output port 2 (P2) is secured. The content of a register P2R is reset.At step 20 (S20), AND is taken between the data of M1 and the conversion data (DAD2) of D/A put out to the port 2 and, if the value of the result is 0, the sub routine is terminated, and if the value of the result is not 0, the program proceeds to step 21 (S21). At step 321, the register P2R is set.

The steps from S16 to S21 are ones at which whether the wave forms shown in Figure 3 are to be put out to the respective bits of the conversion data of D/A is judged and predetermined ones of the wave forms are composed together in conformity with the result of the judgment.

At step 4 (S4), it is detected that the external clock input data input from the clock generating circuit 102 to the MPU 100 is art a high level and, when it is then detected that said external clock input data is at a low level, the program proceeds to step 5 (S5).

This is for the purpose of detecting the edge of the external clock and obtaining a predetermined pulse width t corresponding to the period of the external clock.

At step 5 (S5), the content of the outputting register P1 R is put out to the port 1 (P1). Also, the content of the outputting register P2R is put out to the port 2 (P2). The steps S1 to S5 are repetitively executed and the time of the pulse width of the digital pattern put out is made into a predetermined time t by the judgment at step S4.

Also, by the processing of the steps S1 to S5 being effected, the value of the counter (DAC) is counted by one count each, and the output wave form of D/A can be time-serially produced as a composed wave form.

The composed wave form thus produced is input to the filters 110-1 and 110-2 and is converted into an analog value as previously described.

In the above-described embodiment, the time corresponding to the clock pulse input from the clock generating circuit to the digital computer is the minimum fundamental time, but alternatively, a time obtained by sensing the time of the internal times of the digital computer may be the minimum fundamental time.

Figure 8 conceptionally shows this embodiment.

With a predetermined time obtained by sensing the time of the internal timer 12 of a digital computer 1 being used as a minimum fundamental time, n wave forms with weights are produced by wave form producing means 3, and particular ones of said wave forms are selected and composed by wave form selection means 8 and wave form composition means 9 in accordance with a digital data 7 of n bits obtained by switch input means 4, communication means 6, etc., whereby the thus obtained digital pattern is input to filter means 10, thereby obtaining an analog value. In Figure 8, members given reference numerals similar to those in Figure 1 are similar members.

Figure 9 is a block diagram showing a control circuit for carrying out the embodiment of Figure 8.

In Figure 9, members given reference numerals similar to those in Figure 2 are similar members and need not be described.

The control flow chart ofthis embodiment is also similar to Figures 6 and 7.

Also, a clock pulse may be input to the interruption terminal of the digital computer and D/A conversion can be accomplished with a time obtained by this interruption processing being used as a minimum fundamental time.

Figure 10 conceptionally shows this embodiment.

A clock pulse is input from clock generating means 2 to the interruption terminal INT of a digital computer 1, and with a predetermined time obtained by this interruption processing being used as a minimum fundamental time, n wave forms with weights are produced by wave form producing means, and predetermined ones of said wave forms are selected and composed by wave form selection means 8 and wave form composition means 9 in accordance with a digital data of n bits obtained by switch input means 4, communication means 6, etc., whereby the thus obtained digital pattern is input to filter means 10, thereby obtaining an analog value.

Figure 11 is a block diagram showing a control circuit for carrying out the embodiment of Figure 10, and Figures 12 and 13 are flow charts showing the flow of control.

The D/A conversion by the present embodiment will be further described by reference to these flow charts. First, at step 31 (S31), the data from the switch 104 is input and processed. Also, the display data is put out to the display device 105. At step 32 (S32), a communication with the digital computer 106 is effected, and a data for effecting D/A conversion is obtained and set to a predetermined area in the RAM in the MPU 100.

Then, these steps S31 and S32 are repetitively executed. When, in the meantime, a clock pulse is input from the clock generating circuit 102 to the interruption terminal INT of the MPU 100, the MPU 100 effects the D/A conversion process shown in Figure 13. In the present embodiment, the interruption processing is executed by sensing the falling of the clock pulse.

The details of this will now be described by reference to Figure 13. At step 33 (S33), the content of the outputting register P1 R set in the RAM is set to the port P1 and the content of the outputting register P2R is set to the port P2. Then, steps 34 (S34)--45 (S45) are executed. These steps 3445 are the same as the steps 10-21 of Figure 7 and therefore need not be described.

The aforementioned D/A conversion can also be accomplished by the interruption processing by the internal timer of the digital computer.

Figure 14 conceptionally shows the embodiment.

Interruption is exerted by the internal timer of the digital computer 1 and an interruption routine is executed to thereby effect the D/A conversion processing and obtain a predetermined time, and with this predetermined time being used as a minimum fundamental time, n wave forms with weights are produced by wave form producing means, and particular ones of said wave forms are selected and composed by wave form selection means 8 and wave form composition means 9 in accordance with a digital data of n bits obtained by switch input means 4, communication means 6, etc., whereby the thus obtained digital pattern is input to filter means 10, thereby obtaining an analog value.

The control circuit for carrying out the D/A conversions as shown in Figure 14 is similar to the control circuit of Figure 9.

While the steps as shown in Figure 12 are being repetitively executed, interruption is exerted at a predetermined time interval by the internal timer and the D/A conversion processing as shown in Figure 15 is effected.

At step 53 (S53), the internal timer is set to a predetermined time and started. At step S4 (S54), the content of the outputting register P1 R set in the RAM is set to the port P1 and the content of the outputting register P2R is set to the port P2. Then, steps 55 (S55)--66 (S66) are executed. These steps are similarto the steps 1021 of Figure 7 and therefore need not be described.

Also, the D/A conversion as previously described can be accomplished with a time obtained by the soft timer processing of the digital computer being used as a minimum fundamental time.

Figure 16 conceptionally shows this embodiment.

With a predetermined time obtained by the soft timer processing of the digital computer 1 being used as a minimum fundamental time, n wave forms with weights are produced by wave form producing means, and particular ones of said wave forms are selected and composed by wave form selection means 8 and wave form composition means 9 in accordance with a digital data of n bits obtained by switch input means 4, communication means 6, etc., whereby the thus obtained digital pattern is input to filter means 10, thereby obtaining an analog value.

The control circuit for carrying out the D/A conversion as shown in Figure 16 is similar to the control circuit of Figure 9.

Description will now be made by reference to the flow charts of Figures 17-19. First, at step 101 (S101), the data from the switch 104 is input and processed. At step 102 (S102), the remaining time until a predetermined time is reached is set to the accumulator, and at step 103 (S103), the program proceeds to the soft timer sub routine shown in detail in Figure 19 and the remaining time is counted. At step 104 (S104), the D/A conversion processing shown in detail in Figure 18 is effected.

At step 105 (S105), the display data is put out to the display device 105. At step 106 (3106), the remaining time until a predetermined time is reached is set to the accumulator and, at step 107 (S107), the program proceeds to the soft timer sub routine and the remaining time is counted. At step 108 (S108), the D/A conversion processing is effected. At step 109 (S109), a communication with the computer 106 is effected and the content of the D/A converter is shifted to the right. The least significant bit of the content of the accumulator is transferred to the carry. The content of the carry is set to the most significant bit of the accumulator. At step 124 (S124), whether the carry flag is set is judged and, if there is the carry flag, the program proceeds to step 127 (S127). If there is not the carry flag, the program proceeds to step 101 (S101).

Next, D/A conversion processing will be explained in detail referring to Fig. 18. First, at step 120 (S120), the content of output register P1 R, which has been set in a predetermined area of said RAM, is put out to port 1 (P1), and the content of output register P2R is put out to port 2 (P2). At step 121(3121), the content of D/A counter (DAC) which has been set in said RAM is subjected to increment, and then loaded on the accumulator. At step 122 (S122), the binary value "1000" is set in a memory (M1) set in said RAM. At step 123 (S123), a carry flag is reset" and the content of the D/A converter is shifted to the right. The least significant bit of the content of the accumulator is transferred to the carry. The content of the carry is set to the most significant bit of the accumulator.At step 124 (S124), whether the carry flag is set is judged and, if there is the carry flag, the program proceeds to step 127 (S127). If there is not the carry flag, the program proceeds to step 125 (S125). At step S125, the carry flag is reset and the content of the memory M1 is shifted to the right. The least significant bit of the content of the memory M1 is transferred to the carry. The content of the carry is set to the most significant bit of the memory M1. At step 126 (S126), whether the carry flag is set is judged and, if there is the carry, the program proceeds to step 130 (S130), and if there is not the carry, the program proceeds to step 123 (S123). At step 127 (S127), the carry flag is reset and the content of the memory M1 is shifted to the right.The least significant bit of the content of the memory M1 is transferred to the carry. The content ofthe carry is settothe most significant bitofthe memory M1. At step 128 (3128), whether the carry flag is set is judged and, if there is the carry, the program proceeds to step 3130. If there is not the carry, the program proceeds to step 129 (S129). Step S129 is a step at which delay is effected by the same time as the processing time of steps S123 and S124 with nothing being processed (no operation).

The flow from step S121 to step S129 is programmed so that the processing time up to step S130 is constant whichever processing course is passed through. Also, the time series in which the value of M1 shown in Figure 5 is obtained from the value of the counter DAC and the data of M1 by the increment operation of the counter DAC is produced correspond to the various wave forms of Figure 3.

At step S130, AND is taken between the data of M1 and the D/A conversion data DAD1 put out to the port 1 and, if the value of the result thereof is 0, the program proceeds to step 1-32 (S132), and if said value is not 0, the program proceeds to step 131 (S131). At step S131, the content of the register Pi R for securing the data to be put out to the output port P1 is set. At step 3132, the content of the register Pi R is reset.

At step 133 (S133), AND is taken between the data of M1 and the D/Aconversion data DAD2 put otto the port 2 and, if the ,value of the result thereof is0, the program proceeds to step 135 (S135), and if said value is not 0, the program proceeds to step 134 (S134). At step S134, the content of the register P2R for securing the data to be put out to the output port P2 is set. At step S135, the content of the register P2R is reset.

The flow from step S130 to step S135 judges whether the wave forms shown in Figure 3 are put out to the respective bits of the D/A conversion data, and composes predetermined ones of the wave forms in conformity with the result of the judgement.

Also, the sub routine of D/A conversion is programmed so that the processing time is constant whichever processing course is passed through.

The soft timer processing will now be described in detail by reference to Figure 19.

At step 141(3141), decrement of the value of the accumulator is effected and, if the value of the accumulator is not 0 at step 142 (S142), the program proceeds to step S141, and if the value of the accumulator is 0, the processing is terminated.

By the above-described processing, the D/A sub routine is called for each predetermined time and the time of pulse width t is rendered constant.

Each time the DIA sub routine is called in this processing, the value of the counter DAC is counted by one count each and the output wave form of D/A can be time-serially produced as a composite wave form.

The composite wave form thus produced is input to the filters 110-1 and 110-2 and is converted into an analog value as previously described.

This analog value is used for the adjustment of the process amount such as the amount of charge orthe amount of exposure, for example, in an image forming apparatus such as a copying apparatus.

In the present embodiment, the data for D/A conversion is obtained by the communication with a digital computer, whereas this is not restrictive, but design may also be made such that such data is obtained, for example, by a key input or the like.

Also, of course, the various pulse wave forms produced by the MPU may be inverted.

Also, the state for M, =0000 may be H level or L level.

Also, the number of bits ofthe data forD/A conversion may be arbitrary.

Thus, the present invention is of a construction in which a predetermined pulse signal is composed out of a plurality of pulse signals having a predetermined pulse width and different in period, in accordance with the digital data input, and an analog value is obtained from this composed signal and therefore, in the present invention, as compared with the pulse width modulating system according to the prior art, the pulse signal is a high frequency signal and the response speed is high and also, ripples can be reduced.

Also, the ports for D/A conversion can be an analog data per port and therefore, the number of ports necessary for D/A conversion can be reduced.

Further, the period can be made small by using only the more significant bits during D/A conversion and therefore, the response speed can be increased and ripples can be decreased.

Claims

1. A digital-analog converting apparatus comprising: input means for inputting a digital data; converting means for putting out a pattern signal in response to the digital data input from said input means, said converting means selecting and composing a predetermined pulse signal from among a plurality of pulse signals having a predetermined pulse width and different in period, in accordance with the input digital data, thereby putting out said pattern signal; and output means for putting out an analog signal in response to the pattern signal put out from said converting means.

2. A digital-analog converting apparatus according to Claim 1, wherein said converting means has a digital computer and selects and compose said pulse signal by said digital computer.

3. A digital-analog converting apparatus according to Claim 2, wherein said converting means further has signal generating means for generating a predetermined clock signal and determines said pulse width in accordance with the clock signal input from said signal generating means to said digital computer.

4. A digital-analog converting apparatus according to Claim 2, wherein said converting means further has interruption signal output means for putting out a signal for effecting interruption processing while said digital computer is executing predetermined processing, and determines said predetermined pulse width by said interruption processing.

5. A digital-analog converting apparatus according to Claim 2, wherein said predetermined pulse width is determined by sensing the time of the internal timer of said digital computer.

6. A digital-analog converting apparatus according to Claim 2, wherein said predetermined pulse width is determined by exerting an interruption at a predetermined time interval by the internal time of said digital computer and effecting interruption processing.

7. A digital-analog converting apparatus according to Claim 2, wherein said predetermined pulse width is determined by a program timer.

8. A digital-analog converting apparatus according to Claim 2, wherein said digital computer has a plurality of ports for putting out said pattern signal.

9. A digital-analog converting apparatus according to Claim 2, wherein said digital data is obtained by the communication by said digital computer.

10. Digital-to-analog converting apparatus substantially as herein described with reference to any of the accompanying drawings.