JPS6184119A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To increase the response speed and to reduce the ripple by deciding a pulse width through the interruption processing from an interruption signal output means from a digital computer generating plural pulse signals having a prescribed pulse width and different period. CONSTITUTION:A clock pulse is inputted to an interruption terminal INT of a digital computer 1 from a clock generating means 2, a prescribed time obtained from the interruption processing is used as the minimum basic time and n-set of weighted waveforms by a waveform generating means 3. A prescribed waveform is selected and synthesized among waveforms generated by the means 9 in response to an n-bit of digital data 7 obtained by a switch input means 4 and a communication means 6. The synthesized digital pattern is inputted to a filter means 10 to obtain an analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an apparatus for converting digital data to analog data.

Prior Art Conventionally, this type of device changes the operating pulse width with respect to a constant period T, that is, converts digital data into an analog value (hereinafter referred to as D/A conversion) using a pulse width modulation method.
Was.

According to this method, for example, when outputting a half-value analog value, the ON period and OFF period of the pulse are the same, resulting in a square wave signal with a frequency of 1/T.

Since this signal with a frequency of 1/T is a low frequency signal, it is necessary to increase the filter effect in order to remove this alternating current component, which has the drawback of slowing down the response speed. Furthermore, in order to increase the response speed, it is necessary to reduce the filter effect, which causes an increase in ripple components.

OBJECTS The present invention has been made in view of the above points, and an object of the present invention is to provide a digital-to-analog conversion device capable of increasing response speed and reducing ripples in analog data.

Example The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram conceptually showing an embodiment of the present invention. A clock pulse is input from the clock generation means 2 to the interrupt terminal NT of the digital computer 1, and the waveform generation means generates n weighted waveforms using a predetermined time obtained by this interrupt processing as the minimum basic time. The waveform selecting means 8 and the waveform synthesizing means 9 selectively synthesize a predetermined waveform from the waveforms according to the n-bit digital data obtained by the switch manual means 4, the communication means 6, etc.; The digital pattern thus obtained is filtered by the filter means 1.
0 and obtain an analog value.

FIG. 2 is a block diagram showing a control circuit for implementing the present invention. Reference numeral 100 is a digital computer (hereinafter referred to as MPσ) which outputs various pulse waveforms as shown in FIG. 102 is a circuit that generates a clock pulse as shown in FIG.
Output to Q's interrupt terminal NT. 104 is a switch for inputting various data; 105 is a display for displaying various data; 106 is a digital computer that communicates with the MPU 100 and sends data for D/A conversion to the MPU 100; 110-1 , 110-2 is an MPU
A filter for converting digital data output from 100 into analog data, each with a resistor R1
, a capacitor C5, a resistor R2, and a capacitor C2.

Here, an example will be explained in which 4-bit data is D/A converted.

In FIG. 3, waveform 1 is a signal with a ratio of 1:1 level (H) and low level (L), and the filter 110-1
Or by passing through 110-2, a DC value of % is obtained. Waveform 2 is a signal with a ratio of H level to L level of 1:3, and an analog value is obtained by passing through filter 110-1 or 110-2. Waveform 3 is a signal with a ratio of H level to L level of 1, and the filter 11 (1-1
or passing through 110-2 (yoshi% analog value is obtained).

Waveform 4 is a signal with a ratio of H level to L level of 1:15, and a DC value of 1/16 is obtained by passing through filter 110-1 or 11[1-2. These signal waveforms are made to correspond to each bit of digital data for D/A conversion.

That is, waveform 1 is determined by the most significant bit 3 of the digital data for D/A i conversion stored in a predetermined area in the RAM of the MPU 100, waveform 2 is determined by bit 2, and waveform 2 is determined by bit 1.
By generating waveform 6 with the lowest bit 0 and waveform 4 with the least significant bit 0, DC values correspond to each bit, and by combining them, 16 levels of analog values can be obtained.

For example, if the digital data is 1010,
)K By generating a digital pattern by combining waveforms 1 and 6 corresponding to bits 3 and 1 of the digital data, an analog value of 10/16 can be obtained.

Also, if the digital data is 0110, Fig. 4 (2)
By generating a digital pattern by combining waveforms 2 and 3 corresponding to bits 2 and 3 as shown in FIG. 1, 6716 analog values can be obtained from K.

Next, the D/A conversion according to the present invention will be further explained using the flowchart shown in FIG. 6.7. First step 1
At (81), data from the switch 104 is input and processed. It also outputs display data to the display 105. In step 2 (62), communication is performed with the digital computer 106, data for D/A conversion is obtained, and the data is set in a predetermined area in the RAM in the MPU 100.

Then, this day 42nd□ is repeatedly executed. During this period, the clock pulse 1.0 is output from the clock generation circuit 102. (P.U.
When input to the interrupt terminal NT 100, the MPU 100 performs the D/A conversion process shown in FIG. In this embodiment, interrupt processing is executed by sensing the falling edge of a clock pulse.

The details will be explained with reference to FIG. 7. Step 9)
The output register P1 set in the RAM in
The contents of R are transferred to baud) (P+), and the output register P2R
Set the contents of to the port (P2). Step 10
At (810), the contents of a D/A counter (DAC) set in the RAM is incremented. D.A.
Loading the contents of C into the accumulator Step 11
(Ell) is the memory set in the RAM (
Set 1000 (binary value) to Ml). In step 12 (s12), the carry flag is reset and the contents of the accumulator are shifted to the right. The least significant bit of the contents of the accumulator is then placed in the carry. The contents of the carry are set in the most significant bit of the accumulator. In step 15 (813), it is determined whether the carry flag is set, and if there is a carry flag, the process proceeds to step 16 (816). If there is no carry flag, the process advances to step 14 (814). At 814, the carry flag is reset and the contents of memory C are shifted to the right. The least significant bit of the contents of Ml is moved to carry. The contents of the carry are set in the upper bit of Ml:#. In step 15 (815), it is determined whether the carry flag is set, and if there is a carry, the process advances to step 16 (816). If there is no carry, proceed to step 12 (812).

The steps from 810 to 815 cause the counter (DA
The value of Ml shown in FIG. 5 is obtained from the value of C). counter(
The time series for generating M1 data by the increment operation of the DAC) corresponds to the waveforms shown in FIG.

Next, in step 16 (816), output capo) 1 (P
1) Reset the contents of the register (PIR) that secures the data to be output to. In step 17 (817) Ml
data and D/A conversion data output to port 1 (D
If the resulting value is O, the process goes to step 19 (819), and if it is not 0, the process goes to step 18 (818). In 818, register P
Set 1Ri. In step 19 (S19), the data tJffi to be output to output capo 2 (P2) is stored. Resets the contents of register (P2R).

In step 20 (820), Ml data and port 2
AkJD is calculated between the D/A conversion data (DAD2) outputted to , and when the resulting value is O, the subroutine ends, and when it is not 0, the process goes to step 21 (821) a-b
. At 821, register P2R is set.

Steps from 816 to 821 are D/A change 3
゛) For each bit of data, determine whether or not to output each waveform shown in Figure 5, and according to the determination result, synthesize a predetermined one of each waveform. Using the clock, the interrupt routine can be executed at regular intervals to obtain a time with a predetermined pulse width, the value of the counter (DAC) is counted by 1 for each interrupt, and the output waveform of the D/A is It can be generated chronologically as a composite waveform.

The composite waveform generated in this way is filtered by the filter 110-
1 and 110-2, and is converted into an analog value as described above.

This analog value is used, for example, in an image forming apparatus such as a copying machine to adjust process quantities such as the amount of charge and the amount of exposure.

In this embodiment, the data for D/A conversion was obtained through communication with another digital computer, but the data is not limited to this, and may be obtained by, for example, manual input (R-configuration may also be used).

It goes without saying that the various pulse waveforms generated by the MPU may be inverted.

Also, the state for l+L+=oooo is L even at H level.
It may be level.

Furthermore, the bits of the D/A conversion data may be any number of bits.

Furthermore, in this embodiment, the interrupt processing is executed by the falling edge of the clock pulse input from the outside, but the interrupt processing may be executed by the rising edge 9 of the clock pulse inputted from the outside. By applying an external interrupt, a predetermined pulse signal is synthesized according to the input digital data from among pulse signals with a predetermined pulse width and mantissas of different periods, and an analog value is obtained from this synthesized signal. Because of the high speed that can be obtained, the response speed for high-frequency signals is faster and ripples can be reduced compared to conventional pulse width modulation methods.

Furthermore, since the number of ports for D/'A conversion can be one port and one analog data, the number of ports required for D/A conversion can be reduced.

Also, by using only the upper bits during D/A conversion)
, and the ripples can be made smaller, the response speed can be further increased and ripples can be reduced.

Furthermore, a stable pulse width can be obtained in synchronization with an external clock signal without requiring a timer.

[Brief Description of the Drawings] Fig. 1 is a block diagram conceptually showing an embodiment of the present invention, Fig. 2 is a block diagram of a D/A conversion device which is an embodiment of the present invention, and Fig. 3 is a block diagram conceptually showing an embodiment of the present invention. A diagram showing the waveforms of clock pulses input to the IAPH and signals generated by the MPU, Figure 4 shows an example of a digital pattern obtained by combining each waveform, and Figure 5 shows the relationship between the DAC and Ml. 6 is a main flowchart for D/A conversion according to the present invention, and FIG. 7 is a flowchart showing a D/A conversion subroutine. In the figure, 100.106...digital computer 102.
...Clock pulse generation circuit 104-@-match 110-1.110-2・e@filter.

Claims (3)

[Claims] (1) A digital computer that selects, synthesizes, and outputs a predetermined pulse signal according to input digital data from among a plurality of pulse signals with a predetermined pulse width and different periods, and a digital computer that selects and synthesizes a predetermined pulse signal and outputs the synthesized signal; the digital computer has a conversion means for converting the synthesized signal into an analog value; and an interrupt signal output means for outputting a signal for causing the digital computer to perform an interrupt process while the digital computer is executing a predetermined process; A digital-to-analog conversion device, characterized in that the predetermined pulse width is determined by: (2) The digital-to-analog converter according to claim 1, wherein the digital data is obtained through communication by the digital computer. (3) The digital-to-analog converter according to claim 1, wherein the digital computer has a plurality of ports for outputting the combined signal.