GB2155738A

GB2155738A - Linear interpolation circuit

Info

Publication number: GB2155738A
Application number: GB08505592A
Authority: GB
Inventors: Masahiro Kodama; Tatsuya Sakae; Yoshio Urano
Original assignee: Daikin Industries Ltd
Current assignee: Daikin Industries Ltd
Priority date: 1984-03-12
Filing date: 1985-03-05
Publication date: 1985-09-25
Also published as: GB8505592D0; GB2155738B; DE3508606A1; DE3508606C2; CA1239714A; JPS60191293A

Abstract

In a CRT display unit coordinates of start and end points P0, P1 of a line on the screen of the CRT are provided from a controller 11 and stored in a register 12. A line information calculating portion 13 calculates information necessary for linear interpolation based on the stored start and end point coordinates and the line segment information thus obtained is stored in a register 14. Based on the stored line segment information, a coordinates interpolating portion 15 calculates base line and supplement line data comprising a plurality of dots for constituting a straight line connecting the start and end points, which data are stored in a frame memory transfer register 16, A, B, C, prior to transfer to a frame memory. Thus, base and supplement line data are simultaneously transferred for linear interpolation and at the same time, information of the subsequent line segment is calculated so that the processing time for linear interpolation can be made short. <IMAGE>

Description

SPECIFICATION High Speed Linear Interpolation Circuit of CRT Display Unit Background of the Invention Field of the Invention The present invention relates to a high speed linear interpolation circuit of a CRT display unit.

More particularly, the present invention relates to a high speed linear interpolation circuit of a CRT display unit such as a raster scan type graphic display, in which coordinates of a start point and coordinates of an end point are specified and data of a straight line obtained by interpolation of these points is written in a frame memory.

Description of the Prior Art Figure 1 is a schematic block diagram of a conventional raster scan type graphic display unit.

First referring to Figure 1,the operation of a conventional raster scan type graphic display unit will be briefly described. Data is supplied from a host computer 1 to a pattern data control portion 3 through a transmission line and a host interface 2.

Upon receipt of the data from the host computer 1, the pattern data control portion 3 arranges the data in the form of a pattern to be displayed and the thus arranged data is stored in a segment buffer not shown. A data analytic portion 4 takes out the content of the segment buffer and analyzes the information so that vector calculation processing is applied based on the start point coordinates and the end point coordinates. Then, in case of applying extension, reduction, rotation, parallel movement or the like to a pattern, a coordinates conversion clip portion 5 multiplies the data by necessary matrices.

In addition, when a portion of a pattern on the screen of the CRT display unit is bounded by border lines, the other portions of the pattern protruding from the border lines are clipped off.

A DDA control paint portion 6 provides decomposed line segments existing insides the limits of the coordinates of the respective vertexes of each vector in case of painting out a pattern, whereby data for painting out is obtained. A DDA 7 is a straight-line generator, which calculates coordinates of intermediate points of a vector connecting the start point and the end pdint based on the data from the DDA control paint portion 6 and develops the result of calculation in a frame memory 8 to generate a straight line. The frame memory 8 stores dots on the straight line generated by the DDA 7. The data stored in the frame memory 8 is supplied to a video control portion 9, the data is converted into an analog signal by D/A conversion and is also converted into a video signal based on a color conversion table so as to be supplied to a color monitor 10.Thus, the color monitor 10 displays a pattern based on the data provided from the host computer 1.

Figs. 2 to 4 are illustrations for explaining a linear interpolation method by the DDA 7 in such a conventional color graphic display unit as shown in Fig. 1. Referring to Figs. 2 and 4, a method for representing a straight line by a conventional graphic display unit will be described. In a raster scan type graphic display unit, lines and surfaces are both structured by dots on the screen. These dots are represented by the brightness of horizontal scanning lines and as a result, if a line connecting the start point coordinates and the end point coordinates is to be represented as a slant line on the screen of the CRT display, such a slant line cannot be made smooth straight line, but is represented in the form having steps as shown in Fig. 2, which is known as the so-called jaggy phenomenon.In order to solve such a problem, a method called a brightness modulation system as indicated in Japanese Patent Laying-Open Gazette No.5598111983 or Japanese Patent Laying-Open Gazette No. 191687/1982 for example is conventionally utilized.

More specifically, as shown in Fig. 3, supplement lines are provided for the respective base lines of a line segment to correct the base lines. The brightness in the dots constituting the respective base lines and supplement lines is changed successively so that a smooth line as shown in Fig. 4 is represented.

Figs. 5 to 7 are illustrations for explaining a register utilized for linear interpolation by a conventional brightness modulation system. The frame memory 8 shown in Fig. 1 is generally structured by large capacity dynamic random access memories (hereinafter referred to as D RAM's). However, since the time required for coordinates interpolation by the DDA 7 considerably exceeds the access time by a D-RAM, writing of data from the DDA 7 into the frame memory 8 depends on the access time of the D-RAM. For this reason, at the time of writing data from the DDA 7 into the frame memory 8, access is applied simultaneously to a plurality of D-RAM's so that a plurality of dots of data are written in the D-RAM's, whereby loss due to the difference between the access time of a D-RAM and the time for coordinates interpolation by the DDA 7 can be prevented.More specifically, the DDA 7 includes registers each having a region for storing 4x2 dots, namely, 8 dots in all as shown in Fig. 5.

Data are successively written in the registers and the plurality of data written in the registers are addressed and written in the frame memory 8 by applying access to the D-RAM's at a time. The number of such registers is two for base line data.

While the content of one register is transferred to the frame memory 8, the DDA 7 writes interpolation data in the other register, and upon completion of the transfer of the data from the one register to the frame memory 8, the DDA 7 writes the data stored in the other register into the frame memory 8. Thus, by successively repeating the above described operation, transfer of data from the DDA 7 to the frame memory 8 is performed.

In case where linear interpolation is applied as described above by brightness modulation using the DDA 7 in a conventional color graphic display unit, four transfer registers are required for transfer of data to the frame memory 8 since a straight line is represented by using base line data and supplement line data. Moreover, since the base line data and the supplement line data are alternately transferred, the time twice as much is required for transfer as compared with a case in which brightness modulation is not applied, and accordingly, the processing time becomes long.In addition, since length, inclination, increasing direction and other data of a line segment need be calculated after the start point coordinates and the end point coordinates are provided, interpolation of one straight line requires not only the time for transfer of the interpolated value to the frame memory 8 but also the time for calculation of the inclination and other data, which further extends the processing time. Furthermore, although the base line register and the supplement line register both comprise regions for storing 4x2 dots as shown in Fig. 7, the data which can be written in one register is 4 dots at the maximum and accordingly the remaining 4 dots are not used, as is undesirable from the viewpoint of efficiency.

Summary of the Invention Therefore, a primary object of the present invention is to provide a high-speed linear interpolation circuit of a CRT display unit in which base line data and supplement line data are simultaneously transferred for linear interpolation and at the same time, information of the subsequent line segment is calculated so that the processing time for linear interpolation can be shortened.

Briefly stated, in the present invention, control is performed in the following manner. Coordinates of a start point and coordinates of an end point are provided and based on these start point coordinates and end point coordinates, line segment information necessaryfor linear interpolation is calculated. Then, based on the calculated line segment information, base line data and supplement line data comprising a plurality of dots for constituting a straight line connecting the start point coordinates and the end point coordinates are calculated and provided as output.Of these base line data and supplement line data, a predetermined number of dots are stored in a register and after that, predetermined numbers of base line data and supplement line data are successively stored in other registers and at the same time, the content of the register where storing is completed is transferred to a frame memory.

Consequently, according to the present invention, the number of registers for storing base line data and supplement line data to be transferred to a frame memory can be decreased and on the other hand, the amount of base line data and supplement line data to be transferred at a time can be increased. As a result, the data transfer speed can be noticeably improved.

These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Brief Description of the Drawings Fig. 1 is a schematic block diagram of a conventional color graphic display unit.

Fig. 2 is an illustration for explaining a linear interpolation method by a DDA in a conventional color graphic display unit.

Fig. 3 is an illustration showing an example of display in which a line segment is composed of base lines and supplement lines.

Fig. 4 is an illustration showing an example of a line segment displayed by a conventional brightness modulation system.

Figs. 5, 6 and 7 are illustrations showing registers utilized for interpolation of a line segment by a conventional brightness modulation system.

Fig. 8 is a schematic block diagram of an embodiment of the present invention.

Fig. 9 is an illustration showing an example of a line segment the inclination of which is calculated by a line information calculating portion.

Fig. 10 is an illustration showing an example of A to C registers where base line data and supplement line data of the line segment shown in Fig. 9 are stored.

Fig. 1 1Ato 1 1D are flow charts for explaining the operation of a coordinates interpolating portion shown in Fig. 8.

Fig. 12 is an illustration showing an example of base line data and supplement line data to be stored in a transfer register shown in Fig. 8.

Fig. 13 is a diagram for explaining the input conditions of the A two C registers shown in Figs. 1 1A to 11D.

Fig. 14 is an illustration for explaining the process for transferring the data of the A two C registers.

Description of the Preferred Embodiment Fig. 8 is a schematic block diagram of an embodiment of the present invention. First, referring to Fig. 8, the structure of an embodiment of the present invention will be described. A controller 11 provides start point coordinates P0 (X0, Y0) and end point coordinates P1 (X1, Y, ) of a line segment to a start point coordinates and end point coordinates register 12. The start point coordinates and end point coordinates register 12 stores the thus provided start point coordinates P0 (X0, Y0) and end point coordinates P1 (X1, Y1) and supplies these coordinates data to a line information calculating portion 13. The line information calculating portion 13 is structured by a microcomputer for example and calculates an inclination necessary for interpolating a straight line based on the supplied start point coordinates P0 (X0, Y0) and end point coordinates P1 (X1, Y1). The calculated inclination of a line segment is stored in a line segment register 14. A coordinates interpolating portion 15, which is structured by a microcomputer for example, interpolates a straight line connecting the start point coordinates P0 (X0, Y0) and the end point coordinates P1 (X1, Y1) based on the inclination data of a line segment and supplies base line data and supplement line data to a frame memory transfer register 16.The frame memory transfer register 16 comprises an A register, a B register and a C register, so that these registers store a predetermined number of dots out of a plurality of dots constituting the base line data and a predetermined number of dots out of a plurality of dots constituting the supplement line data and these stored dots are transferred to a frame memory 8 as described above with reference to Fig. 1.

Fig. 9 is an illustration showing an example of a line segment the inclination of which is calculated by a line information calculating portion; Fig. 10 is an illustration showing an example of Ato C registers where base line data and supplement line data of the line segment shown in Fig. 9 are stored; Figs. 1 1A to 11 Dare flow charts for explaining the operation of a coordinates interpolating portion shown in Fig. 8; Fig. 12 is an illustration showing an example of base line data and supplement line data stored in the A to C registers;Fig. 13 is an illustration for explaining the input conditions of the Ato C registers shown in Fig. 12; and Fig. 14 is an illustration for explaining the operation in case of transferring the base line data and supplement line data stored in the A to C registers.

Referring Figs. to 14, a concrete operation of an embodiment of the present invention will be now described. First, the controller 11 stores the start point coordinates P0 (XO, YO) and the end point coordinates P1 (X1, Y1) in the start point coordinates and end point coordinates register 12. The line information calculating portion 13 calculates an inclination of a line segment POP1 shown in Fig. 9 based on the respective coordinates stored in the start point coordinates and end point coordinates register 12.

More specifically, the line information calculating portion 13 sets an XSIGN flag to "1" in the case of X1-X0 > O and an X address counter (not shown) included in the line information calculating portion 13 is made to count up in this case. On the contrary, in the case of X0-X1 < O, the XSIGN flag is set to "0" and the X address counter is made to count down. If the Y component of the line segment POP1 is Y1-Y0 > O, a YSIGN flag is set to "1" and a Y address counter (not shown) in the line information calculating portion 13 is made to count up. On the contrary, if the Y component is Y1 -Y0 < O, the YSlGN flag is set to "0" and the Y address counter is made to count down.The inclination of the line segment P0P1 is calculated by a ratio of a differences / aX t in the X component and a difference I AY s in the Y component in the start point coordinates P0 (XO, Y0) and the end point coordinates P1 (X1,Y1).

Then, in the case of lX1-Xol~lY1-Yolt an XMAJOR flag is set to "1". In this case, the count of the X address counter increments or decrements by 1 successively for each dot and the Y address counter takes an integral part out of the inclination with + signs.

In the case of X1-X0 < j Y1-Y0 the XMAJOR flag is set to "0" and in this case, the X address counter takes an integral part out of the inclination with + signs and the count of the Y address counter increments or decrements by 1 successively for each dot.

In order to facilitate the understanding of the above described operation, a concrete description will be made with reference to Fig. 10. If a line segment is formed with the conditions of / nx 1=12 and I SY l=3, the inclination is 1/4. Accordingly, in the example shown in Fig. 10, the count of the X address counter increments by +1 for each dot, while the Y address counter counts up each time the X address counter counts 4. Thus, each time 4 dots in the X direction are counted, the address counter in the Y direction counts up by 1 and accordingly, the line segment can be represented by the calculated inclination.

The line segment information thus obtained, namely, the inclination, the XMAJOR flag and other data are stored in the line segment register 14. Then, the coordinates interpolating portion 15 applies linear interpolation based on the line segment information stored in the line segment register 14.

Now, referring to Figs. 11 A to 14, the operation of the coordinates interpolating portion 15 will be described. The coordinates interpolating portion 15 interpolates a line segment POP1 based on the line segment information stored in the line segment register 14 so that base line data and supplement line data as shown in Fig. 12 for example are obtained. Then, these base line data and supplement line data are respectively divided into groups of 4 dots in a horizontal direction so that 4 dots of base line data and 4 dots of supplement line data thus divided are transferred to the frame memory transfer register 16. The frame memory transfer register 16 comprises an A register, a B register and a C register.

Then, in the step SP1 shown in Fig. 1 1A to 11 D (referred to simply as SP1 in the drawing), it is determined whether or not 4 dots of base line data and 4 dots of supplement line data can be stored in the same register. If the data can be stored in the same register, it is determined in the step SP2 whether or not the data can be written in the A register. In the example shown in Fig. 12,4dotsof base line data and 4 dots of supplement line data can be written in one register and accordingly in the step SP3, the first dot of base line data and the associated first dot of supplement line data are stored in the A register. In the step SP4, it is determined whether or not interpolation of the line segment by the DDA is completed. If the interpolation is not completed, it is determined in the step SP5 whether or not 4 dots of base line data are stored in the A register and overflow occurs if more dots of base line data are stored. However, since only the first dot of base line data is stored in the A register, it is determined that overflow does not occur, and in the step SP6, it is determined whether or not the supplement line data overflows.

If the supplement line data does not overflow, the program returns to the step SP3. In the step SP3, the second dot of base line data and the second dot of supplement line data are stored in the A register.

The above described operation is repeated so that 4 dots of base line data and 4 dots of supplement line data are successively stored in the A register.

When 4 dots of base line data and 4 dots of supplement line data are stored in the A register, it is determined in the step SP5 whether the base line data in the A register overflows and it is determined in the step SP7 that the supplement line data in the A register overflows as well. Then, in the step SP8, the base line data and the supplement line data stored in the A register are transferred to the frame memory 8.

In case of storing the fifth base line data and fifth supplement line data in a register, it is determined again in the step SP1 whether or not the dots can be stored in the same register. If it is determined that the dots can be stored in the same register, it is determined in the step SP2 whether or not the dots can be written in the A register. At this time, the above mentioned base line data and supplement line data are stored in the A register and are being transferred to the frame memory 8 and accordingly, it is determined that the fifth base line data cannot be written in the A register. Subsequently in the step SP9, it is determined whether or not the fifth base line data can be written in the B register.If it is determined that the fifth base line data can be written in the B register, the fifth base line data is stored in the B register in the step SP10 and thus the fifth to eighth base line data are stored in the B register. Then in the step SP11, it is determined that interpolation of the line segment by the DDA is not completed and in the step SP12, it is determined that the base line data in the B register does not overflow.

Subsequently, when it is determined in the step SP13 that the supplement line data in the B register overflows, it is determined in the step SP14whether or not the supplement line data can be written in the C register. If the supplement line data can be written in the C register, in the step SP15, the base line data is stored in the B register and the supplement line data is stored in the C register. Then, in the step SP16, it is determined that interpolation of the line segment by the DDA is not completed and it is determined in the step SP17 whether or not the base line data overflows. If overflow occurs, the data stored in the B register is transferred to the frame memory 8 in the step SP19.Subsequently if it is determined in the step SP20 that the supplement line data overflows, the supplement line data stored in the C register is transferred to the frame memory 8 in the step SP21.

Subsequently, in case of transferring the ninth to twelfth base line data and supplement line data, it is determined in the step SP1 that these data cannot be stored in the same register and in the step SP22, it is determined whether or not these data can be written in the A register. If the data can be written in the A register, it is determined in the step SP23 whether or not the data can be written also in the B register. If the data can also be written in the B register, the ninth and the tenth base line data are stored in the A register in the step SP24 and the corresponding dots of supplement line data are stored in the B register. Then, in the step SP25, it is determined whether or not interpolation of the line segment by the DDA is completed and if not, it is determined in the step SP26 that the base line data in the A register overflows.Subsequently, in the step SP27, the base line data stored in the A register is transferred.

In the step SP28, it is determined whether or not the supplement line data overflows and if not, it is determined in the step SP29 whether or not the base line data and the supplement line data can be stored in the same register. If the data can be stored in the same register, the eleventh and the twelfth base line data and supplement line data are respectively stored in the B register and in the step SP31, it is determined that interpolation of the line segment by the DDA is not completed. Subsequently, if it is determined in the step SP32 that the base line data in the B register overflows and if it is determined in the step SP33 that the supplement line data in the B register overflows, the base line data and the supplement line data stored in the B register are respectively transferred to the frame memory 8 in the step SP34.Even if overflow does not occur, the data are transferred to the frame memory 8 when it is determined in the step SP31 that interpolation of the line segment is completed.

The conditions of control of the A to C registers for transfer of the 12 dots of base line data and supplement line data to the frame memory 8 through the Ato C registers are as shown in Fig. 13.

In Fig. 13, NOVF with the numeral "1" indicates overflow of base line data in the register and COVF indicates with the numeral "1" overflow of supplement line data in the register. NWRL and NWRM indicate reigsters where base line data is stored. In this case, "00" means the A register; "01", means the B register; and "10", means the C register. CWRL and CWRM indicate registers where supplement line data are stored, in the same manner as in case of NWRL and NWRM. AFULLwith "1" indicates a state where the data written in the A register overflows and the transfer to the frame memory 8 is not completed. In other words, the numeral "0" of AFULL indicates a state where data can be written in the A register. BFULL and CFUFLL have the same meaning as in AFULL.DIFF with "1" indicates the condition where base line data and supplement line data cannot be written in the same register. The output value W indicates a state waiting for the data to be able to be written in a register after completion of transfer to the frame memory 8 since none of the registers can receive the newly applied data at present. In this waiting state, the operation of the DDA is stopped.

The base line data and the supplement line data respectively stored in the A to C registers are transferred as the data of 8x1 dots with respectto the content of 4x2 dots as shown in Fig. 14. As a result, the number of dots of data transferred by one access to the frame memory 8 can be increased from 4 to 8 and accordingly the writing speed can be made fast.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

1. A high-speed linear interpolation circuit of a raster scan type CRT display unit comprising: a frame memory for storing data to be displayed on the screen of a CRT display unit (8), start point coordinates and end point coordinates providing means for providing data representing coordinates of a start point and coordinates of an end point on said screen of said CRT display unit (11), line segment information calculating means for calculating line segment information necessary for linear interpolation based on said data representing said start point coordinates and said end point coordinates provided from said start point coordinates and end point coordinates providing means (13), linear interpolation means for calculating, based on said line segment information calculated by said line segment information calculating means, base line data comprising a plurality of dots for constituting a straight line connecting said start point coordinates and said end point coordinates and supplement line data comprising a plurality of dots corresponding to the respective dots of said base line data for correction of said base line data, so that said base line data and said supplement line data calculated are provided as output (15), a plurality of registers comprising regions for storing a predetermined number of dots of said base line data and a predetermined number of dots of said supplement line data corresponiding thereto (16), and control means in which a predetermined number of dots of said base line data and said supplement line data provided from said linear interpolation means are stored in any one of said plurality of registers and subsequently, predetermined numbers of base line data and supplement line data are successively stored in other registers and simultaneously the content of the register where storing is completed is transferred to said frame memory (15).

2. A high-speed linear interpolation circuit of a CRT display unit in accordance with claim 1, further comprising a start point and end point coordinates storing register for storing said data representing said start point coordinates and said end point coordinates provided from said start point and end point coordinates providing means (12), said line segment information calculating means comprising means for calculating said line segment information based on said data representing said start point coordinates and said end point coordinates stored in said start point and end point coordinates storing register (13).

3. A high-speed linear interpolation circuit of a CRT display unit in accordance with claim 1, further comprising line segment information storing register for storing said line segment information calculated by said line segment information calculating means (14), said linear interpolation means comprising means for calculating said base line data and said supplement line data based on said line segment information stored in said line segment information storing register(13).