JPS59834B2 - Straight line generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a straight line generation circuit for a display device configured with a digital image memory, and in particular, it distributes brightness to a pair of pixels in accordance with the slope of a straight line, and generates a straight line when displaying a line drawing on a digital display. The present invention relates to a linear generation circuit with a display brightness modulation circuit for preventing stepwise waveforms occurring in a display.

Conventionally, in raster scan displays, when displaying line drawings, pixels can only be displayed on a raster, so it is difficult to move from a point on a raster to a point on the next raster, especially on a straight line with a gentle slope. As a result, the straight line becomes stepwise and the connections between rasters are broken, making it difficult to draw a smooth straight line.

The present invention has been made to solve the above-mentioned problems, and it displays one pixel at the same time as a plurality of points, and distributes a predetermined brightness to each of the points corresponding to the slope of the straight line, thereby displaying the stepwise display. It is an object of the present invention to provide a straight line generation circuit which can be used as a line drawing display even on a raster scan monitor. The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a straight line generation circuit (hereinafter referred to as DDA) according to the present invention, where 1 is a SLOPE register, 2 is an adder, and 3 is a SLOPE register.
is a register, 4 is an X counter, 5 is a Y counter, 6 is an M
AJOR counter, T is SIGN register, 8 is memory, 9 is Y+1 counter, 10 is X+1 counter, and counters 9 and 10 (coordinate output circuit) together with MAJOR counter 6, SIGN register 7, and memory 8 form a display brightness modulation circuit. It consists of Next, the operation will be explained.

When interpolating between two points on a straight line, Δ5=(M1N0RPA
Slope △S calculated by RT)/(MAJORPART)
is set in SLOPE register 1. Therefore point Xo
, the slope △S of the straight line from Yo to points X1 and Y1 is △5=△Y/△X, and this △S
is set. Here △Y=Y1-Yb△X=X1-
It is X0. Adder 2 and register 3, along with SLOPE register 1, are part of the DDA decimal point operation section (FUNCTIO).
one NALPART).

△X is set in the MAJOR counter 6, and the clock increments the X counter 4 until △X becomes zero, and then Y
The counter 5 increments every time the adder 2 outputs a carry.
The upper bits of the adder 2 become the address of the memory 8, and the SIGN register 7 contains SIGN(△X),
SIGN(ΔY) data are set and these are also given as addresses in memory 8. Y+1 counter 9,
The X+1 counter 10 is a coordinate output circuit in which a value obtained by counting up one address from the true coordinate point of the DDA is set.

However, only MINORPART counts up, and in this embodiment, only Y+1 counter 9 is incremented by one address from the true value (Y counter 5). Using these plural counters, the DDA simultaneously generates coordinate values of two points (including a point advanced by 1 bit on the MINOR axis). FIG. 2a shows the decimal point calculation section of the DDA according to the present invention, and FIG. 2b shows the output signal of the adder 2A for each step. Of the output signals of the adder 2A, Σ3 and Σ2 serve as address signals for the memory 8. That is, Σ represents 1/16, 1/8, 1/4, and 1/2, respectively. , Σ1, Σ2, Σ3, only the upper two bits are sent to the memory 8. This address signal (output signals Σ2, Σ3) represents the position of the coordinate value with respect to adjacent pixels sandwiching the coordinate value. Therefore, the brightness of the pixel is modulated according to the contents of the memory 8 depending on the degree of proximity of the coordinate value to the pixel, and in this case, 2-bit (4-step) brightness modulation is applied.
In other words, the signal output to memory 8 is 1 bit (Σ3
), two-stage brightness modulation can be obtained;
It goes without saying that by using the output signals of bits Σ1, Σ2, and Σ3, brightness modulation with better resolution accuracy than in this embodiment can be obtained, and these can be done arbitrarily as required.

In this embodiment, an example in which the SLOPE register 1 has 4-bit input terminals A, B, C, and D will be explained, but in practice, the SLOPE register 1 may have a larger number of bits and a combination of these terminals. Of course, inputs corresponding to all slopes (below the decimal point) can be obtained.

Now, the slope of the straight line with the X axis as MAJOR (long axis) is 1.
/4 will be explained as an example.

The data of step 1 in FIG. 2b is set in the SLOPE register 1A, and the data of step 1 is outputted to the adder 2A. As the MAJOR counter 6 increments, the steps advance, and the output signals of steps 2 to 5 change from Σ0 to C4 until the MAJOR counter 6 reaches zero.
repeated. Here, only Σ2 and Σ3 are considered.

FIG. 3 shows the relationship between the output signal of the adder 2A and the display straight line, and S1 to S indicate steps 1 to 5, respectively. That is, when the carry C4 becomes "1", the Y counter 5 increments by 1 bit, and the step at this time is 4 (S4). Also, Y+1 counter 9 is Y
The counter 5 is incremented by one address, and the DDA of FIG. 1 also generates coordinate points shown by broken lines in FIG. 4 with respect to the display straight line shown in FIG. By distributing the luminance of each pixel with respect to the broken line coordinate points in FIG. 4 as shown by the numbers in the circles in FIG. 5, the gradual broken shape can be made into a smooth display straight line. In FIG. 5, the numbers inside the circles indicate the relative magnitude of brightness. On the other hand, the magnitude of the brightness shown in FIG. 5 corresponds to the output signal of the adder 2A in FIG. By setting brightness data in the memory 8 as an address, a predetermined brightness is output in response to the advancement of the DDA step. In FIG. 1, the brightness output Bφ of the memory 8 is for the true coordinate point indicated by the X counter 4 and Y counter 5 of the DDA, B1 is the value of the Y+1 counter 9,
This is for the additional points shown in the X+1 counter 10. On the other hand, in FIG. 1, the SIGN register 7 is set with data indicating the direction to the next coordinate point.

If the luminance distribution shown in FIG. 5 and the output signal of adder 2 are fixed, D
DA decimal point operation part (FUNCTIONAL PART)
The output of the adder 2A and the luminance result in the results shown in FIGS. 7a-d. As is clear from FIG. 7, only directions A and B shown in A and d are correct as brightness distributions, but B,
There is no continuous brightness distribution in the C and D directions shown in c.

Therefore, in order to make these appropriate brightness distributions, SIG
Using the N register 7, find the difference between the coordinate values of the next point and the previous coordinate point, use the sign as direction data, and use this as address data in the memory 8. By setting brightness data in the memory 8 in advance, a brightness distribution depending on the direction is set. In the embodiment of the present invention, the X+1 counter or Y+
We have explained the case where one address is counted up against the X counter or Y counter using one counter, but
X. It goes without saying that an adder or the like that counts down or counts up by one address or more may be used for each counter of Y, and the same effect can be used without departing from the scope of the present invention.

As described above, according to the present invention, the linear generation circuit (DDA
) as X, . At least 1 for one of the Y counters
A coordinate output circuit before and after the address is provided, and the direction of the straight line and at least one bit of the decimal arithmetic unit are outputted from X. Since the configuration uses a taste play brightness modulation circuit that provides brightness information for each coordinate point of the Y counter and coordinate output circuit, compared to conventional DDA, it can be visually improved at low cost without adding any circuits. It is possible to realize a display that does not have any level differences, and its effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 a is the decimal number shown in FIG. 1. A concrete block diagram showing the arithmetic unit, FIG. 2b is an explanatory diagram showing the output signal of the adder in FIG. 2a, FIG. 3 is an explanatory diagram showing the display straight line by conventional DDAVC, The figure is an explanatory diagram showing the display straight line by the DDA of the present invention, Fig. 6 is an explanatory diagram showing the inclination direction of the straight line, and Fig. 7 A, b, c, and d are the display straight lines when straight line direction data are not used. FIG. 1...SLOPE register,...adder, 3... ．． ．． Register, 4...X counter, 5...Y counter, 6...MA
JOR counter, 7...SIGN register, 8
...Memory, 9...Y+1 counter, 10...X+1 counter.

Claims (1)

[Claims] 1. In a straight line generation circuit of a display device configured with a digital image memory, an a decimal point calculation unit consisting of a SIGN register for outputting, a SLOPE register for outputting a signal below the decimal point of the slope of the straight line for each step, and an adder for adding the slope output for each step; and at least one of the decimal point calculation units. A straight line comprising a memory having address inputs of a bit and the output of the SIGN register, the output of the memory being luminance information for each coordinate point of the X and Y counters and the coordinate output circuit. generation circuit.