GB2143372A - Applying barrier metal to a semiconductor - Google Patents
Applying barrier metal to a semiconductor Download PDFInfo
- Publication number
- GB2143372A GB2143372A GB8415370A GB8415370A GB2143372A GB 2143372 A GB2143372 A GB 2143372A GB 8415370 A GB8415370 A GB 8415370A GB 8415370 A GB8415370 A GB 8415370A GB 2143372 A GB2143372 A GB 2143372A
- Authority
- GB
- United Kingdom
- Prior art keywords
- contact window
- layer
- type silicon
- titanium
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
A titanium-tungsten (T2-W) barrier layer (70) is provided between a signal line and an N-type silicon region in a NPN transistor device having an emitter contact window (62) exposed to N-type silicon, a collector contact window (60) exposed to N-type silicon and a further contact window (64) having a layer (35, Fig. 7) of silicon dioxide over P-type silicon, by depositing a layer (70) of an alloy of titanium-tungsten on the surface of the processed semiconductor wafer and etching the titanium-tungsten layer out of the further contact window (64). The silicon dioxide layer (35, Fig. 7) is then etched out of the further contact window to expose the P-type silicon. A metallisation layer of aluminium is then deposited on the semiconductor wafer and undesired portions are etched away using conductor interconnect photolithography to define signal lines (100, 102, 104). Those portions of the titanium-tungsten layer not covered by the signal lines are etched away so that the titanium-tungsten layer provides barrier metal between the signal lines and the N-type silicon of the emitter and collector contact windows so that the signal lines connect directly to the further contact window. Alternatively the titanium-tungsten layer remains only in the emitter contact window. <IMAGE>
Description
SPECIFICATION
Method of selectively applying barrier metal to a surface of a NPN-type semiconductor wafer and to a
NPN semiconductor device
This invention relates to methods of selectively applying barrier metal to surfaces of NPN-type semiconductor wafers and to NPN semiconductor devices.
One of the difficulties of obtaining high yields of bipolar LSI and VLSI integrated circuits is in obtaining good quality thin films for the standard two or more layer metallisation schemes. One of the most serious problems has to do with making sure that these films are able adequately to cover topographical steps on the surface of a silicon wafer and maintain integrity as they do so. By far, the metal element most commonly used in the semi-conductor industry for metal interconnects is aluminium. Unfortunately, aluminium has an affinity for silicon during sintering which results in aluminium signal lines pitting through and shorting out shallow junctioned bipolar devices. This is particularly a problem for the shallow junction emitters of NPN devices. The answer to this problem has been to utilize aluminium alloys containing silicon.While this solves the pitting problem, it causes difficulties with thin film coverage. When the aluminium/silicon layer has been etched to define the metallisation interconnect pattern, the silicon in the alloy is left behind in the form of small nodules. These nodules serve as nucleation centres during subsequent dielectric chemical vapour deposition and produce a very rough surface and even bulbs at steps, resulting in a surface which is very difficult to cover with another layer of metal.
A solution to this problem has been to use non-silicon containing alloys of aluminium together with a barrier metal between the aluminium and the silicon to prevent alloy pitting. A very good candidate for this barrier metal is titanium-tungsten alloy.
Unfortunately, titanium-tungsten makes good ohmic contact to N-type silicon but not to P-type. Past processes utilizing titanium-tungsten alloy have, therefore, necessitated the use of an extra photolithographic masking operation, making the process more complex and costly. That is, in the past a layer of titanium-tungsten alloy had to be defined by photolithographic means and then etched from the
P-type silicon contact windows prior to depositing the aluminium and metallisation layer.
The present invention seeks to avoid the problems of the prior art methods by eliminating the extra photolithographic etching step previously required to pattern the titanium-tungsten layer.
Although the present invention is primarily directed to any novel integer or step, or combination of integers or steps, herein disclosed and/or as shown in the accompanying drawings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided a method of selectively applying barrier metal to a surface of a
NPN semiconductor wafer, comprising the steps of: processing the semiconductor wafer to produce a
NPN transistor device having an emitter contact window exposed to N-type silicon, a collector contact window exposed to N-type silicon, and a further contact window having therein a layer of silicon dioxide over P-type silicon; depositing a layer of an alloy of titanium-tungsten on the surface of the processed semiconductor wafer; etching the titanium-tungsten layer out of the further contact window; etching the silicon dioxide layer out of the further contact window to expose the P-type silicon; depositing a metallisation layer of aluminium on the semiconductor wafer; using conductor interconnect photolithography to etch away undesired portions of the metallisation layer to define signal lines; and etching away those portions of the titaniumtungsten layer not covered by the signal lines so that the titanium-tungsten layer provides barrier metal between the signal lines and the N-type silicon of the emitter and collector contact windows, and so that the signal lines connect directly to the further contact window.
A washed emitter process may be used to produce said NPN transistor device.
Said further contact window may be a base contact window.
According to a further non-restrictive aspect of the present invention there is provided a method of selectively applying barrier metal to a surface of a
NPN-type semiconductor wafer, comprising the steps of: processing the semiconductor wafer to produce a NPN transistor device having an emitter contact window exposed to N-type silicon, a collector contact window exposed to N-type silicon, and a further contact window having therein a layer of silicon dioxide over P-type silicon; exposing said further contact window to P-type silicon by etching said silicon dioxide layer; depositing a layer of an alloy of titanium-tungsten on the surface of the semiconductor wafer; patterningthetitanium- tungsten layer by photolithography so that the titanium-tungsten remains in the emitter contact window only; depositing a metallisation layer of aluminium onto the semiconductor wafer; and using conductor interconnect photolithography to etch away undesired portions of the metallisation layer to define signal lines, so that the titanium-tungsten layer provides barrier metal between said signal lines and the N-type silicon of the emitter contact window and so that said signal lines connect directly to the further contact window and the collector contact window.
According to another non-restrictive aspect of the present invention there is provided a NPN semiconductor device having N-type silicon collector and emitter contact windows and a P-type silicon base contact window, comprising: an aluminium signal line directly contacting the N-type silicon in the collector contact window; a barrier metal titaniumtungsten layer directly contacting the N-type silicon in said emitter contact window; aluminium signal line directly contacting said titanium-tungsten layer in said emitter contact window; and an aluminium signal line directly contacting said P-type silicon of said base contact window, the arrangement being such that said barrier metal separates said aluminium signal lines from the N-type silicon in said emitter contact window only.
The invention is illustrated, merely by way of example, in the accompanying drawings, in which:
Figure I shows an elevational view of a portion of an epitaxial layer of a semiconductor wafer at an early step in a method according to the present invention of selectively applying barrier metal to a surface of a NPN semiconductor wafer;
Figure 2 shows a plan view of the wafer of Figure 1 with a mask superimposed thereupon;
Figures3to 6showthe manner by which a NPN semiconductor device having a washed emitter structure is produced;
Figures 7to 9 are elevational views of a semiconductor wafer during successive stages of a first embodiment according to the present invention of selectively applying barrier metal to a surface of a
NPN semiconductor wafer;;
Figures 10 to 13 are elevational views of a semiconductor wafer during successive stages of a second embodiment of a method according to the present invention of selectively applying barrier metal to a surface of a NPN-type semiconductor wafer.
In a presently preferred embodiment of a method according to the present invention of selectively applying barrier metal to a surface of a NPN-type semiconductor wafer, a silicon wafer first undergoes a washed emitter process in order to produce a device having an N-type silicon emitter and collector contact windows exposed to the bare silicon and a contact window having therein a layer of silicon dioxide over P-type silicon. This washed emitter process will be described first.
A portion of an N-type silicon epitaxial layer 10 of the silicon wafer to be processed is shown in Figure 1. The portion of the epitaxial layer 10 shown in
Figure 1 will be processed into an NPN transistor device. Obviously, while only one NPN transistor device is shown and described, the method is being simultaneously carried out on many like NPN devices. Moreover, not only can NPN transistors be overlaid with signal lines and barrier metal using a method according to the present invention, but in addition, the P-type contact windows isolated and protected from barrier metal by the method are not exclusively base contact windows, but could also be
P-type contact windows for resistors or diodes, for example.
To apply the washed emitter process to the epitaxial layer 10 shown in Figure 1, the wafer is first placed in a furnace tube in the presence of oxygen gas to grow a layer of silicon dioxide 12 on the surface of the expitaxial layer 10. According to conventional photolithography, the silicon dioxide layer 12 is first covered with a layer of photoresist 14
Ultraviolet light is projected onto the photoresist layer 14 through an opening 22 of the mask (see
Figure 2). The portion of the photoresist layer 14 exposed through the opening 22 is then removed using a developerto expose the silicon dioxide layer 12. This exposed portion of the silicon dioxide layer 12 is then etched down to the bare silicon using a wet chemical etch. The remaining portion of the photoresist layer 14 is then removed.The opening 22 has defined what will now become the base region of one NPN transistor device on the epitaxial layer 10. The wafer is then placed in a predeposition tube and a P-type dopant (boron) passed down the tube and is deposited onto the wafer. The wafer is then placed in a second tube which contains oxygen and'or steam which dries the boron dopant into the epitaxial layer 10, where the bare silicon has been exposed, to form a P-type base region 25 (Figure 3).
This is the drive-in step. The silicon dioxide layer 12 shields the other portions of the epitaxial layer 10 from the dopant. A new layer of silicon dioxide 28 is grown across the surface of the wafer as a consequence of the drive-in step.
Next, a mask 30 (Figure 4) having an opening 32 is used to etch away the silicon dioxide layer 28 to expose a portion of the base region 25 to the bare silicon again. The two step doping process just described is repeated to dope more heavily this isolated portion of the base region 25 and thereby form a base contact region 27. Again, a new layer of silicon dioxide 35 is grown during the drive-in step.
Next, a silicon nitride layer 37 is deposited across the wafer using a standard low pressure chemical vapour deposition technique. A photolithographic mask 40 having openings 42a, 44a, 46a is used to etch corresponding windows 42b, 44b, 46b in the silicon nitride layer 37 (Figure 5). A mask 50 (Figure 6) having oversized openings 52a, 54a is then used to select the corresponding windows 42b, 44b, which were etched in the previous step. These windows 42b, 44b, delineate what will become the
NPN collector and emitter contact regions, respectively. The silicon dioxide layers 12, 38, 35 are then etched to form the windows 52b, 54b as shown in
Figure 6.Note that the actual etched windows 52b, 54b correspond to the patterns defined by windows 42b, 44b and not by the oversized windows 52a, 54a.
The etch ant used for silicon dioxide does not significantly etch the silicon nitride layer 37. Hence, the windows 52a, 54a can be oversized to eliminate the problems of imprecise alignment between the windows of the mask 50 and the windows 42b, 44b of the silicon nitride layer 37.
Now, it is necessary to dope the silicon exposed in the windows 52b, 54b with a N-type dopant to form the collector and emitter contact regions of the NPN transistor device. In a washed emitter process, this is
done by minimising the amount of silicon dioxide which is grown during the diffusion of the N-type
dopant into the epitaxial layer 10. The wafter (as
shown in Figure 6) is placed in a doping tube and a
N-type dopant such as phosphorous is deposited onto the silicon in the windows 52b, 54b. This is analogous to the predeposition step of the conventional two step process. To avoid the growth of
another layer of silicon dioxide, a drive-in step does
not follow, but instead, the predeposition step is
relied upon alone to diffuse the N-type dopant into the silicon to the necessary extent to form a collector
contact window 60 and an emitter contact window
62. Actually, a very thin layer of silicon dioxide is
unavoidably grown on the wafer as a result of the predeposition step alone. This thin layer can, however, be "washed" (actually etched) away using a nonmasked wet chemical etch. Hence, the terminology washed emitter process'. Figure 6 shown the
NPN transistor device produced by this well known process having the collector and emitter contact windows 60,62 exposed to bare silicon, while a base contact window underlying the window 46b is covered by the silicon dioxide layer 35.
Now, according to a first embodiment of the present invention illustrated in Figures 7 to 9, a layer 70 of titanium-tungsten alloy is sputtered across the surface of the wafer. The titanium-tungsten layer 70 makes direct contact with the silicon in the collector and emitter contact windows 60, 62 and with the silicon dioxide layer 35 overlying the base contact window. P-type silicon contact photolithography is performed using a mask 80 having an opening 82 to etch away a corresponding portion 74 of the titanium-tungsten layer 70. A window 36 is then etched in the silicon dioxide layer 35 to expose the base contact window 64 in the base contact region 27 to bare silicon. A first layer 90 of aluminium metallisation is deposited across the wafer (Figure 8).The first layer 90 is then patterned usig interconnect photolithography and portions 92,84, 96,98 thereof are etched away to produce signal lines 100,102,104.
Those remaining portions of the titanium-tungsten layer 70 which are not covered by the signal lines 100, 102 are etched away using the signal lines which are covered with photoresist as a mask. The remaining photoresist is then removed. Note that the photoresist could be removed before etching the titanium-tungsten layer in that the etchant used for titanium-tungsten will not etch aluminium. The remaining portions of the silicon dioxide layers 12, 28,35 and the silicon nitride layer 37 are left untouched in the normal fashion. The resulting structure is shown in Figure 9 wherein the titaniumtungsten layer 70 provides a barrier between the signal lines 100, 102 and the silicon in the N-type collector and emitter contact windows 60,62 but not in the P-type silicon base contact window 64.
Consequently, no extra photolithographic step is necessary to define the titanium-tungsten layer 70 since it is initially removed from the base contact window 64 when the silicon dioxide layer is moved and later etched using the signal lines as a mask.
Shallow junction bipolar structures can, therefore, be protected without introducing silicon nodules.
Barrier metal can be put in the N-type silicon contact windows, but not in the P-type silicon contact windows, without significantly adding complexity to the manufacturing process. One metal deposition and two non-critical etching steps have been added in place of an extra photolithographic masking operation.
An alternative embodiment of the present invention is shown in Figures 10 to 13. According to this method, and starting with the washed emitter structure shown in Figure 6, a mask 120 having an opening 122 is used to open up the base contact window 64 (and all other P-type contact windows on the wafer) by removing the exposed portion of the silicon dioxide layer 35 (Figure 10). A titaniumtungsten layer 70A is deposited across the entire wafer 10. A mask 130, having openings 132, 134 is used to etch away portions 72A, 74A of the titaniumtungsten layer 70A so that the latter remains in the
N-type silicon emitter contact windows only (see
Figure 11). Next an aluminium metallisation layer 140 is applied and interconnect photolithography used to etch away portions 142, 144, 146, 148 of the metallisation layer 140 to define signal lines 150, 152, 154 (Figure 12). The end result is the device shown in Figure 13 having the titantium-tungsten layer 70A installed between the signal lines and the
N-type emitter windows only.
Claims (8)
1. A method of selectively applying barrier metal to a surface of a NPN semiconductor wafer, comprising the steps of processing the semiconductor wafer to produce a NPN transistor device having an emitter contact window exposed to N-type silicon, a collector contact window exposed to N-type silicon, and a further contact window having therein a layer of silicon dioxide over P-type silicon; depositing a layer of an alloy of titanium-tungsten on the surface of the processed semiconductor wafer; etching the titanium-tungsten layer out of the further contact window; etching the silicon dioxide layer out of the further contact window to expose the P-type silicon; depositing a metallisation layer of aluminium on the semiconductor wafer; using conductor interconnect photolithography to etch away undesired portions of the metallisation layer to define signal lines; and etching away those portions of the titaniumtungsten layer not covered by the signal lines so that the titanium-tungsten layer provides barrier metal between the signal lines and the N-type silicon of the emitter and collector contact windows, and so that the signal lines connect directly to the further contact window.
2. A method as claimed in claim 1 in which a washed emitter process is used to produce said NPN transistor device.
3. A method as claimed in claim 1 in which said further contact window is a base contact window.
4. A method of selectively applying barrier metal to a surface of a NPN-type semiconductor wafer, comprising the steps of: processing the semiconductor wafer to produce a NPN transistor device having an emitter contact window exposed to N-type silicon, a collector contact window exposed to
N-type silicon, and a further contact window having therein a layer of silicon dioxide over P-type silicon; exposing said further contact window to P-type silicon by etching said silicon dioxide layer; depositing a layer of an alloy of titanium-tungsten on the surface of the semiconductor wafer; patterning the titanium-tungsten layer by photolithography so that the titanium-tungsten remains in the emitter contact window only; depositing a metallisation layer of aluminium onto the semiconductor wafer; and using conductor interconnect photolithography to etch away undesired portions of the metallisation layer to define signal lines, so that the titanium-tungsten layer provides barrier metal between said signal lines and the N-type silicon of the emitter contact window and so that said lines connect directly to the further contact window and the collector contact window.
5. A NPN semiconductor device having N-type silicon collector and emitter contact windows and a
P-type silicon base contact window, comprising: an aluminium signal line directly contacting the N-type silicon in the collector contact window; a barrier metal titanium-tungsten layer directly contacting the
N-type silicon in said emitter contact window; aluminium signal line directly contacting said titanium-tungsten layer in said emitter contact window; and an aluminium signal line directly contacting said
P-type silicon of said base contact window, the arrangement being such that said barrier metal separates said aluminium signal lines from the
N-type silicon in said emitter contact window only.
6. A method of selectively applying barrier metal to a surface of a NPN-type semiconductor wafer substantially as herein described with reference to Figures 7 to 9 or Figures 10 to 13 of the accompany- ing drawings.
7. A NPN semiconductor device substantially as herein described with reference to and as shown in
Figure 9 or Figure 13 of the accompanying drawings.
8. Any novel integer or step, or combination of integers or steps, hereinbefore described and/or as illustrated in the accompanying drawings, irrespective of whether the present claim is within the scope of, or relates to the same or a different invention from that of, the preceding claims.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51320683A | 1983-07-12 | 1983-07-12 | |
| US06/513,208 US4486946A (en) | 1983-07-12 | 1983-07-12 | Method for using titanium-tungsten alloy as a barrier metal in silicon semiconductor processing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8415370D0 GB8415370D0 (en) | 1984-07-18 |
| GB2143372A true GB2143372A (en) | 1985-02-06 |
| GB2143372B GB2143372B (en) | 1987-07-01 |
Family
ID=27057779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8415370A Expired GB2143372B (en) | 1983-07-12 | 1984-06-15 | Applying barrier metal to a semiconductor |
Country Status (4)
| Country | Link |
|---|---|
| AU (1) | AU563246B2 (en) |
| DE (1) | DE3425599A1 (en) |
| FR (1) | FR2549289B1 (en) |
| GB (1) | GB2143372B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2218568A (en) * | 1988-05-13 | 1989-11-15 | Mitsubishi Electric Corp | Production method for semiconductor device |
| US5240879A (en) * | 1991-03-20 | 1993-08-31 | U.S. Philips Corp. | Method of manufacturing a semiconductor device having conductive material provided in an insulating layer |
| US5254498A (en) * | 1991-05-23 | 1993-10-19 | Sony Corporation | Method for forming barrier metal structure |
| US5364817A (en) * | 1994-05-05 | 1994-11-15 | United Microelectronics Corporation | Tungsten-plug process |
| USRE36663E (en) * | 1987-12-28 | 2000-04-18 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL82113A (en) * | 1987-04-05 | 1992-08-18 | Zvi Orbach | Fabrication of customized integrated circuits |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3946426A (en) * | 1973-03-14 | 1976-03-23 | Harris Corporation | Interconnect system for integrated circuits |
| FR2372511A1 (en) * | 1976-11-25 | 1978-06-23 | Comp Generale Electricite | Emitters and base contacts formed on planar semiconductors - with only a short distance between emitter and base |
-
1984
- 1984-06-15 GB GB8415370A patent/GB2143372B/en not_active Expired
- 1984-06-22 AU AU29794/84A patent/AU563246B2/en not_active Ceased
- 1984-07-05 FR FR8410694A patent/FR2549289B1/en not_active Expired
- 1984-07-11 DE DE19843425599 patent/DE3425599A1/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36663E (en) * | 1987-12-28 | 2000-04-18 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
| GB2218568A (en) * | 1988-05-13 | 1989-11-15 | Mitsubishi Electric Corp | Production method for semiconductor device |
| US4902646A (en) * | 1988-05-13 | 1990-02-20 | Mitsubishi Denki Kabushiki Kaisha | MESFET process employing dummy electrodes and resist reflow |
| GB2218568B (en) * | 1988-05-13 | 1993-01-20 | Mitsubishi Electric Corp | Semiconductor device and production method therefor |
| US5240879A (en) * | 1991-03-20 | 1993-08-31 | U.S. Philips Corp. | Method of manufacturing a semiconductor device having conductive material provided in an insulating layer |
| US5254498A (en) * | 1991-05-23 | 1993-10-19 | Sony Corporation | Method for forming barrier metal structure |
| US5364817A (en) * | 1994-05-05 | 1994-11-15 | United Microelectronics Corporation | Tungsten-plug process |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8415370D0 (en) | 1984-07-18 |
| FR2549289A1 (en) | 1985-01-18 |
| FR2549289B1 (en) | 1987-04-30 |
| AU563246B2 (en) | 1987-07-02 |
| DE3425599A1 (en) | 1985-04-25 |
| GB2143372B (en) | 1987-07-01 |
| AU2979484A (en) | 1985-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |