GB2141243A - Variable reluctance transducer circuit - Google Patents

Abstract

A variable reluctance transducer circuit includes an input comparator (10), an output flip-flop (35), an exclusive NOR gate (22) gating the flip-flop output and the comparator output together and controlling a first counter (24) which counts clock pulses when enabled. The first counter (24) is set to a preset state periodically and a second counter (32-34) counts the number of consecutive cycles in which the first counter (24) counts from this preset state to another predetermined state. The output flip-flop changes state only if the second counter counts to a predetermined number. The transducer circuit may be used in an internal combustion engine ignition system and is stated to provide immunity from impulsive noise. <IMAGE>

Description

SPECIFICATION Variable reluctance transducer circuit This invention relates to a variable reluctance transducer circuit intended for use, inter alia, in internal combustion engine ignition systems.

In such an application, it is found that several problems exist. Firstly, the duration and amplitude of the transducer output signals vary considerably with engine speed and impulsive noise signals are often present which are of amplitude similar to that of the transducer output, particularly at low speed.

Various proposals have already been made for overcoming these problems, but all these involve complex analog circuits, which do not lend themselves to adaptation to large scale integrated circuit construction.

It is an object of the present invention to provide a variable reluctance transducer circuit having satisfactory impulsive noise immunity but which is suitable for manufacture as a large scale integrated circuit.

A variable reluctance transducer circuit in accordance with the invention comprises voltage comparator means connected to the transducer output, discrimination means connected to the output of the comparator means and operating to determine the validity of a change in the comparator output by testing the output of comparator a plurality of times in each of a series of consecutive sample intervals so as to provide an output only if more than a predetermined proportion of the tests in each of a predetermined number of consecutive sample intervals are valid, and an output circuit connected to said discrimination circuit.

Preferably the discrimination circuit includes gate means connected to receive the output of the comparator means and to receive the output of the output circuit and arranged to pass signals on to the remainder of the discrimination circuit only when the change in the comparator means output is such as, if validated, will cause a change in the output of the output circuit.

In the accompanying drawings: Figure lisa circuit diagram showing an example of the invention made of a conventional CMOS integrated circuits; Figure 2 is the circuit diagram of another example of the invention implemented as a CMOS large scale integrated circuit, and Figures 3 and 4 are circuit diagrams showing two different interface circuits for connecting the circuit of Figure 1 or Figure 2 to the transducer itself.

As shown in Figure 1 the circuit using converition CMOS integrated circuits includes at its input a voltage comparator 10 which is the only analog circuit included in the circuit.

As shown in Figure 3 the comparator 10 has its inverting input connected by two resistors 11,12 in series to one output terminal of the transducer 13, the other terminal of which is grounded. the noninverting input of the comparator is also grounded.

Two protective diodes 14, 15 connect the junction of resistors 11, 12 to ground and to the positive supply respectively. In the alternative arrangement of Figure 4the resistor 12 is replaced by a capacitor 16, and a pair of resistors 17,18 which are connected in series between the positive supply and ground have their common point connected to the junction of resistor 11 with capacitor 16. Another pair of resistors 19, 20 connected in series between the positive supply and ground have their common point connected to the non-inverting input of the voltage comparator 10. The arrangement shown in Figure 4 is a.c. coupled to the transducer. In either case hysteresis may be added by means of a suitable d.c.

positive feedback connection.

Returning to Figure 1, the output of the comparator 10, (which may be an LM139 integrated circuit, necessitating a external pull-up resistor 21 at its output) is connected to one input of an EXNOR gate 22, the other input of which is connected to the final output of the circuit. The output of gate 22 is connected to one input of an OR gate 23 which has its output connected to the INHIBIT input of a four bit binary presettable down counter 24 (a CMOS integrated circuit type MC14526). This has its preset data inputs Do and D1 connected to the positive supply and D2 and D3 grounded so that the counter is preset to 0011 (or 3) on receipt of an input at its PRESET ENABLE input terminal. The CASCADE FEEDBACK input of the counter is connected to the positive supply and the MASTER RESET input is grounded.

The "0" output of the counter 24 is connected to the other input of gate 23 and the CLOCK input is connected to a 1MHz clock pulse source.

A second counter 25, in this case a simple binary ripple-through counter (CMOS integrated circuit type MC14024) has its CLOCK input connected to the output of an inverter 26, the input of which is connected to the clock pulse source. The Q3 output of this counter 25 is connected by a resistor 27 to the RESET input thereof, such input being connected by a capacitor 28 to ground. The Q3 output is also connected to the PRESET ENABLE input of counter 24 and also to the CLOCK input of a D-type flip-flop circuit 31 (CMOS integrated circuit type MC14013), the DATA input of which is connected to the "0" output of the counter 24. Both the S and R inputs of flip-flop 31 are grounded.The Q and Q outputs of flip-flop 31 are connected to inputs of each of two AND gates 30 and 29 respectively, the other inputs of which are connected to the Q2 output of the counter 25.

The output of gate 29 is connected to the R input of a D-type flip-flop circuit 32, which has its S input grounded, its CLOCK input connected to the output of gate 30 and its Q output connected to its D input.

The Q output of circuit 32 is connected to the CLOCK input of another D type flip-flop circuit 33 having its R input connected to the output of gate 29, its S input grounded and its 0 output connected to its D input.

Theoutput of circuit 33 is connected to the CLOCK input of yet another D type flip-flop circuit 34 having its R input connected to the output of gate 29 its S input grounded and its D input connected to a supply. The 0 output of circuit 34 is connected to the CLOCK input of another D type flip-flop circuit 35 which has both its S and R terminals grounded and ftsQoutput output connected to its D input. TheBof circuit 35 is connected to the remaining input of gate 22 and the Q output provides the final output of the circuit.

The circuit described above operates to validate signals from the comparator 10 by sampling the output thereof at 4 A S intervals and clocking or resetting the counter made up of flip-flop circuits 32, 33 and 34 according to whether or not the output of gate 22 is low in any three of the four 1 ffi S periods in each cycle. Counter 24 is set at the beginning of each 4 S period to the 0011 state referred to above, counter 25 is clocked every 1 F S, and counter 24 is only clocked if its "0" is not high and the output of XNOR gate 22 is low. If counter 24 reaches zero it is inhibited until reset by counter 25.Circuit 31 is set or reset at the end of each 411 S cycle if the "0" output of counter 24 is high - i.e. if three or four clock pulse have been counted, and determines whether gate 29 or gate 30 passes the next Q2 pulse from counter 25, to reset or clock the counter 32,33,34.

Flip flop circuit 35 is clocked each time four valid samples (i.e. samples in which gate 30 is enabled) have been counted, the gate 22 thereafter starts passing signals only when the output of comparator 10 is opposite the previously confirmed state.

Turning now to Figure 2, the special purpose CMOS integrated circuit includes an input comparator 10 and an EXNOR gate 22 as in Figure 1. Another EXNOR gate 40 has one input connected to the output of gate 22 and its other input connected to the Q output of a flip-flop circuit 41, and D-input of which is connected to the output of gate 40. The CLOCK input of flip-flop circuit 41 is connected to the output of an OR gate 42, one input of which receives the 1 MHz clock pulse train. The R input of circuit 41 is connected to an NRC bus which is supplied with pulses every 411 S by an on-chip divider (not shown).

Another flip-flop circuit 43 has its CLOCK input connected to the Q output of circuit 41 and its Q output connected to its D input. The R input of circuit 43 is connected to the NRC bus. The Q outputs of circuits 41 and 43 are connected to the inputs of a NAND gate 44, the output of which is connected to an inverter 45 with its output connected to the other input of OR gate 42. The circuits 41,43 and gate 44 act in precisely the same manner as counter 24 of Figure 1 to provide a low output if the output of gate 22 is low for 3 or 4 of each group of each fou r 1 u5 periods.

A flip-flop circuit 43 and gates 46 and 47 correspond to circuit 31 and gates 29 and 30 of Figure 1, but gates 46,47 are NAND gates and receive a 250 KHz square wave from the on-chip divider mentioned. Flip-flop circuits 48,49,50 and 51 correspond to circuits 32 to 35 of Figure 1, and an additional flip-flop circuit 52 is provided which receives the output of circuit 51 at its D input and a 2MHz synchronised clock signal at its CLOCK input. TheB output of flip-flop circuit 52 is connected to gate 22 and the 0 output provides the verified output signal.

With either of the arrangements described above, verification of a change in the output of the compara tortakes a mere 16 W S which is insufficient to affect the accuracy of an engine spark ignition system in which the circuit is employed.

Claims (8)

1. A variable reluctance transducer circuit comprising voltage comparator means connected to the transducer output, discrimination means connected to the output of the comparator means and operating to determine the validity of a change in the comparator output by testing the output of comparator a plurality of times in each of a series of consecutive sample intervals so as to provide an output only if more than a predetermined proportion of the tests in each of a predetermined number of consecutive sample intervals are valid, and an output circuit connected to said discrimination circuit.

2. A circuit as claimed in claim 1 in which the discrimination circuit includes gate means connected to receive the output of the comparator means and to receive the output of the output circuit and arranged to pass signals on to the remainder of the discrimination circuit only when the change in the comparator means output is such as, if validated, will cause a change in the output of the output circuit.

3. A circuit as claimed in claim 2 in which said gate means comprises an exclusive nor gate and said output circuit is a flip-flop circuit.

4. A circuit as claimed in claim 2 in which said discrimination circuit includes a first counter for counting clock pulses when enabled, means for presetting the first counter to a set value for each sample and enabling the counter, means for inhibiting counting by said first counter at a predetermined count state thereof, a flip-flop circuit connected to said presetting means for setting thereby to one state for each sample and to the first counter for setting thereby to its other state if said predetermined count state is attained before resetting, and a second counter connected to said flip-flop circuit and counting the number of successive cycles in which said flip-flop circuit is set to its other state.

5. A variable reluctance transducer circuit substantially as hereinbefore described with reference to Figures 1 and 3 of the accompanying drawings.

6. A variable reluctance transducer circuit substantially as hereinbefore described with reference to Figures 1 and 4 of the accompanying drawings.

7. Avariable reluctance transducer circuit substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.

8. A variable reluctance transducer circuit substantially as hereinbefore described with reference to Figures 2 and 4 of the accompanying drawings.