GB2133909A

GB2133909A - A control circuit for a microcomputer

Info

Publication number: GB2133909A
Application number: GB08400753A
Authority: GB
Inventors: Tilmann Kruger; Hans Grasser; Peter Ennen
Original assignee: Diehl GmbH and Co
Current assignee: Diehl Verwaltungs Stiftung
Priority date: 1983-01-19
Filing date: 1984-01-12
Publication date: 1984-08-01
Also published as: IT1195997B; DE3301603C1; FR2539527A1; IT8420565V0; GB8400753D0; GB2133909B; IT8419212A0; FR2539527B1

Abstract

In an operating-voltage-dependent control circuit(s) for a microcomputer (MC) a reset circuit (RS) is provided which resets and starts the microprocessor of the microcomputer. On the one hand, long mainsfailure bridging times for the microprocessor and the working store of the microcomputer are desirable but, on the other hand, superfluous re- loadings of the working store are not. A bistable storage circuit (FF) is provided which changes over, in the event of an operating voltage which is too low for the operation of the working store, into its first switching state. In this switching state, upon occurrence of a reset signal of the reset circuit (RS) an initialisation (re-loading) signal for the working store is obtained. The second switching state of the storage circuit is switched after the start of the microprocessor. If the operating voltage does not fall to a value which endangers data safety in the store, on a following rise in operating voltage the microprocessor is reset and started without initialisation of the store. <IMAGE>

Description

SPECIFICATION A control circuit for a microcomputer This invention relates to a control circuit for a microcomputer having a microprocessor with a working store, the circuit being dependent upon the operating voltage and having a reset circuit which generates a reset signal which resets and starts the microprocessor in the event of the operating voltage becoming sufficiently high and stops it in the event of the operating voltage becoming too low.

A control circuit of this kind is described in German Patent Specification No. 31 03 489.

There, after a break in the operating voltage, the reset circuit is intended to start the microprocessor only when a voltage state suitable for operation has been safely reached.

The operating voltage of microcomputers is derived from the mains electricity supply. In order to be able to bridge or cover a failure of mains electricity for a period of time, a storage capacitor is provided. Depending on the capacitance thereof and the load current, certain mains failure times can be compensated or allow for without adversely affecting the running of the microcomputer.

With known microcomputers, the peripheral equipment is switched off in the event of mains failure (load decrease). This means that the mains failure time which can be bridged or covered by the storage capacitor is effectively extended so that a longer mains failure time is allowed for than would otherwise be the case.

Microcomputers constructed using P-channel MOS technology are known in which the operating voltage of the microprocessor can be switched off independently of the operating voltage which is feeding the working store (RAM).

If, in the event of mains failure, the operating voltage of the microprocessor were to be switched off, then the energy of the storage capacitor could be available solely for maintaining the loading of the working store. However, the microprocessor would have to be reset and started afresh after every mains failure, even though the mains failure may only be for a brief time. Moreover, in the event of a mains failure which lasts for a long time and during which the operating voltage applied to the working store drops below a minimum value, indefinable data accumulated in the working store would have to be reckoned with. Initialising the working store after each mains failure in order to avoid the introduction of such data into the working store would in practice nullify the possible benefit to be gained by bridging mains failure times.

An object of the present invention is to provide a circuit with which, on the one hand, relatively long mains-failure bridging times for the microprocessor and the working store may be achievable, but with which, on the other hand, superfluous initialisations are not effected.

According to the present invention there is provided an operating-voltage-dependent control circuit for a microcomputer having a microprocessor with a working store, comprising a reset circuit which is capable of generating a reset signal which, in the event of an operating voltage becoming sufficiently high, resets and starts the microprocessor and stops it in the event of the operating voltage becoming too low, characterised in that a bistable storage circuit is provided which, in the event of an operating voltage too low for the operation of the working store, goes into its first switching state, in that the first switching state, upon occurrence of a reset signal, leads to an initialisation signal for the working store and in that a second switching state of the storage circuit is selectable after starting of the microprocessor so that during the second switching state the reset signal only resets and starts the microprocessor.

Further according to the present invention there is provided a microcomputer with at least one control circuit as described in the immediately preceding paragraph.

The operating voltage range in which the data of the working store is s."l ensured to be not adversely affected is greater than the operating voltage range in which the microprocessor can work. Through the present invention the result may be achieved that, in the event of a drop in the operating voltage as a result of mains failure, initially the microprocessor stops, but the working store is still maintained by the operating voltage.

If the operating voltage only drops to a value (bearing in mind the specifications of the working store) where the data safety is still guaranteed, when the reset signal occurs in the course of a following rise in the operating voltage, the data of the working store is still ensured, so that its initialisation (reloading) is superfluous and therefore does not take place. Thus the result is achieved that the microcomputer rapidly resumes its operation even after a fairly long failure time of the mains supply.

Only when, in the appropriate circumstances, a low enough operating voltage is reached that the data safety of the working store is no longer guaranteed does the storage circuit register this low operating voltage being reached. Upon later rising operating voltage, in this case upon occurrence of the reset signal, the working store is loaded anew, so that the necessary data safety is guaranteed for following operation of the microcomputer.

In a further development of the invention, the storage circuit is switched from the first switching state into the second one only when the initialisation of the working store is terminated.

Thus the result is achieved that breaks in voltage occurring during initialisation cannot lead to the second switching state (which is a sign of definitely protected data) being selected before the working store is actually loaded with the correct data.

To extend the mains-failure bridging time, the microprocessor may be switched off at a value of the operating voltage which lies between the value at which the storage circuit goes into the first switching state and that value at which the reset circuit responds.

Further according to the present invention there is provided a control circuit for a microcomputer having a microprocessor with a working or read/write store, said control circuit comprising a reset circuit capable of generating a reset signal which resets and starts the microprocessor when the oerating voltage of the microprocessor reaches a sufficiently high value and the reset signal also being capable of stopping the microprocessor, whilst still maintaining the working store, should the operating voltage drop to a sufficiently low value, said control circuit being such that, provided the operating voltage does not fall to a value which endangers data safety in the store, on a following rise in operating voltage the microprocessor is reset and started without initialisation (re-loading) of the working store, but where the operating voltage falls to a value which endangers data safety in the store, on a following rise in operating voltage the microprocessor is reset and started and the working store is initialised (re-loaded).

Still further according to the present invention there is provided a microcomputer with at least one control circuit as described in the immediately preceding paragraph.

An embodiment of a control circuit for a microcomputer in accordance with the present invention will now be described, by way of only, with reference to the accompanying drawings in which:~ FIGURE 1 shows the control circuit in a microcomputer; FIGURE 2 shows a reset circuit of the control circuit; FIGURE 3 shows a switch-off stage of the control circuit; FIGURE 4 shows a bistable storage circuit of the control circuit; and FIGURE 5 shows voltage diagrams of the control circuit.

A P-channel-MOS microcomputer MC (for example from the Series Hitachi HMCS 40) has in particular a microprocessor and a working store or a write/read store (RAM). The microprocessor is wired up with an oscillator (not shown in more detail) for internal timing frequency generation.

Connected to the microcomputer MC are a data display device B, a data input device E and a switching-relay output device A.

The microcomputer MC is connected by way of a control circuit S to a mains-operated power supply part which consists of a rectifier G, a storage capacitor C1 as well as a stabilisation stage H.

The frequency (50 Hz) of the mains feeding the rectifier G is applied to an input 1 of the microcomputer MC. If the mains fails, then the microcomputer MC switches off the devices A, B and E (load drop) by way of its input 1.

The earth potential of the rectifier G is connected to an input 2 of the microcomputer MC.

The negative rectifier potential is applied in unstabilised manner to an input 3.

The stabilisation stage H has a resistor R1, a Zener diode Z and a resistor R2 connected in series. Lying in parallel with the resistor R2 is the base-collector section of a transistor T1, the emitter of which supplies an operating voltage (stabilised within certain limits) to an input 4 of the microcomputer MC.

The control circuit S has a reset circuit RS, a switch-off stage AS and a bistable storage circuit FF, in the form of a flip-flop. The output of the reset circuit RS is applied to a reset input 5 of the microcomputer MC. A signal at this input 5 causes the program cycle of the microprocessor to be reset to "0" and started at the commencement of the signal; during the reset signal RES the program takes its course and stops with the end of the reset signal RES (see FIGURE 5c).

The output of the storage circuit FF is connected to an input 7 of the microcomputer MC.

At the input 7 there stands a signal WS which corresponds to the first or second switching state of the storage circuit FF (see FIGURE 5d). The microcomputer MC is so designed that, when the reset signal RES is applied to the input 5 and a low level signal stands at the input 7, it not only resets and starts the microprocessor, but also loads or charges the working store afresh. If, on the other hand, in the case of a "high" level of the signal WS, the reset signal RES occurs, the working store is not loaded or charged afresh; only the microprocessor is reset and started.

In the reset circuit RS in accordance with FIGURE 2, lying between the inputs 2 and 3 and parallel to one another are series connections consisting of resistors R3 and R4 as well as the emitter-collector section of a transistor T2 and of a resistor R5. Between the inputs 2 and 4 there lies the series connection consisting of a resistor R6, R7 and the collector-emitter section of a transistor T3. The base of the transistor T2 lies between the resistors R6 and R7. The base of the transistorT3 lies between the resistors R3 and R4.

The input 5 is connected to the collector of the transistorT2. Moreover, it is applied, by way of a resistor R8, to the base of the transistor T3.

The switch-off stage AS in accordance with FIGURE 3 has, between the inputs 2 and 4, a series connection consisting of the emittercollector section of a transistor T4, of a resistor R9 and of a resistor R10. The base of the transistor T4 lies between the Zener diode Z and the resistor R1. Connected in parallel with the resistor R10 is the base-emitter section of a transistor T5, the collector of which is applied to the input 6.

With the storage circuit FF in accordance with FIGURE 4, lying in parallel between the inputs 2 and 4 are series connections of the emittercollector section of a transistor T6 and of a resistor Tri 1, as well as of the emitter-collector section of a transistor T7 and of a resistor R12. The collector of the transistor T7 is connected to the input 7 and, by way of a resistor Tri 3, to the base of the transistor T6. The collector of the transistor T6 lies, by way of a resistor R 14, at the base of the transistor T7. The base of the transistor T7 is connected by way of a resistor R15 to the input 2.

Lying parallel to the resistor R15 is the series connection consisting of a resistor R16 and a diode D. Connected to the resistor R16 and the diode D is an RC-member, consisting of a capacitor C2 and a resistor R17. Applied to the RC-member is a signal SWS which is derived from the impulses of the oscillator of the microprocessor and which occurs as soon as the data display device B is activated (see FIGURE sue).

Illustrated, by way of example only, is a particular plotted course or curve of the operating voltage US indicated in FIGURE 5a. At the point in time to, the mains-operated power supply part of the microcomputer MC1 is switched on. The capacitor C1 is then charged up. At a point in time tl a voltage U1 is reached at which the operating voltage UP is applied to the microprocessor (see FIGURE 5c). At a point in time t2 a voltage U2 is reached at which the reset signal RES (see FIGURE 5b) begins and thus sets the microprocessor to "0" and starts it.Since, at this point in time, the storage circuit FF stands in its first switching state (see FIGURE 5d), the working store is also charged or loaded. As soon as the loading has taken place, at a point in time t3, the data input device E and the switching-relay output device A, as well as more particularly the data display device B, are switched on. By device B, the impulses of the internal oscillator of the microcomputer MC are applied to the storage circuit FF, whereby this switches over into its second switching state.

The microcomputer MC is now entirely operational. The charging of the capacitor C1 increases up to a point in time t4.

A mains failure occurs at a point in time t5. In this way the data display device B switches off and oscillator impulses no longer arrive at the storage circuit FF (see FIGURE 5e).

As a result of the failure at the point in time t5, the operating voltage US drops. With a voltage U3 at a point in time t6, which voltage is lower than the voltage U2, the reset signal RES ends (see FIGURE Sb) and stops the microprocessor. With a voltage which has dropped to U1 at the point in time t7, the microprocessor is separated from its operating voltage UP (see FIGURE 5c). Through this reduction of current consumption, the discharge of the capacitor C1 flattens out, so that the voltage drop does not follow the line L, but the line L'. As should be evident from FIGURE 5a, it is possible that an extended mains failure time can be bridged by the capacitor C1.

At a point in time t8 the mains switches on again. At this point in time the operating voltage UP has still not fallen below the minimum value U4 necessary for the working store. Accordingly, the storage circuit FF is not reset to its first switching state (see FIGURE 5d). As from the point in time t8 the operating voltage US rises. At a point in time t9 when the voltage U1 is reached, the switch-off stage AS switches on the supply voltage UP (see FIGURE 5c) for the microprocessor. At a following point in time t10 the microprocessor is reset and started. The oscillator signals are subsequently then delivered to the storage circuit FF (see FIGURE 5e).

At a point in time t11, then again the same switching state as at t4 is reached.

At a point in time ti 2 the mains voltage fails again. At points in time t13 and t14 the same procedures as previously described in relation points in time t6 and t7 take place.

The time-span between points in time ti 4 and tl 5 is longer than the time-span between the points in time t7 and t8. At the point in time ti S, the voltage US drops to a voltage which is lower than the voltage U4. This voltage is not sufficient to keep the data of the working store protected.

At point in time t16 the mains starts up again.

Between the point in time tl 5 and ti 6 the storage circuit FF has switched back into its first switching state (see FIGURE 5d). The capacitor C1 is recharged with the mains voltage. At point in time ti 7 the switch-off stage AS applies the operating voltage UP to the microprocessor. Following on the point in time ti 8 at which the voltage U2 is reached, the microprocessor is reset and started.

Moreover, the working store is loaded, as has already been described for the point in time t2 or t3 respectively.

Claims

1. A control circuit for a microcomputer having a microprocessor with a working or read/write store, said control circuit comprising a reset circuit capable of generating a reset signal which resets and starts the microprocessor when the operating voltage for the microprocessor reaches a sufficiently high value and the reset signal also being capable of stopping the microprocessor, whilst still maintaining the working store, should the operating voltage drop to a sufficiently low value, said control circuit being such that: provided the operating voltage does not fall to a value which endangers data safety in the store, on a following rise in operating voltage the microprocessor is reset and started without initialisation (reloading) of the working store; but where the operating voltage falls to a value which endangers data safety in the store, on a following rise in operating voltage the microprocessor is reset and started and the working store is initialised (re-loaded).

2. An operating-voltage-dependent control circuit for a microcomputer having a microprocessor with a working store, comprising a reset circuit which is capable of generating a reset signal which, in the event of the operating voltage becoming sufficiently high, resets and starts the microprocessor and stops it in the event of an operating voltage becoming too low, characterised in that a bistable storage circuit is provided which, in the event of an operating voltage too low for the operation of the working store, goes into its first switching state, in that the first switching state, upon occurrence of a reset signal, leads to an initialisation signal for the working store and in that a second switching state of the storage circuit is selectable after starting of the microprocessor so that during the second switching state the reset signal only resets and starts the microprocessor.

3. A control circuit as claimed in Claim 2, in which the storage circuit is switched from the first switching state into the second switching state only when initialisation of the working store is concluded.

4. A control circuit as claimed in Claim 2 or Claim 3 by which, on a mains failure, the peripherals of a microcomputer are switched off, and in which the second switching state is selected with switching-on of a data display device by impulses of an internal oscillator of the microcomputer being applied to the storage circuit.

5. A control circuit as claimed in any one of claims 2 to 4, in which the microprocessor is switched off at a value of the operating voltage which lies between the value at which the storage circuit goes into its first switching state and the value at which the reset circuit responds.

6. A control circuit for a microcomputer substantially as herein described and illustrated with reference to FIGURES 1 and 5 of the accompanying drawings.

7. A control circuit as claimed in Claim 1 or Claim 2 in which the reset circuit is substantially as herein described and illustrated with reference to FIGURE 2 of the accompanying drawings.

8. A control circuit as claimed in Claim 1 or Claim 2 comprising a switch-off stage substantially as herein described and illustrated with reference to FIGURE 3 of the accompanying drawings.

9. A control circuit as claimed in Claim 1 or Claim 2 in which a, or the, bistable storage circuit is substantially as herein described and illustrated with reference to FiGURE 4 of the accompanying drawings.

10. A microcomputer with at least one control circuit as claimed in any one of the preceding claims.