GB2133618A - Fabricating semiconductor circuits - Google Patents

Fabricating semiconductor circuits Download PDF

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Publication number
GB2133618A
GB2133618A GB08332939A GB8332939A GB2133618A GB 2133618 A GB2133618 A GB 2133618A GB 08332939 A GB08332939 A GB 08332939A GB 8332939 A GB8332939 A GB 8332939A GB 2133618 A GB2133618 A GB 2133618A
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GB
United Kingdom
Prior art keywords
radiation
substrate
mask
optical system
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08332939A
Other versions
GB8332939D0 (en
GB2133618B (en
Inventor
Anthony Ernest Adams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co PLC
Original Assignee
General Electric Co PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB838300117A external-priority patent/GB8300117D0/en
Application filed by General Electric Co PLC filed Critical General Electric Co PLC
Priority to GB08332939A priority Critical patent/GB2133618B/en
Publication of GB8332939D0 publication Critical patent/GB8332939D0/en
Publication of GB2133618A publication Critical patent/GB2133618A/en
Application granted granted Critical
Publication of GB2133618B publication Critical patent/GB2133618B/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A method of annealing (eg. driving in and activating impurities in) selected regions of a semi-conductor substrate 3 during fabrication of a circuit in the substrate. A laser beam is directed onto the substrate 3 through a mask 13 which shields the non-selected regions of the substrate from the laser beam, the masked beam being focussed onto the substrate 3 by an optical system 11. <IMAGE>

Description

SPECIFICATION Fabricating semiconductor circuits This invention relates to methods of fabricating semiconductor circuits.
A basic feature of conventional methods of fabricating semiconductor circuits is the formation, on the surface of a substrate of semiconductor material, of a layer of material in which are formed windows which define selected regions of the substrate into which dopant material is required to be introduced. A series of diffusions or ion-implantations is then used to introduce dopant material through the windows into the regions of the substrate defined by the windows followed by controlled furnace anneals to drive the dopant material into the substrate and cause the doped regions of the substrate to become electrically active.
It has been demonstrated that a beam of laser radiation, either in the form of a pulsed beam illuminating the whole substrate or a scanned cw beam, may be used as an alternative to furnace annealing. However, extreme care must then be taken to avoid damage to the masking layer defining the windows. One proposed method of overcoming this difficulty is to deposit additional layers to reflect radiation away from the substrate except from the doped regions it is desired to anneal. However, this technique requires several preparation steps and is difficult to carry out satisfactorily.
It is an object of the present invention to provide an alternative laser annealing technique which avoids the above mentioned difficulties.
According to the present invention, a method of annealing selected regions of a substrate of semiconductor material during fabrication of a circuit in the substrate comprises directing a beam of radiation onto said substrate through a mask such that nonselected regions are shielded from said radiation by the mask.
The radiation is suitably laser radiation.
The invention also provides an apparatus for carrying out a method according to the invention comprising: a source of radiation; an optical system arranged to direct radiation from said source onto a surface ofa semiconductor body; and means for mounting a mask between the source and the optical system; the optical system being adapted to provide an image of the mask on the surface of the semiconductor body.
One method and apparatus in accordance with the invention will now be described, by way of example, with reference to the accompanying drawing which is a schematic diagram of the apparatus.
Referring to the drawing, the apparatus comprises a chamber 1 in which a silicon substrate 3 to be pro cessed is contained, the substrate containing a pre defined pattern of doped regions which it is desired to anneal. The atmosphere within the chamber 1 is controllable by means of a vacuum and gas handling system (not shown) connected with the chamber via a suitable duct 5.
Radiation derived from a laser 7, for example a Q-switched ruby laser, is directed onto a main face of the substrate 3 by way of a beam profiling optical system 9 and a further optical system 11. The optical system 11 is disposed in the chamber 1 and a mask 13 is disposed in the wall of the chamber 1 in the path of the radiation between the two optical systems 9 and 11.
The beam profiling system 9 is used to process the spatial intensity of the laser beam so as to produce a beam which is uniform over its cross-section to within a few per cent. The system 9 suitably comprises a lens arrangement or a laser amplifier running in saturation.
The system 11 comprises a high quality beam splitter 15 which deflects the beam received through the mask 13 through a lens system 17 onto a phase con- jugate mirror 19, the lens system 17 serving to reduce the size of the projected mask to match the aperture of the mirror 19. After reflection at the mirror 19 the radiation passes through the beam splitter 15 to impinge on the substrate 3 which is positioned at an optically equivalent position to the mask 13.
The mask 13 comprises a metal pattern on a thin quartz plate, the pattern corresponding to areas ofthe substrate 3 which it is not desired to anneal, i.e. to those areas ofthe substrate 3 which are required to be shielded from the radiation.
In use of the apparatus the substrate 3 is first accurately positioned with respect to the projected image of the mask 13, and the laser 7 then pulsed at high power to effect the required annealing as rapidly as possible. Alignment of mask image and substrate 3 may be facilitated by incorporating a few alignment holes (not shown) in the mask 13 and aligning the images of the holes with corresponding holes etched in the substrate 3. A low power helium-neon or other suitable laser may be used for this purpose.
To reduce the risk of laser induced damage to the mask 13 and optical systems 9 and 11, the peak power passing through these components may be limited to a suitably low level, and the laser energy raised to the required level for annealing by a laser amplifier (not shown positioned at the optically equivalent position to the mask 13.

Claims (8)

1. A method of annealing selected regions of a substrate of semiconductor material during fabrication of a circuit in the substrate comprising directing a beam of radiation onto said substrate through a mask such that non-selected regions are shielded from said radiation by the mask.
2. A method according to Claim 1 in which said radiation is laser radiation.
3. An apparatus for carrying out a method accord- ingtoeitheroneofthepreceding claims, comprising: a source of radiation; an optical system arranged to direct radiation from said source onto a surface of a semiconductor body; and means for mounting a mask between the source and the optical system, the optical system being adapted to provide an image of the mask on the surface of the semiconductor body.
4. An apparatus according to Claim 3 in which said optical system comprises: a beam splitter arranged to direct radiation after it has passed through said mask onto a phase conjugate mirror arranged to reflect said radiation through said beam splitter onto said surface.
5. An apparatus according to Claim 4 in which a lens system is interposed in the radiation path between said beam splitter and said mirror, said lens system being effective to substantially match area of said radiation beam to the aperture of said mirror.
6. An apparatus according to Ciaim 3 or Claim 4 in which a laser amplifier in interposed in the radiation path between said beam splitter and said surface.
7. A method of annealing selected regions of a substrate of semiconductor material during fabrication of a circuit in the substrate, substantially as herinbefore described, with reference to the accompanying drawing.
8. An apparatus for carrying out the method of Claim 7, substantially as hereinbefore described with reference to the accompanying drawings.
GB08332939A 1983-01-05 1983-12-09 Fabricating semiconductor circuits Expired GB2133618B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08332939A GB2133618B (en) 1983-01-05 1983-12-09 Fabricating semiconductor circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB838300117A GB8300117D0 (en) 1983-01-05 1983-01-05 Fabricating semiconductor circuits
GB08332939A GB2133618B (en) 1983-01-05 1983-12-09 Fabricating semiconductor circuits

Publications (3)

Publication Number Publication Date
GB8332939D0 GB8332939D0 (en) 1984-01-18
GB2133618A true GB2133618A (en) 1984-07-25
GB2133618B GB2133618B (en) 1986-09-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB08332939A Expired GB2133618B (en) 1983-01-05 1983-12-09 Fabricating semiconductor circuits

Country Status (1)

Country Link
GB (1) GB2133618B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000706A1 (en) * 1997-06-27 1999-01-07 Cooper Gregory D Transferring a programmable pattern by photon lithography
GB2354111A (en) * 1999-07-13 2001-03-14 Nec Corp Method for forming semiconductor films at desired portions on a substrate
EP1139409A2 (en) * 2000-02-29 2001-10-04 Agere Systems Guardian Corporation Selective laser anneal on semiconductor material

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1122489A (en) * 1965-05-27 1968-08-07 Ibm Method of diffusing material into a substrate
GB1136924A (en) * 1964-12-23 1968-12-18 Matsushita Electric Ind Co Ltd Method of diffusing impurities into solid materials
US3699649A (en) * 1969-11-05 1972-10-24 Donald A Mcwilliams Method of and apparatus for regulating the resistance of film resistors
GB1536618A (en) * 1976-12-06 1978-12-20 Ibm Semiconductor devices
US4155779A (en) * 1978-08-21 1979-05-22 Bell Telephone Laboratories, Incorporated Control techniques for annealing semiconductors
GB2021316A (en) * 1978-05-23 1979-11-28 Western Electric Co Isolation region for a semiconductor device
GB2087641A (en) * 1980-11-19 1982-05-26 Secr Defence Semiconductor devices
EP0071471A2 (en) * 1981-07-30 1983-02-09 Fujitsu Limited Method of forming a single-crystal semiconductor film on an amorphous insulator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1136924A (en) * 1964-12-23 1968-12-18 Matsushita Electric Ind Co Ltd Method of diffusing impurities into solid materials
GB1122489A (en) * 1965-05-27 1968-08-07 Ibm Method of diffusing material into a substrate
US3699649A (en) * 1969-11-05 1972-10-24 Donald A Mcwilliams Method of and apparatus for regulating the resistance of film resistors
GB1536618A (en) * 1976-12-06 1978-12-20 Ibm Semiconductor devices
GB2021316A (en) * 1978-05-23 1979-11-28 Western Electric Co Isolation region for a semiconductor device
US4155779A (en) * 1978-08-21 1979-05-22 Bell Telephone Laboratories, Incorporated Control techniques for annealing semiconductors
GB2087641A (en) * 1980-11-19 1982-05-26 Secr Defence Semiconductor devices
EP0071471A2 (en) * 1981-07-30 1983-02-09 Fujitsu Limited Method of forming a single-crystal semiconductor film on an amorphous insulator

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000706A1 (en) * 1997-06-27 1999-01-07 Cooper Gregory D Transferring a programmable pattern by photon lithography
US6291110B1 (en) 1997-06-27 2001-09-18 Pixelligent Technologies Llc Methods for transferring a two-dimensional programmable exposure pattern for photolithography
US6480261B2 (en) 1997-06-27 2002-11-12 Pixelligent Technologies Llc Photolithographic system for exposing a wafer using a programmable mask
US6600551B2 (en) 1997-06-27 2003-07-29 Pixelligent Technologies Llc Programmable photolithographic mask system and method
US6888616B2 (en) 1997-06-27 2005-05-03 Pixelligent Technologies Llc Programmable photolithographic mask system and method
GB2354111A (en) * 1999-07-13 2001-03-14 Nec Corp Method for forming semiconductor films at desired portions on a substrate
US6989300B1 (en) 1999-07-13 2006-01-24 Nec Corporation Method for forming semiconductor films at desired positions on a substrate
EP1139409A2 (en) * 2000-02-29 2001-10-04 Agere Systems Guardian Corporation Selective laser anneal on semiconductor material
EP1139409A3 (en) * 2000-02-29 2003-01-02 Agere Systems Guardian Corporation Selective laser anneal on semiconductor material
US7605064B2 (en) 2000-02-29 2009-10-20 Agere Systems Inc. Selective laser annealing of semiconductor material

Also Published As

Publication number Publication date
GB8332939D0 (en) 1984-01-18
GB2133618B (en) 1986-09-10

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