GB2087641A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

Info

Publication number
GB2087641A
GB2087641A GB8037170A GB8037170A GB2087641A GB 2087641 A GB2087641 A GB 2087641A GB 8037170 A GB8037170 A GB 8037170A GB 8037170 A GB8037170 A GB 8037170A GB 2087641 A GB2087641 A GB 2087641A
Authority
GB
United Kingdom
Prior art keywords
substrate
flux
film
energy
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8037170A
Other versions
GB2087641B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Defence
Original Assignee
UK Secretary of State for Defence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Secretary of State for Defence filed Critical UK Secretary of State for Defence
Priority to GB8037170A priority Critical patent/GB2087641B/en
Publication of GB2087641A publication Critical patent/GB2087641A/en
Application granted granted Critical
Publication of GB2087641B publication Critical patent/GB2087641B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A semiconductor device having one or more regions of reduced minority carrier lifetime is produced in a process in which a substrate of semiconductor material (1) having a transparent film (9) covering a high melting point material is irradiated with an intense radiant flux, either pulsed or continuous. The flux density and the duration of irradiation are selected so that the minority carrier lifetime of the semiconductor material (1) is reduced. The flux may be radiant energy from a laser source (5). The substrate material may be silicon or doped silicon material and the film may be of silicon dioxide or silicon nitride. The flux may be scanned over the substrate so that an extensive area may be irradiated; the scan may be continuous or stepped. Other regions of the substrate may be left uncovered by film (9) but irradiated to enhance the minority carrier lifetime in those regions. The process may be used to produce fast switched storage devices such as switched charge coupled device correlation or random access digital memory circuits, or for enabling production of MOS and bipolar components on a common chip. <IMAGE>

Description

SPECIFICATION Semiconductor devices The present invention relates to semiconductor devices and to processes for their manufacture. In particular, in relation to these processes, it concerns a technique for reducing minority carrier lifetime (hereinafter referred to as MCL).
In charge storage components, for example capacitors, memory cells and charge coupled devices (CCD's), long term charge storage is generally requisite and for these components therefore it is desirable that the minority carrier lifetimes be long. In other components - for example fast switching circuit components - speed of operation is all important, and in contrast it is generally desirable that the MCL be as short as possible and charge storage effects be minimized. In many applications - for example in CCD correlators, random access memory circuits (RAM's) and MOS/bipolar hybrid circuits, - both storage components and fast switching components, are required.Where both these types of components are integrated in a common semi-conductor substrate some form of processing compromise is generally required, or complex circuitry is needed to mitigate the problems of incompatibility.
A variety of processes for increasing MCL in a semiconductor exists. Cleaning procedures such as those using HCl/H202/NH4OH sequences, by the complexing of heavy metal surface contaminants have been shown to increase MCL. Similarly, furnace procedures which reduce the interface states at a semiconductor/insulator interface, by reducing the surface recombination velocity, also increase MCL. Also processes of gettering via HCI, Cl2, TCE environments in oxidation or annealing can similarly remove heavy metals and/or reduce defects such as stacking faults in the semiconductor, to increase MCL.
Laser irradiation has been used to increase MCL through back surface damage to semiconductor wafers. In this way, similar to ion implantation into wafer back surfaces or back surface mechanical treatment, enhanced MCL is achieved. A process including laser zone refining, followed by surface contaminant removal by liquid or gaseous plasma etching, can also be used to increase MCL.
On the other hand, MCL can be reduced by diffusion techniques. Typically, heavy metal dopants - e.g. gold - are used. These may be introduced by evaporation or chemical deposition, or by ion implantation, and are subsequently caused to diffuse at elevated temperature. It is however a drawback that these dopants can diffuse very rapidly throughout a wafer, and it is difficult if not impossible to control the diffusion to localise the dopant effectively. Additionally these dopants can be easily transferred from wafers into the body of a furnace and out into other wafers subsequently, so much so, that gold processing is forbidden in many MOS processing laboratories.
Because of the ready mobility of these dopants, even at low processing temperatures, reproducibility and reliability of low lifetime are difficult to achieve. The diffused dopant is often responsible for an increase in device leakage current.
The invention is intended to provide an alternative. It provides, in one form, a means of producing a region or regions within a semiconductor wafer, characterised by diminished MCL. These regions, which may be produced in a wafer of otherwise long MCL, are localised and stable. Further, this invention provides, in another form, a means for producing short MCL over an entire wafer.
According to the invention there is provided a process for the manufacture of a semiconductor device including the following steps:- providing a substrate of semiconductor material, having an intimate contact with its upper surface, a transparent film, the material of this film being mismatched in structure to the material of the substrate and having a higher melting point than that of the substrate; and, exposing the substrate through this film to an intense flux of energy of density and duration sufficient to produce in the region of the semiconductor material underlying the film, a reduction in minority carrier lifetime.
It is thought that localised defects are induced in the underlying exposed region by localised stresses sustained by the mismatched film, which may be either in tension or compression during or following the exposure, and it is these defects that bring about the reduction in MCL.
The energy flux may be of visible of non-visible radiation, or of energetic particles, and the term 'transparent' is to be contrued accordingly.
The semiconductor material may be of silicon.
It may be doped n- or p-type, or may include preformed regions of one or both types. Thus in silicon, the dopant may be phosphorus, or may be boron. For a silicon substrate the film material may be silicon dioxide (SiO2), or silicon nitride (Si3N4).
The flux may be a flux of radiant energy produced by a laser source. The laser source may be of pulsed or continuous wave (CW) type. The film area that is exposed may be defined by the laser beam cross-section itself, or if smaller, by a pattern definition mask - e.g. of gold or aluminium - defined on the film surface. An area of film. larger than the beam cross-section, may be exposed by sequenced step-and-shot traverse (pulsed source) or by continuous scan (CW source), the desired energy flux and duration of exposure of the scanned film being achieved by appropriate choice of scan-rate.
The film may be patterned so that only a part of the substrate is covered. When this substrate and the film are exposed to the flux of energy, MCL can be reduced in the covered parts of the substrate, by a mechanism such as that discussed above.
Concurrently in the uncovered part of the substrate the zone refining effects, consequent on the exposure to the energy flux, will concentrate trace quantities of heavy metal contaminants at the surface, from which they may be easily removed by etching, with consequent increase of MCL in these regions.
The invention will now be described by way of example only, with reference to the accompanying drawings of which: FIGURE 1: is an illustration of apparatus used in performance of the above process; FIGURE 2: is a cross-section of a semiconductor substrate treated by this process; and FIGURES 3 and 4: are perspective views of a substrate, treated in each case for defining a localised region of substrate subject to lifetime reduction.
There is shown in Figure 1 a semiconductor substrate 1 supported on a sliding carriage 3 in the field of a ruby laser source 5.-A flux of energy, a coherent light pulse, is directed from the laser source 5,onto the supported substrate 1 by means of an optic light guide 7. This guide 7 also serves to diffuse and redistribute the laser light to produce a light beam pulse of homogenously distributed intensity. Such a guide is described in UK Patent Application No. 4601 5/78,#and is employed since a uniform beam of wide crosssection area - e.g. 6 mm diameter - is convenient for the present purpose.
The substrate 1 is of boron doped p-type silicon material with a film 9 of silicon dioxide (SiO2) dielectric material formed on its upper surface.
This film 9 is about 3,000 A thick, formed by thermal growth, e.g. by heating and exposing the substrate 1 to oxygen or oxygen and water vapour under control growth conditions - a technique that is well known.
To form a localised region of reduced MCL in the substrate 1, the position of the substrate 1 is adjusted first, by controlling the carriage movement, to bring a target area of the dielectric film 9 beneath the exit aperture of the light guide 7. The laser source 5 is activated, and the laser light pulse it emits is guided onto the dielectric film 9. This film is thus exposed to the incident flux of energy over an area that is defined by the crosssection of the beam (Figure 1) or, as shown in Figures 2 and 3, over a smaller area that is defined by a window 11 in a reflecting mask 13. This mask 13, of aluminium, or other metal, is formed on the film 9 and defined by conventional techniques such as evaporation and photolithography.
The exact mechanism whereby the laser energy is absorbed by the substrate in this method is not yet fully understood. It is generally believed that when an intense flux of laser energy strikes a bare silicon surface, melting of the surface region followed by rapid recrystallization and solidification occurs. In this method, however, the silicon is covered by a transparent film of higher melting point than the substrate. Thus in this case as the melting point of silicon is 141000 while that of SiO2 is > 1 6000 C, the silicon would be expected to melt first. Thus, it is believed, initially the energy is absorbed quite deep in the semiconductor; when silicon surface melting occurs the silicon dioxide is still solid.Thus when the silicon recrystallizes the stressed surface film can cause lock-in of dislocations and other defects in the underlying silicon so that generation/recombination centres are provided.
Other possible explanations relate to solid phase epitaxial regrowth of material in the heated regions possibly combined with absorption of dopant from the surface film. In any case, provided the energy flux is of sufficiently high magnitude and of sufficiently short duration, the region of silicon 1 5 underlying the target area is found, on cooling, to exhibit reduced MCL.
This reduction of MCL has been verified using guard-ring MOS capacitors within this region, which have been formed by conventional processing on the dielectric surface. These capacitors have been pulsed from accumulation or inversion into depletion, and the time required to establish an inversion layer, measured. It has been found from such measurements that for the 3000 A thick layer of oxide 9, a flux of 0.9 Joule/cm2 and for a single pulse of duration of between 10 and 13 nanoseconds, that the storage time of the MOS capacitor is reduced to a time of the order of a few milliseconds corresponding to a reduced minority carrier lifetime T0 of about 10-9 seconds.This compares favourably with the original storage time value 1-2 mins or so, minority carrier lifetime To of about 10 ysec to 40 ,uses, found for untreated material.
A monotonic relationship between energy density and reduced lifetime is observed for pulses in the range of energy density between 0.6 and 0.9 Jcm for about 3000 A of SiO2 on Si. For this oxide thickness considerable increase in oxide surface damage is observed above 1 Jcm-2. In the lower range 0.1-0.5 Jcm#2 reduced MCL has been observed, but the MCL reductions are not so dramatic. Above 1.5 Jcm#2 the surface damage caused by the beam becomes extensive and this sets a practical limit on the energy densities that can be used. Thus energy densities in the range 2 J/cm2 to 1 2 J/cm2, for the silicon-silicon oxide system, appear to be sufficient to produce a local region of substantially diminished MCL.
Similar results have been found for oxide layers of between 300 and 3000 A thickness, with some small variation of the lower limit energy density required.
In the example shown in Figure 4, the film 9 is used to cover only a part of the surface of the substrate 1, its pattern being defined by conventional photolithography. When this substrate 1 is mounted on the carriage 3 and carriage movement controlled, uncovered regions of the substrate 1, as well as the region of the substrate 1 covered by the film 9, are passed underneath the optical guide 7. When the laser 5 is operated, the exposure of the substrate 1 to radiation causes a reduction of MCL in the covered region of the substrate, and it also heats and anneals the surrounding parts of the substrate.
With sufficient energy density the localised heating of the uncovered parts of the substrate can produce a zone refinement of the silicon material, impurities being driven to the substrate surface. This step is then followed by etching - either by a chemical solvent, or by ion beam plasma - to remove these impurities. The film 9 may be removed before or after this etching step.
The capability to reduce MCL locally in a semiconductor material may be applied to the manufacture of a wide variety of devices e.g. -- (i) Devices such as charge coupled or other correlators which have storage region holding analog or digital charge packets for comparison with other charge packets, and incorporating fast switching circuits within which fast operation is necessary; (ii) Random access digital memory circuit using charge storage nodes for data retention (e.g.
dynamic RAM). These each require local long MCL in the storage region; but in the switching and/or detection circuits short MCL could be advantageous in avoiding charge storage effects in the circuits, and give minimum access time; and, (iii) MOS and bipolar circuits integrated on a common chip. Bipolar circuits often require short lifetime e.g. to avoid charge storage problems in the base.

Claims (19)

1. A process for the manufacture of a semiconductor device including the following steps: providing a substrate of semiconductor material, having in intimate contact with its upper surface, a transparent film, the material of this film being mismatched in structure to the material of the substrate and having a higher melting point than that of the substrate; and exposing the substrate through this film to an intense flux of energy of density and duration sufficient to produce in the region of the semiconductor material underlying the film, a reduction in minority carrier lifetime.
2. A process as claimed in claim 1 wherein the flux is a flux of electromagnetic radiant energy produced by a laser source.
3. A process as claimed in claim 2 wherein the substrate is exposed to one or more pulses of intense flux.
4. A process as claimed in claim 3 wherein an extensive area of the semiconductor material is exposed to the energy flux, with a sequenced stepand-shot traverse of the semiconductor substrate relative to the source of energy.
5. A process as claimed in claim 2 wherein the substrate is exposed to an intense flux of continuous energy.
6. A process as claimed in claim 5 wherein an extensive area of the semiconductor material is exposed to the energy flux, by applying a continuous scan of the energy source over and relative to the semiconductor substrate.
7. A process as claimed in either one of the preceding claims, claim 4 or claim 6, wherein part only of the surface of the substrate is covered by transparent film, the extensive area of the semiconductor material exposed, including both covered and uncovered parts, to thereby produce adjacent regions of higher and of lower minority carrier lifetime.
8. A process as claimed in any one of the preceding claims 1 to 7 wherein the substrate is of silicon or doped silicon material.
9. A process as claimed in claim 8 wherein the silicon material is boron doped.
10. A process as claimed in either claim 8 or claim 9 wherein the film is of silicon dioxide.
1 A process as claimed in claim 10 wherein the film is of thickness lying between 300 A and 3000 A inclusive.
12. A process as claimed in claim 1 1 wherein the energy flux is of density lying between 0.5 and 1.5 Joule/cm2 inclusive.
13. A process as claimed in claim 12 wherein the energy flux is of density lying between 0.6 and 0.9 Joules/cm2 inclusive.
14. A process as claimed in claims 12 and 3 wherein the, or each, pulse is of duration of between 10 and 13 nanoseconds inclusive and the flux is of energy density between 0.6 and 0.9 Joules/cm2 inclusive for each pulse.
15. A process as claimed in claim 14 wherein an extensive area of the material is exposed to the energy flux, with a sequenced step-and-shot traverse, a single pulse applied each step.
16. A process as claimed in claim 2 wherein an optic light guide is employed between the source and the substrate to guide laser radiation onto the surface of the substrate and to distribute the radiation homogeneously over the region exposed.
17. A process for the manufacture of a semiconductor device performed substantially as hereinbefore described with reference to and as shown in Figures 1 to 3 of the accompanying drawings.
18. A process for the manufacture of a semiconductor device, performed substantially as hereinbefore described with reference to and as shown in Figures 1 and 4 of the accompanying drawings.
19. A semiconductor device including one or more regions of high minority carrier lifetime, and one or more regions of low minority carrier lifetime, produced by any one process as claimed in the preceding claims.
GB8037170A 1980-11-19 1980-11-19 Semiconductor devices Expired GB2087641B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8037170A GB2087641B (en) 1980-11-19 1980-11-19 Semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8037170A GB2087641B (en) 1980-11-19 1980-11-19 Semiconductor devices

Publications (2)

Publication Number Publication Date
GB2087641A true GB2087641A (en) 1982-05-26
GB2087641B GB2087641B (en) 1985-01-09

Family

ID=10517427

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8037170A Expired GB2087641B (en) 1980-11-19 1980-11-19 Semiconductor devices

Country Status (1)

Country Link
GB (1) GB2087641B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2133618A (en) * 1983-01-05 1984-07-25 Gen Electric Co Plc Fabricating semiconductor circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2133618A (en) * 1983-01-05 1984-07-25 Gen Electric Co Plc Fabricating semiconductor circuits

Also Published As

Publication number Publication date
GB2087641B (en) 1985-01-09

Similar Documents

Publication Publication Date Title
US5688715A (en) Excimer laser dopant activation of backside illuminated CCD&#39;s
US4151008A (en) Method involving pulsed light processing of semiconductor devices
US6051483A (en) Formation of ultra-shallow semiconductor junction using microwave annealing
CN1222016C (en) Method of formation jonctions by laser annealing and rapid thermal annealing
KR100511765B1 (en) Fabrication mehtod for reduced-dimension integrated circuits
JP4166298B2 (en) Method of introducing chemical elements into receiving materials
US6645838B1 (en) Selective absorption process for forming an activated doped region in a semiconductor
US6013566A (en) Method of forming a doped region in a semiconductor substrate
US7737036B2 (en) Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation
US4364778A (en) Formation of multilayer dopant distributions in a semiconductor
KR101124408B1 (en) Linearly focused laser-annealing of buried species
US5840592A (en) Method of improving the spectral response and dark current characteristics of an image gathering detector
JPH0963974A (en) Formation of doped layer in semiconductor substrate
US20090042353A1 (en) Integrated circuit fabrication process for a high melting temperature silicide with minimal post-laser annealing dopant deactivation
US6952269B2 (en) Apparatus and method for adiabatically heating a semiconductor surface
US7863193B2 (en) Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation
GB2087641A (en) Semiconductor devices
US20070022623A1 (en) Laser surface drying
US20140363986A1 (en) Laser scanning for thermal processing
Pai et al. Rapid thermal annealing of Al‐Si contacts
US20020098712A1 (en) Multi-thickness oxide growth with in-situ scanned laser heating
US6204160B1 (en) Method for making electrical contacts and junctions in silicon carbide
Gelpey et al. An overview of ms annealing for deep sub-micron activation
Shibahara et al. Merits of heat assist for melt laser annealing
JPS61163635A (en) Semiconductor impurity doping device

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee