GB2129614A - Method of delineating thin layers of material - Google Patents

Abstract

A method for delineating thin layers of material, e.g. thin oxide layers, is disclosed. A protective layer of electrically conductive material (60), e.g. of polysilicon, is deposited onto the thin layer of material (30) in order to protect the thin layer against any contamination and/or erosion which might occur during subsequent lithographic processing. The protective layer of material is then patterned, e.g. by means of a resist layer (70) in order to delineate the thin layer of material. The method is particularly suited to forming source and drain contact holes in the gate oxide of FETs, by etching a hole or holes through the thin layer (30) and depositing a further electrically conductive material onto the unmasked protective layer and into the hole(s). <IMAGE>

Description

SPECIFICATION Method of delineating thin layers of material The invention relates to the delineation of thin layers of material and has especial application to the fabrication of information processing devices.

The fabrication of many information processing devices, e.g. electronic devices, integrated circuits and magnetic bubble devices, involves the formation of a relatively thin layer of material, e.g. a thin oxide layer, on a second material such as a semiconductor material, and the subsequent patterning of the thin layer of material. Typically, this patterning is accomplished by depositing a resist onto the thin layer of material, patterning the resist, etching the thin layer of material using the patterned resist as an etch mask, and then removing the resist with, for example, solvents or plasma etchants.

Included among the information processing devices which undergo such a fabrication procedure are many MOS (metal-oxide-semiconductor) integrated circuits (the term integrated circuit, as used herein, denotes a plurality of interconnected devices), e.g. MOS logic circuits. These MOS integrated circuits (ic's) include a plurality of MOSFETs (metal-oxidesemiconductor field effect transistors), each of which includes an active surface layer semiconductor material, a relatively thin gate oxide (GOX) formed on the surface of the active layer, a conducting gate of, for example, doped polysilicon, formed on the surface of the GOX, and two relatively heavily doped portions of the active layer, on opposite sides of the gate, which constitute the source and drain of the MOSFET.The MOSFETs are separated and electrically insulated from one another by a relatively thick (compared to the GOX) field oxide (FOX). In addition, there are conducting polysilicon runners extending from the gates of selected MOSFETs to polysilicon contacts, called polycons, extending through the thin GOXs to the sources or drains of other MOSFETs.

Currently, the MOS ic's described above are fabricated by forming the relatively thin GOXs and relatively thick FOX on the surface of the active layer of the ic. The relatively thick FOX separates GOX-covered surface areas of the active layer, called GASAD (gate-and-sourceand-drain) areas, where the MOSFETs are to be formed. Polysilicon source and drain contacts (polycons) are formed by depositing a resist, for example, an organic photoresist, onto the GOXs and FOX, opening windows in the resist to expose portions of the GOXs overlying selected GASAD areas, and then etching holes through the exposed portions of the GOXs to the underlying active layer, using the patterned resist as an etch mark.After removing the resist with chemical solvents or with a plasma etchant, a layer of polysilicon is deposited onto the GOXs and FOX, and thus polysilicon is deposited into the holes extending through the GOXs (overlying the selected GASAD areas) to the active layer. The polysilicon in the holes contacting the active layer are the polycons. The deposited layer of polysilicon is then patterned to form polysilicon gates in the GASAD areas, and to form the polysilicon runners extending from the gates in certain GASAD areas to polycons extending through the thin GOXs to regions (for example, source and/or drain regions) of the active layer beneath other, selected GASAD areas.

An undesirable feature of the fabrication procedures described above is the fact that the thin layers of material, e.g. the thin GOXs, are directly contacted by a resist. Consequently, these thin layers of material are potentially contaminated by the resist and are undesirably reduced in thickness because they are subjected to the etching action of the chemical solvents or plasmas which are used to remove the resist. The undesirable thinning of the thin layers of material, produced during the removal of the resists, is particularly significant for layers thinner than about 500 Angstroms.

As a consequence of the adverse effects of current processing techniques, new methods have been sought, thus far without success, for fabricating information processing devices, which methods do not involve contacting a thin layer of material, such as a thin GOX, with a resist.

In the invention as claimed a conductive protective layer is formed between the thin insulative layer and the maskig layer and thus protects the thin insulative layer from undesirable contamination and thinning.

Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which :- Figures 1-5 are sectional views, at different stages of fabrication, of an electronic component (having a thin gate oxide) being fabricated in accordance with the invention.

The process to be described is suitable for fabricating information processing devices which include relatively thin (less than about 500 Angstroms thick, and preferably less than about 400 Angstroms thick) layers of material e.g. thin oxides, which are delineated during the fabrication of the devices. Devices which include a thin layer of material (delineated during the fabrication of the device) are fabricated by depositing a protective layer of material onto the thin layer of material. Alternatively, two or more protective layers are deposited onto the thin layer of material. Then the thin layer of material is delineated by patterning the protective layer (or layers) of material.This patterning step is accomplished, for example, by forming a patterned masking layer, e.g. a patterned resist, on the surface of the protective layer (or layers), and then etching the protective layer (or layers) using the masking layer as an etch mask.

Having been delineated, the thin layer of material is then, for example, patterned, using the patterned protective layer (or layers) as an etch mask. Alternatively, for example, patterned contacts to the thin layer of material are formed by depositing a layer of contact material onto the patterned protective layer (or layers). The contact material is thus also deposited into the holes in the protective layer (or layers), and into contact with the thin layer, resulting in the formation of the patterned contacts. The patterned protective layer (or layers) is, for example, incorporated into the device undergoing fabrication.

Among the materials which are useful for protecting thin layers of material, e.g. thin oxide layers such as thin layers of a silicon oxide, e.g. SiO2, is polysilicon. The protective polysilicon layer may be deposited onto a thin layer of material by conventional low-pressure chemical vapour deposition techniques. The thickness of the protective polysilicon layer is advantageously in the range from about 1000 to about 2000 Angstroms. A thickness less than about 1000 Angstroms is undesirable because the incidence of pinholes and defects in the protective polysilicon layer will generally be undesirably high. On the other hand, a thickness greater than about 2000 Angstroms is undesirable because such a layer of polysilicon requires an undesirably long time to etch through its thickness during the patterning of the polysilicon layer.However, if longer etch ing times are acceptable, then thicker layers are not precluded.

Other materials which are useful for protect ing thin layers of material include refractory metals such as tungsten or molybdenum. The thickness of a protective refractory metal layer is advantageously in the range from about 500 to about 2000 Angstroms. Thicknesses outside this range are undesirable for the same reasons as those given above, and thick nesses greater than about 2000 Angstroms are not precluded if longer etching times are acceptable.

Both the protective layer (or layers) and the underlying thin layer are patterned by conventional techniques such as wet chemical etch ing, plasma etching, and reactive sputter etch ing. If, for example, the thin layer of material is a thin layer of SiO2 (which is to be delin eated), and the protective layer is a layer of polysilicon, then the polysilicon layer is readily etched (through a patterned masking layer), without the SiO2 layer being significantly affected, by reactive sputter etching the polysili con in a Cl2 plasma. A useful Cl2 plasma is produced by flowing Cl2 gas into, for example, a parallel-plate reactive sputter etching machine at a flow rate of about 10 to about 20 cc/minute, while maintaining the pressure within the reactor chamber at about 5 to about 10 millitorr and by maintaining the power density in the range 0.1 to about 0.4 watts/cm2.The ratio of the etch rates of the polysilicon layer relative to the SiO2 layer in such a Cl2 plasma is typically about 30-to-1.

While the Cl2 plasma described above is also useful for sputtering the SiO2 layer (using the patterned polysilicon layer as an etch mask), the sputtering is relatively slow (less than about 1 0 Angstroms/minute). Preferably, when patterning the SiO2 layer (using the patterned polysilicon layers as an etch mask), the Sl02 layer is etched, without significantly affecting the polysilicon layer, by reactive sputter etching the SiO2 in a CHF3 plasma. A useful CHF3 plasma is produced by flowing CHEF, into the reactive sputter etching machine at a flow rate of about 15 to about 20 cc/minute, while maintaining the pressure within the reactor chamber at about 60 to about 70 millitorr and by maintaining the power density in the range 0.1 to about 0.2 watts/cm2.The etch rate of the SiO2 layer in such a CHEF, plasma is typically about 500 Angstroms/minutes, while the etch rate of the SiO2 layer relative to the polysilicon layer is typically about 50-to-1.

During the patterning of the polysilicon and SiO2 layers, the SiO2 layer is never contacted by the masking layer on the surface of the polysilicon layer, and thus the SiO2 layer avoids undesirable contamination and thinning.

The invention is not limited to s#pecific information processing devices, to specific protective layers, or specific protected layers. However, as a pedagogic aid, the fabrication of an MOS ic using the inventive process is described below.

With reference to Fig. 1 an MOS ic which includes polycons, e.g. a VLSI (very large scale integrated) MOS ic, is fabricated by forming relatively thin GOXs 30 and a relatively thick FOX on the surface of a layer of doped semiconductor material 20. The layer 20 constitutes the surface active layer of a substrate 10 of semiconductor material. The relatively thick FOX 40 separates the GOXcovered GASAD areas 50, on the surface of the layer 20, where MOSFETs are to be formed. If, for example, the active layer 20 is of silicon, then the GOXs 30 and the FOX 40 will typically be, respectively, relatively thin and thick layers of SiO2. The FOX 40 is formed, for example, by thermally oxidizing the surface of the layer 20. After opening windows in the FOX (by conventional techniques) to expose the GASAD areas 50 on the surface of the layer 20, the GOXs 30 are formed, for example, by again thermally oxidizing the surface of the layer 20. For VLSI MOS ic's the thickness of the SiO2 GOXs 30 ranges from about 50 to about 400 Angstroms, and is preferably about 250 Angstroms. A thickness of the GOXs 30 less than about 50 Angstroms is undesirable because this results in the gate threshold voltages (the minimum voltages across the MOSFET gates which produce a detectable change in the currents within the current channels of the MOSFETs) becoming so low that it is difficult to regulate current flow.On the other hand, thicknesses greater than about 400 Angstroms are undesirable because undesirably high voltages must be applied across the gates of the MOSFETs to regulate the currents within the MOSFET current channels.

The thickness of the SiO2 FOX 40 of the VLSI MOS ic's ranges from about 3000 to about 4000 Angstroms, and is preferably about 3500 Angstroms. A thickness less than about 3000 Angstroms is undesirable because the FOX might not be thick enough to prevent the inversion of the underlying silicon and the resulting electrical conduction between the two GASAD regions which should be electrically isolated from one another. On the other hand, a thickness greater than about 6000 Angstroms is undesirable because the FOX thus forms undesirably high steps which are difficult to cover with other materials during subsequent processing, and it is difficult to etch away the material at these high steps.

After the GOXs 30 and the FOX 40 of the ic are formed, a protective layer 60 of polysilicon is deposited onto the GOXs and FOX of the ic, as shown in Fig. 2. The polysilicon layer 60 is deposited, for example, by conventional low pressure chemical vapour deposition techniques. The purpose of the polysilicon layer 60 is to protect the underlying GOXs 30 from any contamination and erosion which might occur during subsequent lithography. The thickness of the polysilicon layer 60 ranges from about 1000 to about 2000 Angstroms, and is preferably about 1500 Angstroms. A thickness less than about 1000 Angstroms is undesirable because the incidence of pinholes and defects in the polysilicon will be undesirably high.On the other hand, a thickness greater than about 2000 Angstroms is undesirable because such a layer of polysilicon requires an undesirably long time to etch through its thickness during the subsequent step of etching holes through both the polysilicon layer 60 and selected GOXs 30. However, if longer etching times are acceptable, then thicker layers are not precluded.

A patternable masking layer 70, e.g. the trilevel resist described by J. M. Moran and D.

Maydan in "High Resolution, Steep Profile, Resist Patterns", The Bell System Technical Journal, Volume 58, No. 5, May-June 1979, pp. 1027-1036, is deposited onto the polysilicon layer 60, and the masking layer is patterned, i.e. windows are opened in the masking layer to expose portions of the polysilicon layer 60 overlying the GOXs of selected GASAD areas. Thereafter, holes 80 are etched through the exposed portions of the polysilicon layer 60 and through the underlying GOXs 30 to the active layer 20 (using the patterned layer 70 as an etch mask), as shown in Fig. 3. The etching of these holes 80 is achieved, for example, by reactive sputter etching the polysilicon layer 60 in a Cl2 plasma (described above), and reactive sputter etching the GOXs 30 in a CHF3 plasma (described above).The high polysilicon-to-SiO2 etch selectively of the Cl2 plasma substantially precludes the SiO2 GOXs 30 from being etched by the Cl2 plasma, while the high SiO2to-silicon etch selectively of the CHEF, plasma substantially precludes the polysilicon layer 60 and (silicon) active layer 20 from being etched by the CHF3 plasma. Then the masking layer 70 is removed with, for example, conventional chemical solvents such as H2-S04, or by conventional plasma etching methods.

At the completion of the lithography procedure, described above, a second layer 90 of polysilicon is deposited onto the first layer 60, and thus polysilicon is also deposited into the holes 80 and into contact with the active layer 20. It is the polysilicon in the holes 80 contacting the layer 20 which constitute the polycons 100 to the active layer 20 beneath the selected GASAD areas. This is shown in Fig. 4. The second layer 90 is deposited, for example, by conventional low pressure chemical vapour deposition techniques.

The thickness of the second layer 90 ranges from about 1500 to about 2500 Angstroms, and is preferably about 2000 Angstroms. The specified thickness range for the layer 90, in combination with the specified thickness range for the layer 60, results in the combined thickness of the polysilicon layers 60 and 90 ranging from about 2500 to about 4500 Angstroms. Because the polysilicon layers 60 and 90 are later patterned to form the polysilicon gates of the ic, the gates will have a thickness ranging from about 2500 to about 4500 Angstroms. A thickness of the polysilicon gates less than about 2500 Angstroms is undesirable because this will result in the gates having an undesirably high sheet resistance.On the other hand, a thickness of the polysilicon gates greater than about 4500 Angstroms is undesirable because this will result in the polysilicon gates being so tall that sidewall capacitance becomes undesirably large.

The two polysilicon layers 60 and 90, and consequently the polycons 100 formed by the deposition of the second polysilicon layer 90, are now doped (using conventional techniques) with an appropriate n- or p-dopant (depending on whether the active layer 20 is of n-type or p-type conductivity). The doping of the polysilicon layers 60 and 90 is useful in producing high conductivity gates (the polysilicon layers are patterned to form the gates), while the doping of the polycons 100 produces good electrical contacts to the active layer 20. The dopant also diffuses through the polycons 100, as shown in Fig. 4, to form relatively highly doped regions 110 of the active layer 20, e.g. portions of the sources or drains of the MOSFETs whose GOXs have been pierced by the polycons.Thereafter, the two polysilicon layers 60 and 90 are patterned, by conventional techniques, to form MOSFET gates 120 in the GASAD areas 50, and to form polysilicon runners 130 extending from the polysilicon gates 120 in selected GASAD areas, to the polycons 100 extending through the GOXs to the active layer beneath other selected GASAD areas, as shown in Fig.

5.

The steps involved in completing the MOS ic are conventional. That is, self-aligned source and drain regions are formed on the opposite sides of the gates (by conventional techniques), and an insulating layer, e.g. a layer of SiO2, is deposited onto the ic. Conventional lithographic techniques are then used to open windows in the insulating layer to expose the gates and the source and drain regions of the ic. Finally, a layer of metal, e.g.

copper-doped aluminium, is deposited onto the ic (and thus metal is deposited into the holes extending through the insulating layer to form metallic contacts to the gates and the source and drain regions), and the layer of metal is then patterned to form metallic runners.

In the event that composite, metal silicideon-polysilicon gates are desired, e.g. tantalum silicide-on-polysilicon gates, then the above fabrication procedure is modified by forming a metal silicide layer on the two polysilicon layers after the polysilicon layers have been doped. Thereafter, both the silicide layer and the polysilicon layers are patterned to form metal silicide-on-polysilicon gates and metal silicide-on-polysilicon runners extending from selected gates to the polycons.

It should be noted that an extremely thin layer of SiO2, typically about 10 Angstroms thick, tends to form on the surface of the first polysilicon layer 60 prior to the deposition of the second polysilicon layer 90, during the course of the method. Thus, the polysilicon gates, as well as the polycons, formed in accordance with the method typically include two layers of polysilicon separated by a thin boundary layer of SiO2. This thin boundary layer of SiO2 is detectable, for example, in transmission electron micrographs (of crosssections) of ic's made in accordance with the invention. However, this boundary layer of SiO2 is so thin (compared to the two layers of polysilicon), and the quantity of SiO2 is so small (compared to the quantity of polysili con), that the SiO2 has no detectable adverse effect on the conductance of the polysilicon gates and polycons.

Example The method was used to fabricate a VLSI MOS logic circuit which included ring oscilla tors, line drivers, shift registers, 4-bit adders, and other devices. This VLSI MOS logic cir cuit, which also included polycons, was fabri cated using 1#m, 1 1/2cm, and 2#m design rules.

The method was initiated by growing a FOX of SiO2, about 3500 Angstroms thick, on the surface of a 7.5 cm (three-inch) silicon wafer.

This FOX was grown by thermally oxidizing the silicon wafer in a wet (H20) environment.

In order to form the active layer of the logic circuit, and in order to define the dopant concentration at the silicon-FOX interface (which is one of the parameters which deter mines the threshold voltage for the gates of the enhancement mode MOSFETs of the logic circuit), the FOX-covered silicon wafer was implanted with boron atoms at a dosage of about 2 x 1012cm~2. The energy of the boron atoms, which was about 170 keV, was enough to ensure that the boron atoms would penetrate the FOX to the silicon-FOX interface.

The GASAD areas on the surface of the wafer were then exposed by opening windows in the FOX using conventional lithographic techniques. These windows (and thus the GASAD areas) were about 7ym in length and about 15,um in width.

A GOX of SiO2, about 250 Angstroms thick, was grown on the surface of each of the GASAD areas by heating the wafer for about 15 minutes at about 1000 C in an O2-HCl (3% HCI) ambient. Then the wafer was an nealed in an Argon atmosphere for about 15 minutes and at about 1000 C in order to reduce the fixed charge within the SiO2. This heat treatment also activates the boron im plant (the boron atoms displace silicon atoms in the silicon crystal lattice as a result of the Argon annealing step).

A first layer of polysilicon, about 1500 Angstroms thick, was then deposited onto the wafer using conventional low pressure chemi cal vapour deposition techniques. Then a 1.8,um-thick organic resist, sold under the trade name HPR-204 resist by the Philip A.

Hunt Chemical Corporation of Palisades Park, New Jersey, was spun onto the wafer and baked for about 120 minutes at about 210 C.

A layer of SiO2, about 1200 Angstroms thick, was then plasma deposited onto the organic resist, and a layer of DCOPA (90% dichloro propyl-acrylate and 10% copolymer) x-ray re sist, about 3500 Angstroms thick, was then deposited onto the 1200-Angstrom-thick layer of SiO2 by spinning.

After aligning the polycon-level mask over | the GASAD areas, the DCOPA x-ray resist was exposed for about 5 minutes to 4.37 Angstrom x-ray radiation. The intensity of the radiation was about 75,uwatts/cm2. The x-ray resist was developed with a wet developer which included isopropyl alcohol and methylethylketone. Then, the 1200-Angstrom-thick layer of SiO2 was patterned, using the patterned x-ray resist as an etch mask, by reactive sputter etching the wafer in a CHF3 plasma. The CHF3 plasma was formed by flowing CHF3 into the reactor chamber at a flow rate of about 79 cc/minute while maintaining the pressure within the reactor chamber at about 10 millitorr and while maintaining the power density at about 0. 1 watts/ cm2.Finally, the HPR-204 resist was patterned, using the patterned layers of x-ray resist and SiO2 as an etch mask, by reactive sputter etching the wafer in an 02-CF4 (1 % CF4) plasma. This 02-CF4 plasma was formed by flowing a mixture of 02 and CF4 (1 % CF4) into the reactor chamber at a flow rate of about 83 cc/minute while maintaining the pressure within the reactor chamber at about 4 4 millitorr and while maintaining the power density at about 0.2 watts/cm2.

Holes were then etched through the polysilicon layer (the holes were located over those GASAD areas where polycons were desired), using the patterned resist as an etch mask, by reactive sputter etching the polysilicon layer in a Cl2 plasma for about 5 minutes. This etching, which took place in a parallel plate, reactive sputter etching machine, was achieved by flowing Cl2 gas into the reactor chamber at about 20 cc/minute while maintaining the total pressure within the reactor chamber at about 5 millitorr and the power density at about 0.3 watts/cm2. Then, holes were etched through the GOXs where polycons were desired, using the patterned polysilicon layer as an etch mask, by reactive sputter etching the wafer (in the parallel plate reactive sputter etching machine) in a CHF3 plasma.

During this last etching step CHEF, was flowed into the reactor chamber at about 18 cc/minute while the total pressure within the reactor chamber was maintained at about 68 millitorr and the power density was maintained at about 0.2 watts/cm2.

The HPR-204, SiO2, and DCOPA x-ray resist were then stripped from the surface of the wafer by applying a solution of sulphuric acid and hydrogen peroxide to the wafer, while maintaining the ambient temperature at about 80 C. The wafer surface was also cleaned with conventional chemical solutions, which included HF, to remove any remaining deposits of the resist.

A A second layer of polysilicon, about 2500 Angstroms thick, was then deposited onto the surface of the wafer, using conventional low pressure chemical vapour deposition techniques. As a result, polysilicon was deposited into the holes extending through the first polysilicon layer and the GOXs to the underlying silicon, resulting in the formation of the polycons.

The two polysilicon layers and the polycons were then doped with phosphorus by placing the wafer within a conventional PBr2 source furnace for about 60 minutes. The temperature of the furnace was maintained at about 950 C. This phosphorus diffusion step resulted in the polysilicon layers and the polycons achieving n±type conductivity (the doping level was about 1020cm-3). In addition, phosphorus was also driven into the silicon regions surrounding the polycons, resulting in the partial formation of the source or drain regions of the MOSFETs whose GOXs had been pierced by the polycons.

The remaining steps in the fabrication of the VLSI MOS logic circuit were conventional, and are described by Watts et al in an article entitled "Electron Beam Lithography For Small MOSFETs", IEEE Transactions Electron Devices, November 1981, Volume ED-28, No. 11, p. 1338.

Claims (11)

1. A method of delineating a thin insulative layer over a semiconductor body comprising forming a conductive protective layer over the thin layer, forming a masking layer over the protective layer, selectively removing portions of the masking layer, selectively etching the protective layer using the masking layer as a mask, selectively etching the insulative layer and removing the masking layer.

2. A method as claimed in claim 1 wherein the thin insulative layer has a thickness of less than 400 Angstrom units.

3. A method as claimed in claim 1 or claim 2 wherein the thin insulative layer is of SiO2 and the semiconductor body is of silicon.

4. A method as claimed in any of the preceding claims wherein the masking layer is a resist layer which is removed by chemical etching or plasma etching.

5. A method as claimed in any of the preceding claims wherein the protective layer is a layer of polysilicon.

6. A method as claimed in claim 5 wherein the polysilicon layer has a thickness ranging from 1000 to 2000 Angstrom units.

7. A method as claimed in any of claims 1 to 4 wherein the protective layer of material is a layer of refractory metal.

8. A method as claimed in any of the preceding claims wherein a hole is etched through the protective layer and the insulative layer and, after removal of the masking layer, a second conductive layer is formed over the protective layer so as to extend through the hole and form a contact to the semiconductor body.

9. A method as claimed in claim 8 wherein the thin insulative layer constitutes the gate insulators of field effect devices, and the conductive layer and the second conductive layer are etched to form the gate electrodes of the devices and conductors interconnecting selected gate electrodes with selected said contacts.

10. A method of delineating a thin insulative layer substantially as herein described with reference to the drawings.

11. A method of delineating a thin insulative layer substantially as herein described with reference to the example.