GB1572020A - Formation of silicon patterns on semiconductor devices - Google Patents
Formation of silicon patterns on semiconductor devices Download PDFInfo
- Publication number
- GB1572020A GB1572020A GB1915877A GB1915877A GB1572020A GB 1572020 A GB1572020 A GB 1572020A GB 1915877 A GB1915877 A GB 1915877A GB 1915877 A GB1915877 A GB 1915877A GB 1572020 A GB1572020 A GB 1572020A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- silicon
- etching
- parts
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 33
- 229910052710 silicon Inorganic materials 0.000 title claims description 33
- 239000010703 silicon Substances 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 238000000034 method Methods 0.000 claims description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000001311 chemical methods and process Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 claims description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 2
- 239000000470 constituent Substances 0.000 claims description 2
- 229910052740 iodine Inorganic materials 0.000 claims description 2
- 239000011630 iodine Substances 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- 229910017604 nitric acid Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 4
- 241000206607 Porphyra umbilicalis Species 0.000 description 3
- 238000000197 pyrolysis Methods 0.000 description 3
- 238000003631 wet chemical etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Description
( > 4) IMPROVEMENTS IN OR RELATING TO THE
FORMATION OF SILICON PATTERNS ON SEMICONDUCTOR DEVICES
(71) We. the POST OFFICE. a British corporation established by Statute. of 23 Howland Street. London WIP 6HO. do hereby declare the invention. for which we pray that a patent may be granted to us, and the method by which it is to be performed. to be particularly described in and bv the following statement:
This invention relates to the formation of silicon patterns on semiconductor devices.
Polvsilicon is currently used for forming a self aligning gate electrode in silicon semiconductor devices such as silicon gate unipolar devices. It is also used as an electrical interconnecting medium in such integrated circuits. The polysilicon is deposited on top of a gate oxide layer (the gate dielectric) which is in turn formed on a silicon substrate. The polvsilicon can be deposited on the device by pyrolysis of silane (SiH4) in a nitrogen carrier gas. The patterns required for the gate electrode and the interconnections are then produced in the polxsilicon layer by photolithographically defining a protective mask on the polysilicon laver. The unprotected areas are removed by a wet chemical etching procedure using a suitable etching solution to leave the desired polysilicon pattern. This tvpe of process invariably produces a polvsilicon patterned layer in which the edges of the pattern are vertical. Furthermore the etching process can under cut the protective mask so that an area of polvsilicon greater than the area defined by the mask is etched awav.
It has recently been realised that it may not always be desirable to have a polysilicon pattern with vertical edges. One reason for this is that any layers deposited on top of the polysilicon are subject to stresses at cross-over points with the polysilicon and this can tend to cause micro cricks in the layers. Furthermore. if the next step in the processing of a semiconductor device is thermal oxidation of the polysilicon laver. experience has shown that if the layer has a tapered or bevelled edge the tendency of oxide to grow under the perimeter of the polvsilicon pattern is reduced.
One known technique for producing a polvsilicon pattern with tapered or bevelled edges involves rounding the edges of the masking photoresist pattern with a high temperature post-bake. The unmasked polysilicon is then removed by using a reactive ion-etching technique.
We ha'e developed a method of producing a bevelled edge to the polysilicon pattern which allows a standard wet chemical etching technique to be employed. Our method involves forming a first layer of polycrvstalline silicon on the semiconductor device and then forming a second layer of amorphous silicon on the first layer. When the two layers are etched a bevelled edge is automaticallv produced in the polycrystalline layer. This method stems from the realisation that it is possible to produce either an amorphous silicon layer or a polycrystalline silicon layer by appropriatelv selecting the temperature of deposition of the silicon. The etch rate of amorphous silicon is several times greater than that of polvcr4talline silicon and this results in the formation of the bevelled edge to the polycrystalline layer when the two layers are etched.
According to the present invention there is provided a method of forming a patterned silicon laer on a semiconductor device. said method comprising forming a first layer of polycrystalline silicon on the semiconductor device. forming a second layer of amorphous silicon on said first layer and producing the desired pattern in the silicon layers using a photolithographic etch technique. The wedge portions of the polycrvstalline part of the silicon pattern produced bv such a method are bevelled. Usually the thickness of the polycrvstalline silicon layer is greater than that of the amorphous silicon layer. After the etching step the amorphous layer can be converted to a polycrystalline layer or alternatively it can be removed by an etch back technique.
The etching of the silicon may be carried out using a wet chemical technique.
The invention also provides a semiconductor device having a silicon layer produced by the method defined above.
The invention will be described now by way of example only with particular reference to the accompanying drawings. In the drawings: Figure I is a section through a semiconductor device prior to treatment by the present method. and flgiire 2 is a similar section illustrating the device after treatment by the present method.
Referring to Figure 1 a semiconductor device comprises a silicon substrate 10 on which is formed an oxide layer 11. A layer 12 of polycrystalline silicon is formed on the oxide layer Il. The layer of polycrystalline silicon is deposited on the oxide layer 11 by pyrolysis of silane in nitrogen at a temperature above approximately 650"C. A layer 14 of amorphous silicon is formed on the layer 12 of polycrystalline silicon. The amorphous layer 14 is formed by pyrolvsis of silane in nitrogen gas at a temperature below approximately 640"C. Pvrolysis of silane in nitrogen at a temperature below approximately 640 C results in the formation of amorphous silicon, whilst pyrolysis of silane in nitrogen above approximately 650 C results in polycrystalline silicon being formed.
To produce the desired pattern in the silicon layers a photolithographic mask 16 is formed on the amorphous layer 14. The mask is formed by conventional techniques and defines the desired silicon pattern. The unmasked areas of the silicon layers are then etched awav bv a wet chemical etch process using a CP4a based etch ant. The etch rate of the amorphous silicon layer 14 is much greater than the etch rate of the polycrystalline silicon layer 12. This results in a rapid side-ways etching in the amorphous layer taking place during the time required to etch through the polycrystalline layer. Thus under cutting of the masking layer occurs and promotes bevelling of the crystalline silicon layer edges at an angle of approximately 45 . The result is shown in Figure 2. The amorphous layer 14 has relatively steep vertical sides after the etching step.
The amorphous layer 14 can then be treated in one of two ways. If the relatively small vertical edges of the amorphous layer are acceptable in the semiconductor device being formed, although steep edges throughout the whole of the polysilicon layer are not acceptable, then the amorphous layer may be converted into the polycrystalline form at the next processing stage. Amorphous silicon can be converted to the polycrystalline form by a five minute anneal at 9500C in nitrogen. The conversion would normallv occur as a matter of course as the next operation following production of the polysilicon pattern is generally a high temperature (above about 90() C) furnace process.
Alternativelv. if a small vertical edge is not acceptable, the amorphous layer 14 can be removed after the bevelling has been carried out. This can be done using an etch back technique after the masking layer 16 has been removed. The etch back consists of immersing the device in polysilicon etchant once again for a period just sufficient to remove the amorphous layer. Because the amorphous layer etches much faster than the polycrystalline laver. the polycrystalline layer is relatively unaffected by the etch back. For some devices a polvsilicon etch back is alreadv included as a routine processing step and therefore the amorphous layer would be removed automatically. It should be noted that when an etch back technique is employed the crystalline layer 12 should be formed with a thickness equal to the thickness of silicon required in the finished device.
In some photolithographic masking svstems a deposited oxide layer is used as a patterning medium for cutting the polysilicon layer. The use of the amorphous polycrystalline layer imposes the restriction that this oxide should be a low temperature (less than 600 C) deposited oxide and not a furnace oxide or high temperature (above about 64()C) deposited oxide. This is to avoid unintentional crystallisation of the amorphous layer during processing.
The present technique can be used to produce completely bevelled edges using the polysilicon etch back method for removing the amorphous layer. Bevelled edges produced in this way appear well suited for use in the manufacture of large scale integrated circuits. In some applications the vertical wall in the top part of the silicon layer does not present a problem. For example. in some cases the problem is oxide undergrowth around the edge of the polysilicon pattern at a later stage in the process. This problem is apparently overcome by use of bevelled edges at the lower part of the layer and small vertical portions at the upper part of the layer would be quite acceptable.
Use of the two silicon layers in conjunction with a wet chemical etching technique is advantageous in situations where bevelled polysilicon edges are required. Because tapering occurs automatically as a result of the formation of the two silicon layers, bevelled and unbevelled polysilicon layers may follow identical processing paths during the photolithog raphic stages and polysilicon etching. Thus there is no requirement for further capital plant or photolithographic expertise. The use of a low temperature deposited oxide as the protective mask for defining the polysilicon pattern to be etched is quite common and therefore the restriction from using high temperature patterning oxides is not a special one.
Furthermore wet etching techniques are relatively inexpensive compared with reactive ion etching techniques.
In one example of the present method the CP4a based etchant has the following constituents:
Part A 5 parts nitric acid 63'wiz 3 parts hydrofluoric acid 40% 3 parts acetic acid 60z/c Part B 3 gms of iodine in
500 ml of acetic acid 606iF Parts A and B are stored separatelv and mixed as I part A and 2 parts B when required although other mixing ratios can be used.
WHAT WE CLAIM IS:
1. A method of forming a patterned silicon layer on a semiconductor device, said method comprising forming a first layer of polycrystalline silicon on the semiconductor device, forming a second layer of amorphous silicon on the first layer, and producing a desired pattern in the silicon layers using a photolithographic etch technique, the resulting edge portions of the polvcrystalline silicon layer being bevelled.
2. A method as claimed in claim 1 wherein the thickness of the polycrystalline silicon laxer is greater than the thickness of the amorphous silicon layer.
3. A method as claimed in claim l or claim 2 wherein, after said etching step, the amorphous silicon is converted to polycrystalline silicon.
4. A method as claimed in claim I or claim 2 wherein. after said etching step. the amorphous silicon is removed bv an etch back technique.
5. A method as claimed in any preceding claim, wherein the etching of the silicon is carried out using a wet chemical technique.
6. A method of forming a patterned silicon layer on a semiconductor device substantially as hereinbefore described.
7. Semiconductor devices whenever prepared by the method claimed in any preceding
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (7)
- **WARNING** start of CLMS field may overlap end of DESC **.raphic stages and polysilicon etching. Thus there is no requirement for further capital plant or photolithographic expertise. The use of a low temperature deposited oxide as the protective mask for defining the polysilicon pattern to be etched is quite common and therefore the restriction from using high temperature patterning oxides is not a special one.Furthermore wet etching techniques are relatively inexpensive compared with reactive ion etching techniques.In one example of the present method the CP4a based etchant has the following constituents: Part A 5 parts nitric acid 63'wiz3 parts hydrofluoric acid 40%3 parts acetic acid 60z/c Part B 3 gms of iodine in500 ml of acetic acid 606iF Parts A and B are stored separatelv and mixed as I part A and 2 parts B when required although other mixing ratios can be used.WHAT WE CLAIM IS: 1. A method of forming a patterned silicon layer on a semiconductor device, said method comprising forming a first layer of polycrystalline silicon on the semiconductor device, forming a second layer of amorphous silicon on the first layer, and producing a desired pattern in the silicon layers using a photolithographic etch technique, the resulting edge portions of the polvcrystalline silicon layer being bevelled.
- 2. A method as claimed in claim 1 wherein the thickness of the polycrystalline silicon laxer is greater than the thickness of the amorphous silicon layer.
- 3. A method as claimed in claim l or claim 2 wherein, after said etching step, the amorphous silicon is converted to polycrystalline silicon.
- 4. A method as claimed in claim I or claim 2 wherein. after said etching step. the amorphous silicon is removed bv an etch back technique.
- 5. A method as claimed in any preceding claim, wherein the etching of the silicon is carried out using a wet chemical technique.
- 6. A method of forming a patterned silicon layer on a semiconductor device substantially as hereinbefore described.
- 7. Semiconductor devices whenever prepared by the method claimed in any preceding
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1915877A GB1572020A (en) | 1978-04-26 | 1978-04-26 | Formation of silicon patterns on semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1915877A GB1572020A (en) | 1978-04-26 | 1978-04-26 | Formation of silicon patterns on semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1572020A true GB1572020A (en) | 1980-07-23 |
Family
ID=10124733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1915877A Expired GB1572020A (en) | 1978-04-26 | 1978-04-26 | Formation of silicon patterns on semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1572020A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2129614A (en) * | 1982-10-29 | 1984-05-16 | Western Electric Co | Method of delineating thin layers of material |
| CN108538966A (en) * | 2018-04-18 | 2018-09-14 | 晋能光伏技术有限责任公司 | A kind of deficient manufacturing procedure rework preocess method after efficient heterojunction battery CVD |
-
1978
- 1978-04-26 GB GB1915877A patent/GB1572020A/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2129614A (en) * | 1982-10-29 | 1984-05-16 | Western Electric Co | Method of delineating thin layers of material |
| CN108538966A (en) * | 2018-04-18 | 2018-09-14 | 晋能光伏技术有限责任公司 | A kind of deficient manufacturing procedure rework preocess method after efficient heterojunction battery CVD |
| CN108538966B (en) * | 2018-04-18 | 2023-11-03 | 晋能光伏技术有限责任公司 | Poor reworking process method for high-efficiency heterojunction battery CVD (chemical vapor deposition) post-process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |