DE3339268A1 - METHOD FOR PRODUCING AN INTEGRATED CIRCUIT WITH A THIN ISOLATING LAYER - Google Patents

Description

description

Method of manufacturing an integrated circuit with a thin insulating layer

The invention relates to a method for producing an integrated Circuit according to the preamble of claim 1.

The manufacture of many integrated circuits involves the formation of a relatively thin layer of material, such as a thin one Oxide layer, on a second material such as a semiconductor material, and then forming a pattern in the thin layer of material. This pattern formation is usually done by applying a resist material to the thin Material layer, forming a pattern in the resist material, etching the thin material layer using the with a Patterned resist material layer as a mask, and then Removal of the resist layer, the last-mentioned step, for example, with solvents or with plasma etchants is carried out. Among the information processing devices which such a manufacturing process takes place, there are many MOS (metal-oxide-semiconductor) ICs (integrated circuits; this term denotes) here several interconnected components), e.g. logi-

see MOS circuits. These MOS Integrated Circuits (ICs) contain several MOSFETs (metal-oxide-semiconductor field effect transistors), each of which has an active surface Semiconductor material layer / a relatively thin gate oxide layer (GOX) on the surface of the active layer and a formed on the surface of the GOX, e.g. from doped polysilicon having existing conductive gate. In addition, there are two relatively heavily doped sections of the active layer provided on opposite sides of the gate / which form the source and drain of the MOSFET.

The MOSFETs are interconnected by a relatively thick field oxide layer (FOX) separated and electrically isolated from each other. In addition, there are polysilicon lines leading from the gates certain MOSFETs to polysilicon contacts, also called Polycons which extend through the thin gate oxide layers to the source,, and drain electrodes of other MOSFETs extend.

At present, the above-described MOS ICs are manufactured by that on the surface of the active layer of the IC the relatively thin gate oxides and relatively thick field oxides are formed will. The relatively thick field oxide separates surface areas of the active layer that are covered with gate oxide, which also are referred to as GASAD (gate-and-source-and-drain) areas where the MOSFETs are to be formed. The polycons are

formed by a resist material on the gate oxides and the field oxide, for example, an organic photoresist material is deposited, and windows are formed in the resist material be to sections of the selected GASAD land areas to expose covering gate oxide. Then, through the exposed portions, the gate oxide becomes the active one underneath Layer holes are etched using the patterned resist material as an etching mask. After removing the resist material by means of chemical solvents or by plasma etching, a polysilicon layer is applied to the gate oxides or the Field oxide is applied, and this causes polysilicon into which is spread through the gate oxides (which are over the selected GASAD areas are deposited) to the active layer extending holes. The one contacting the active layer in the holes Polysilicon makes up the polycons. The deposited polysilicon layer is then patterned to be used in the GASAD areas, polysilicon gates and the polysilicon lines that extend from the gates in certain GASAD areas to the polycons that pass through the thin gate oxides run to those areas (e.g. to source and / or drain areas) that are part of the active layer are below other selected GASAD areas.

An undesirable peculiarity of the manufacturing processes explained above is that the thin material layers, for example the thin gate oxide layers directly with a resist material come into contact. Consequently, these thin ma-

material layers of the risk of contamination by the resist material exposed ^ and its thickness is reduced to an undesirable extent as it is exposed to the corrosive action of chemical solvents or are exposed to the plasma with which the resist material layer is removed. The unwanted dilution the thin layers of material during the removal of the resist material is particularly serious for layers that are thinner than 50 nm.

The invention is based on the object of a method of the above mentioned type in such a way that an undesired thinning of the thin layer is avoided.

This object is achieved according to the invention by the features specified in the characterizing part of claim 1.

In the following, exemplary embodiments of the invention are explained in more detail with reference to the drawing. Figures 1-5 each show in cross-sectional view various stages of a manufacturing process for manufacturing an electronic component (with a thin gate oxide layer) according to the invention.

The invention provides a new method for manufacturing components used for information processing, the relatively thin (less than 40 nm thick) material layers, for example thin oxide layers, which during subjected to the production of the components of a pattern formation

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(i.e .: certain sections of the surface of a thin layer remain uncovered while the rest of the surface is covered remain). The invention also relates to by this new process manufactured components. According to the invention, components which contain a thin layer of material are used (which is subjected to patterning during component manufacture), produced by being on the thin Material layer a protective material layer is applied. Alternatively, two or more protective layers can be applied to the thin layer of material. Then will the thin layer of material outlined in a pattern by using the protective layer or layers a pattern is or will be provided. This pattern formation takes place, for example, that on the surface of the protective layer (or layers) a patterned masking layer, for example a patterned resist material layer is formed, and then the protective layer (or layers) using the masking layer is etched as an etching mask.

After the plan of the thin layer has been determined, it is provided with a pattern, for example, by using the Protective layer provided with a pattern (or the protective layers) can be used as an etching mask. Alternatively, for example patterned contacts to the thin layer of material formed by placing a layer of contact material on top of the with a Protective layer (or protective layers) provided with a pattern applied

will. As a result, the contact material is also in the holes the protective layer (layers) is introduced and comes into contact with the thin layer, resulting in the formation of a pattern provided contacts. The protective layer (s) provided with a pattern is e.g. in the component during its manufacture included.

Polysilicon should be mentioned among the materials which are suitable for protecting thin material layers, for example thin oxide layers, in particular a silicon oxide layer (for example SiO _3). According to the invention, the protective layer made of polysilicon is applied to a thin material layer, for example by conventional low-pressure CVD processes. The thickness of the polysilicon protective layer is advantageously in the range of approximately 100-200 nm. A thickness less than about 100 nm is undesirable because the occurrence of pinholes and defects in the protective polysilicon layer generally becomes undesirably high. On the other hand, a thickness greater than about 200 nm is undesirable because such a polysilicon layer is undesirable long etching time is required to etch through the entire thickness of the layer during the patterning of the polysilicon layer. On the other hand, if longer etching times are acceptable, thicker layers cannot be ruled out.

Other materials that are suitable for protecting thin layers of material are refractory metals such as tungsten or molybdenum. The thickness of a refractory metal

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The protective layer is advantageously between approximately 50 and 200 nm. Thicknesses outside this range are from those mentioned above Reasons undesirable, on the other hand, thicknesses of more than 200 nm are not excluded if longer etching times can be accepted.

Both the protective layer (or layers) and the thin protected layer underneath (if desired) are patterned by conventional methods such as wet chemical etching, plasma etching or reactive sputter etching. For example, if the thin material _{layer is a thin SiO 2} layer (which is to be outlined in a pattern) and the protective layer is a polysilicon layer, the polysilicon layer can easily be etched (through a masking layer provided with a pattern) without the SiO ₂ - Layer is significantly influenced by exposing the polysilicon in a Cl ₂ T plasma to reactive sputter etching. A suitable Cl _{2 plasma is obtained by flowing Cl 3} gas into a parallel plate apparatus for reactive sputter etching with a throughput of about 10 to 20 cm ³ / min, while the pressure in the reaction chamber is at about 6.7 to 13.3 microbar and a power density in the range

is set between 0.1 and about 0.4 watt / cm. The ratio of the etching speeds of the polysilicon layer on the one hand and the SiO ₂ layer on the other hand is approximately 30: 1 _{in such a Cl 2 plasma.}

While the Cl ^ plasma described above can also be used to atomize

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the SiOj layer (with the polysilicon layer provided with a pattern as an etching mask), this sputtering process, however, proceeds relatively slowly (below 1 nm / min.). For pattern formation of the SiO ₂ layer (using the patterned polysilicon layers as an etching mask), the polysilicon layer _{is preferably etched by reactive sputter etching of the SiO 2} in a CHF plasma. A suitable CHF-j plasma is obtained by flowing CHF ₃ into the sputter etching apparatus, the flow rate being about 15-20 cm ³ / min. is, the pressure in the reaction chamber is set to about 79.8-93.1 microbar and a line

power density is set in the range between 0.1 and about 0.2 watt / cm. The etching rate of the SiO ₂ layer in such a CHF ₃ plasma is about 50 nm / min., While the etching rate of the SiOj layer in relation to that of the polysilicon layer is typically about 50: 1.

During the patterning of the polysilicon and SiO ₂ layers, the SiO ₂ layer is never touched by the masking layer on the surface of the polysilicon layer, thus avoiding undesirable contamination and thinning of the SiO ₂ layer.

The invention is not limited to the manufacture of special components for information processing, limited to special protective layers or to special protected layers. For illustrative purposes, however, the production of a MOS IC according to the method according to the invention will be explained in more detail below.

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be tert.

According to Flg. 1, according to the invention, a MOS-IC containing polysilicon contacts, e.g. a VLSI-MOS-IC (a large-scale integrated circuit) is produced in that on the surface of a layer of doped semiconductor material 20 relatively thin gate oxide layers (GOX) 30 and a relatively thick field oxide layer (FOX) 40 are formed. The layer 20 forms the active surface layer of a semiconductor substrate 10. The relatively thick field oxide layer 40 separates the GASAD areas 50 covered with gate oxide on the surface of the layer 20 where MOSFETs are to be formed. For example, if the active layer 20 is made of silicon, the gate oxide layers 30 and the field oxide 40 are typically relatively thin and a relatively thick SiOj layers or layers, respectively. The field oxide 40 is formed, for example, by thermally oxidizing the surface, the layer 20. After windows have been opened in the field oxide (this is done according to conventional methods) to expose the GASAD regions 50 on the surface of the layer 20, the field oxide layers 30 are formed by, for example, renewed thermal oxidation of the surface of the layer 20. For VLSI-MOS-ICs according to the invention, the thicknesses of the SiO ₃ gate oxide layers 30 are in a range between about 5 and 40 nm, preferably the thickness is about 25 nm. A thickness of the gate oxide layers 30 of less than 5 nm is not desirable, because this would cause the gate threshold voltages to become so low that regulation of the flow of current would be difficult

would (the gate threshold voltages are the minimum voltages at the MOSFET gates, which cause a noticeable change in the currents within the Strora channels of the MOSFETs). on the other hand Thicknesses of more than about 40 nm are undesirable because they are used for regulation of the currents in the MOSFET current channels, unreasonably high voltages would have to be applied to the gates of the MOSFETs.

The thickness of the Si0 ₂ field oxide 40 of the VLSI-MOS ICs is in the range between about 300 and about 400 nm, preferably it is about 350 nm. A thickness of less than about 300 nm is not desirable because the field oxide may not then is thick enough to prevent inversion of the underlying silicon and the resulting electrical connection between the two GASAD regions, which should be electrically isolated from one another. On the other hand, a thickness greater than about 600 nm is undesirable because the field oxide would then form undesirably high steps which would be difficult to cover with other materials during the subsequent processing steps. In addition, it is difficult to etch the material at such high levels.

As FIG. 2 shows, after the gate oxide layers 30 and the field oxide 40 have been formed, a protective layer 60 made of polysilicon is applied the gate oxide layers and the field oxide applied. This is done, for example, by using conventional low-pressure CVD processes. The task of the polysilicon layer is to protect the underlying gate oxide layers 30 from possible contamination and from erosion during the subsequent lithography

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to protect. The thickness of the polysilicon layer is in the range between approximately 100 and approximately 200 runs; it is preferably approximately 150 nm. A thickness less than about 100 nm is undesirable because of the occurrence of pinholes and defects in the Polysilicon would be undesirably high. On the other hand, a thickness of more than about 200 nm has the disadvantage that such a polysilicon layer an undesirably long time to etch during the subsequent etching step to etch holes through the Polysilicon layer 60 and the selected gate oxide layers 30 required. However, if longer etching times are acceptable, see above thicker layers can also be provided.

On the polysilicon layer 60 is a patternable one Masking layer 70 is applied, for example the three-level resist material layer developed by J.M. Moran and D. Maydan in "High Resolution, Steep Profile, Resist Patterns", The Bell System Technical Journal, Vol. 58, No. 5, May / June 1979, pages 1027-1036. The masking layer is provided with a pattern, i.e. there are windows in the masking layer formed to expose portions of polysilicon layer 60 over the gate oxide layers of selected GASAD areas. Then will through the exposed portions of the polysilicon layer 60 and through the underlying gate oxide layers 30 holes 80 is etched to the active layer 20, the patterned layer 70 serving as an etching mask, as shown in FIG. 3. That Etching of these holes 80 takes place, for example, by reactive sputter etching of the polysilicon layer 60 in a Cl ^ plasma (this was described above) and by reactive sputter etching of the gate

oxide layers 30 in a CHF ₃ plasma (also described above). The high polysilicon / Si0 ₂ etching selectivity of the Cl ^ plasma practically prevents the SiO, the gate oxide layers 30 from being etched by the Cl ^ -Pl-asma, while the high SK ^ / silicon etching selectivity of the CHF. Plasma practically etches the Polysilicon layer 60 and the active (silicon) layer 20 prevented by the CHF ₃ plasma. The masking layer 70 is then removed, for example, by conventional chemical solvents such as H ₃ SO ₄ or by conventional plasma etching processes.

To complete the lithography process discussed above, a second polysilicon layer 90 is placed on top of the first polysilicon layer 60 applied so that 80 Polysilicon in the holes is located, which is in contact with the active layer 20. The one located in the holes 80 and with the layer 20 Contacting polysilicon forms the polysilicon contacts (Polycons) 100 for the active layer 20 below the selected GASAD areas. This is shown in FIG. 4. The second layer 90 is formed using conventional low pressure CVD processes, for example educated.

The thickness of the second layer 90 is in the range between approximately 150 and approximately 250 nm, preferably the thickness is 200 nm. The particular thickness range of layer 90 in combination with the specified thickness range for layer 60 results in a combined one Thickness of the polysilicon layers 60 and 90 in the range of about 250 to 450 nm. Since the polysilicon layers 60 and 90 later to form the polysilicon gates of the IC with a mu-

ster, the gates have a thickness in the range between about 250 and about 450 nm. A thickness of the polysilicon gates of less than about 250 nm is therefore not desirable, because it would lead to the gates having an undesirable sheet resistance. On the other hand, a thickness is the Polysilicon gates greater than about 450 nm are undesirable because it would cause the polysilicon gates to be so tall would be that the sidewall capacitance would assume an undesirably large value.

Now the two polysilicon layers are 60 and 90 and accordingly also the polycons 100 formed by the application of the second polysilicon layer 90 (by customary methods) doped with a suitable n- or p-dopant (the conductivity type depends on whether the active layer 20 is n-conducting or p-conducting is). The doping of the polysilicon layers 60 and 90 favors the production of high conductivity gates (the Polysilicon layers are provided with patterns to form the gates), while the doping of the polycons 100 is good electrical Contacts for the active layer 20 are generated. The dopant also diffuses through the polycons 100, as in FIG. 4 is indicated, and forms relatively heavily doped zones 110 of the active layer 20, e.g. source or drain zones of the MOSFET, whose gate oxide layers are penetrated by the polysilicon contacts. The two polysilicon layers 60 are then formed and 90 patterned using conventional techniques to form MOSFET gates 120 in GASAD areas 50, as well Polysilicon lines 130 leading from the eolysilicon gates

120 in selected GASAD areas to the through the gate oxide layers to the active layer under other selected GASAD areas extending polycons 100, as FIG. 5 shows.

The steps necessary to complete the MOS-IC correspond to the state of the art. That means: self-aligned source and drain zones are formed on opposite sides of the gates (by conventional process steps), and an insulating layer, for example an SiO ₂ layer, is applied to the IC. Windows are then formed in the insulating layer by conventional lithography processes in order to expose the gates and the source and drain regions of the IC. Finally, a metal layer, e.g. a layer of copper-doped aluminum, is applied to the IC (this allows metal to get into the holes extending through the insulating layer and forms metallic contacts with the gates and the source and drain zones) and the metal layer is then used for formation provided with a pattern of metallic conductors.

In the event that composite metal silicide-on-polysilicon gates are desired, e.g. tantalum silicide-on-silicon gates, the production process described above is modified by adding a metal silicide layer after the doping of the polysilicon layers is formed on the two polysilicon layers. Thereafter, the silicide layer and the polysilicon layers patterned to metal silicide-on-polysilicon gates as well as metal silicide-on-polysilicon conductors, which

extend from selected gates to the polysilicon contacts.

A thin SiC ^ layer, typically about 1 nm thick, is usually formed on the surface of the first polysilicon layer 60 before the application of the second polysilicon layer 90 while the production method according to the invention is being carried out. The polysilicon gates produced according to the invention, as well as the polysilicon contacts, thus typically contain two polysilicon layers separated by a thin SiO2 interface. This thin boundary layer made of SiO ₂ can be detected, for example, in transmitted-light electron beam micrographs of cross-sections of ICs according to the invention. However, this SiOj boundary layer is so thin compared with the two polysilicon layers, and the amount of SiO ₂ is so small (compared to the amount of polysilicon) that the SiO _{2 has} no detectable detrimental influence on the conductivity of the polysilicon formed according to the invention. Has gates and polysilicon contacts.

example

The method according to the invention was used to produce a logic VLSI-MOS circuit which contained ring oscillators, line drivers, shift registers, 4-bit adders and other components. This VLSI-MOS logic circuit, which also contains polysilicon contacts, was manufactured on the basis of -, 1.5 <& m · and 2 fym - design specifications.

The manufacturing process began with the growth of about 350 nm thick SiO ₂ field oxide on the surface of a 3-inch silicon wafer. The field oxide was grown by thermal oxidation of the silicon wafer in a wet environment (H ₂ O).

To form the active layer of the logic circuit and to define the dopant concentration at the intermediate layer Silicon / field oxide (this is one of the parameters that determine the threshold voltage the gates of the MOSFETs of the enhancement type of the logic circuit), the silicon oxide covered by the field oxide was

12 -2 wafers with boron atoms with a dosage of about 2 χ 10 cm implanted. The energy of the boron atoms was about 170 keV, which was sufficient to ensure that the boron atoms were the field oxide penetrated to the silicon / field oxide interlayer.

The GASAD areas on the surface of the wafer were then exposed by conventional lithographic processes by forming windows in the field oxide. These windows (and thus the GASAD areas) were 7 ^ m long and wide about

By heating the wafer to about 1000 ° C. for about 15 minutes in an O ₂ -HCl (3% HCl) environment, an approximately 25 nm thick gate oxide of SiO _{2 was} grown on the surface of each GASAD region. The wafer was then subjected to a heat treatment for about 15 minutes at a temperature of about 1000 C in an argon atmosphere in order to reduce the solid charge within the SiO ₂ . This heat treatment also activates the boron implant

(The boron atoms displace silicon atoms in the silicon crystal lattice as a result of the argon heat treatment).

A first polysilicon layer approximately 150 nm thick was then applied to the wafer by conventional low-pressure CVD processes. A 1.8 nm thick organic resist material was then spun onto the wafer (this resist material is sold under the trade name HPR-2O4 resist by the company Philip A. Hunt Chemical Corporation of Palisades Park, New Jersey) / and the wafer was approximately Baked for 120 minutes at a temperature of about 210 C. An approximately 120 nm thick SiO ₂ layer was deposited on the organic resist material by plasma deposition, and then _{an approximately 350 nm thick X-ray resist material layer was deposited on the 120 nm thick SiO 2} by spinning (the material was DCOPA (90% dichloro-propyl acrylate and 10% copolymer)).

After aligning the mask on the plane of the polysilicon contacts over the GASAD areas, the DCOPA x-ray resist material layer was exposed to x-rays having a wavelength of 0.437 nm for about 5 minutes. The intensity of the radiation was 75 / 6Watt / cm *. The X-ray resist layer was developed in a wet developer containing isopropyl alcohol and methyl ethyl ketone. Then, using the X-ray resist material layer as an etching mask, the 120 nm thick SiO ₂ layer was patterned by reactive sputter etching of the wafer in a CHF-j plasma. The CHF ₃ plasma was formed by adding CHF ₃ with

a rate of about 79 cm ³ / min. The flow into the reactor chamber was _# while the pressure inside the reactor chamber was kept at about 13.3 microbar and the power density was set at about 0/1 watt / cm ² . Finally, using the patterned layers of the X-ray resist and the SiO ₂ as an etch mask, the HPR-204 resist was patterned by reactive sputter etching of the wafer in an O ₂ -CF ₄ (1% CF ₄ ) plasma. This O ₂ -CF ₄ plasma was formed by flowing a mixture of O ₂ and CF ₄ (1% CF ₄ ) into the reactor chamber / the throughput being about 83 cm ³ and a pressure of about 5.3 microbar in the reactor chamber maintain

2 and a power density of about 0.2 watt / cm was set.

Holes were then etched through the polysilicon layer (the holes were over those GASAD areas where polysilicon contacts were desired) using the patterned resist material layer as an etch mask. The etching was carried out by reactive sputter etching of the polysilicon layer in a Cl ₂ plasma for a time of about 5 minutes. This etching, which took place in a parallel plate apparatus for reactive sputter etching, took place while in the reactor chamber with a throughput of 20 cmVmin. Cl ₃ -GaS was flowed in while the total pressure inside the reactor chamber was kept at about 6.6 microbar and the power density at about 0.3

Watt / cm has been set. Then through those gate oxide layers, where polysilicon contacts were desired, holes etched through the patterned polysilicon layer served as a mask. The etching was done by reactive sputtering

Etching of the wafer (in the parallel plate apparatus for reactive sputter etching _{) in a CHF 3 plasma.} During the last Xtz step, CHF _{3 was} generated with a throughput of around 18 craVmin. Flowed into the reactor chamber, where a pressure of about 90.4 microbar is maintained and the power density is about

0.2 watt / cm was set.

Then from the surface of the wafer were the HPR-204, stripped of SiO ₂ and the DCOPA X-ray resist material, by the wafer was treated with a solution of a sulfurous acid and hydrogen peroxide, which was done at an ambient temperature of about 8O ⁰ C. In addition, the wafer surface was cleaned with common chemical solvents containing HF in order to remove any remaining residues of resist material.

Then a second, about 250 nm thick polysilicon layer applied. This was done using conventional low-pressure CVD processes. This cut through in the the first polysilicon layer and the gate oxide layers to the underlying silicon holes extending polysilicon down, resulting in the formation of the polysilicon contacts.

The two polysilicon layers and the polysilicon contacts were then doped with phosphorus by placing the wafer in a conventional PBr ₃ oven for about 60 minutes. The furnace temperature was about 950 C. This phosphorus ^{diffusion step resulted in the n +} conductivity of the polysilicon layers and

of the polysilicon contacts, the doping strength being about 10 cm ~ fraud. In addition, phosphorus has also been driven into the silicon areas surrounding the polysilicon contacts, resulting in a partial formation of the source and drain zones of the MOSFETs, the gate oxide layers of which are penetrated by the polysilicon contacts was.

The remaining steps in making the VLSI MOS logic circuit corresponded to the state of the art. These steps are for example from Watts in the article "Electron Beam Lithography For Small MOSFETs, "IEEE Transactions Electron Devices / November 1981, Vol. ED-28, No. 11, p. 1338.

Claims (9)

Claims , 1 / Method for producing an integrated circuit, in which a thin insulating layer on a semiconductor body (20) (30) and on this a masking layer (70) is formed, the masking layer is selectively etched, the insulating layer is etched using the masking layer as a mask, and the masking layer is removed in a further etching step characterized in that prior to the formation of the masking layer over the thin insulating layer a conductive protective layer (60) is formed which protects the thin insulating layer when the masking layer is removed. 2. The method according to claim 1, characterized in that that the thin insulating layer (30) has a thickness of less than 40 nm. Radedcettreee 43 8000 Munich 60 Telephone (089) 883605/88 »», Telex SiTJiti Telegramme Patentconsult SOfmenberger StraBe 4S 6200 Wleiboden Telephone (06121) S62945 / S61998 Telex 4186237 Telegrams Pstentconsult Fax (CCITT 2) Wiesbaden and MUndien (089) 8344618 Attention Petentcomult 33332G8 3. The method according to claim 1 or 2, characterized in that the thin insulating layer consists of SiO ₂ and the semiconductor body consists of silicon. 4. The method according to any one of claims 1-3, characterized in that the masking layer is a resist material layer which is removed by chemical etching or plasma etching. 5. The method according to any one of claims 1-4, characterized in that the protective layer is a polysilicon layer is. 6. The method according to claim 5, characterized in that that the polysilicon layer has a thickness between about 100 and about 200 nm. 7. The method according to claim 6, characterized in that that the protective layer is a layer of refractory metal. 8. The method according to any one of claims 1-7, characterized in that the protective layer (60) and a hole (80) is etched through the insulating layer (30), and that after removing the masking layer (70) over a second conductive layer (90) is formed in the protective layer which extends through the hole and makes contact BATH ORIGINAL with the semiconductor body (20). 9. The method according to claim 8, characterized in that that the thin insulating layer (30) is a gate oxide, that the conductive layer (60) and the second conductive layer (90) to be etched over a portion of the gate oxide To form the gate electrode (120) and a conductor (130) which connects the gate electrode to a contact portion (100).