GB2123980A

GB2123980A - Aligning photomask with wafer

Info

Publication number: GB2123980A
Application number: GB08235711A
Authority: GB
Inventors: Masao Kosugi; Hiroshi Sato; Kazuo Takahashi; Ichiro Ishiyama; Shuichi Yabu
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1981-12-15
Filing date: 1982-12-15
Publication date: 1984-02-08
Also published as: DE3246305A1; JPS58102939A; GB2123980B

Abstract

The line width of the alignment pattern on a mask is sufficiently narrow so that on exposure of a resist covered wafer to the mask the mask pattern is transferred to the resist but the alignment mark is not. The pattern of the mask is formed so that the line width of the alignment pattern is thin as compared with that of the actual element pattern, so that the exposure amount, in the alignment pattern portion on the resist is high due to diffraction phenomenon and thus, the alignment pattern of the mask is not transferred onto the wafer.

Description

SPECIFICATION Mask aligner Background of the invention Field of the invention This invention relates to a mask aligner, namely, a device for aligning, into a predetermined positional relation, a mask which is a negative and a wafer onto which the actual element pattern of the mask is to be printed, and thereafter transferring the pattern of the mask onto a resist applied to the surface of the wafer.

Description of the prior art In aligning a mask and a wafer, providing alignment patterns in opposed relationship on the mask and wafer is usual, and even inevitable particularly in automatized alignment (auto-alignment). The alignment patterns on the surface of the mask and the surface of the wafer are provided with their positional accuracy guaranteed relative to actual element patterns such as circuits and, if the mask and wafer are aligned by the use of the alignment patterns, it will mean that they have been aligned by the use of the actual element patterns. Usually, alignment is carried out with the alignment patterns of the mask and wafer observed at a time through an alignment observation optical system and for this reason, the alignment patterns of the mask and wafer differ in shape from each other.

Heretofore, where alignment has been completed and thereafter exposure has been applied, the actual element pattern of the mask has been transferred to the wafer and simultaneously therewith, the alignment pattern of the mask has been transferred onto the opposed alignment pattern of the wafer and this alignment pattern of the wafer could not be used as the alignment pattern thereafter.

Therefore, a method has heretofore been adopted in which as the number alignment patterns as necessary are provided on the wafer and these alignment patterns of the wafer are consumed sequentially during alignment steps.

This method, however, has the following disadvantages. One is that there are a number of alignment patterns and therefore the area to be occupied by circuit patterns (actual element patterns) is descreased. Another disadvantage is that the mutual positional error of the plurality of alignment patterns reduces the alignment accuracy.

That is, where in the first step, all alignment patterns for use thereafter are made on the wafer, the error between those alignment patterns may cause deterioration of the alignment accuracy during the second and subsequent steps and, where in a certain step, the alignment pattern for use in the next step is made on the wafer, the mutual positional error between the actual element pattern of the mask used in that step and the alignment pattern prepared on the mask for the next step which is to be transferred to the wafer becomes a problem.

For the purpose of overcoming the above-noted disadvantages, means for protecting the alignment pattern of the wafer have been proposed.

One of them, as is known from U.S. Patent No.

4,007,988, is a method whereby the alignment pattern portion of the wafer or the mask is partly masked and exposure is applied. In this case, the alignment pattern portion of the wafer is not exposed at all.

Another means, as is known from U.S. Patent No.

3,844,655, is a method whereby excessive exposure is applied only to the alignment pattern portion prior to exposure.

In these two methods, the form differs depending on whether the photosensitive material (resist) is of the positive type or of the negative type, but in any case, as the result of the development, the alignment pattern of the mask is not printed around the alignment pattern of the wafer and, during the subsequent alignment processes, the alignment pattern of that wafer can be reused.

However, of these two methods, the former masking method has the disadvantages that a masking mechanism is required and that time is lost because a masking member is put in and out, and the latter pre-exposure method has the disadvantages that a mechanism for applying the excessive exposure is required and that the time loss corresponding to the exposure time therefor is caused.

Summary of the invention It is an object of the present invention to eliminate the above-noted disadvantages and to provide a mask aligner in which the number of alignment patterns is limited to minimum one and protection of the alignment pattern of a wafer is achieved without using a technique which involves an additional mechanism such as masking or pre-exposure and a time loss (reduced productivity).

This object is achieved by constituting the alignment pattern of a mask by a line width thinner than the visualizing-limit line width WO (determined by the performance of resist, the performance of a projection optical system, etc. used in the mask aligner) namely, the minimum line width which can be transferred to the wafer.

That is, this object is achieved by providing, in a mask aligner of one-to-one magnification system, an alignment pattern of a line width thinner than the visualizing-limit line width W0, and by providing, in a mask aligner of reduction ratio m, an alignment mark of a line width thinner than W0/m.

The invention will become more fully apparent from the following detailed description thereof taken in conjunction with the accompanying drawings.

Brief description of the drawings Figure 1 is a conceptional view showing the manner in which a mask pattern is printed on a wafer.

Figure 2 is a graph showing the distribution of illumination on the surface of the wafer.

Figure 3 is a graph showing the changes in the distribution of the amount of exposure with changes in the exposure time.

Description of the preferred embodiment Figure 1 illustrates the manner in which the alignment pattern on a mask 1 in a proximity type aligner or a projection type aligner is printed onto a wafer 2. The mask 1 has thereon an actual element pattern 3 having a line width L thicker than the visualizing-limit line width W0 and an alignment pattern 4 having a line width e thinner than the visualizing-limit line width W0, and exposure light 5 is applied thereto. Figure 2 shows the distribution of illumination Ion the surface of the wafer.

As shown in Figure 2, it is geometro-optically conceivable that a distribution of illumination is indicated at 6, 6' which completely provides a contrast is formed on the surface of the wafer, but in the printing system by the proximity method or the projection method, a distribution of illumination as indicated at 7, 7' is formed under the influence of the diffracted light from a minute pattern. That is, as the line width becomes smaller, the going-round of light to the dark portion by diffraction occurs to provide a wave-optic distribution of illumination.

Where the actual element pattern 3 of the mask 1 is to be formed on the wafer 2, it is usual to reproduce a resist image having the same line width as the pattern line width and to this end, the exposure amount is controlled by exposure time t.

Figure 3 shows the distribution of the exposure amount I x t when the exposure time t has been varied. In Figure 3, letter S designates the resist sensitivity.

In the distribution of exposure amount denoted at 8 in Figure 3, the exposure is "under" and in this case, the resist line width is thicker than the line width L of the actual element pattern 3 on the mask, and in the distribution of exposure amount denoted at 10, the exposure is "over" and the resist line width is thinner than the line width L of the actual element pattern 3 on the mask.

Accordingly, the distirbution of exposure amount denoted at 9 is optimum to print the actual element pattern 3, whereby a resist image on line width L is reproduced.

On the other hand, the alignment pattern 4 of the mask 1 comprises a line width e thinner than the visualizing-limit line width W0, and a resist image corresponding thereto is not formed because an exposure exceeding the resist sensitivity S is provided.

It has been described above as the one-to-one magnification system, namely, the proximity method or the 1:1 projection method, that in the proper exposure amount for the actual element pattern, the alignment pattern is comprised of a line width which is not visualized, and specifically, the line width of the alignment pattern is e relative to the line width L of the actual element pattern, but even in the projection method of reduction ratio m, the line width of the alignment pattern is determined to elm relative to the line width Lim of the actual element pattern, whereby this method can likewise be ap plied.In the actual use, the line width of the mask pattern must be determined by conditions including the resist characteristic, the performance of the projection optical system, etc., but it will be sufficient if said line width is about 1/2 of the visualizing-limit line width W0.

In a mask aligner having an observation optical system or a detection optical system for alignment of a mask and a wafer, it is necessary that the line width of the alignment pattern of the mask be a line width which is not transferred to the wafer and be resolvable by the observation or detection optical system.

Also, in the aligner using the present invention, the exposure light may be ultraviolet light, farultraviolet light orX-rays or the like.

In the present invention, the alignment pattern of the mask has been described as not being transferred to the wafer, but the present invention can also be applied to such a special usage that a predetermined portion of the actual element pattern of the mask is not to be transferred to the wafer, by making the pattern line width corresponding to said portion thinner than the visualizing-limit line width W0.

If the present invention is used, alignment in all photo processes becomes possible by using a single wafer alignment pattern without adding any additional function and without any time loss, and this is highly useful.

Claims

1. A mask aligner having: a mask having an actual element pattern and an alignment pattern; and a wafer to which the actual element pattern of said mask is transferred; the alignment pattern of said mask being a pattern of a line width which is not transferred to said wafer.

2. A mask aligner having: a mask having an actual pattern and an alignment pattern; a wafer to which the actual element pattern of said mask is transferred; and means for observing or detecting the alignment of said mask and said wafer; the alignment pattern of said mask being a pattern of a line width which is not transferred to said wafer and being resolvable by said alignment means.

3. A mask for integrated circuit manufacture having an alignment pattern arranged so that it is not transferred, in use, to the wafer.

4. A mask according to claim 3, where the alignment pattern comprises light transmissive lines arranged to transmit less light than light transmissive lines of circuit patterns on the mask.

5. A mask according to claim 4, wherein the line width of the alignment pattern is less than that of the circuit pattern.

6. A mask substantially as herein described with reference to the accompanying drawings.

7. A mask aligner including a mask substantially as herein described with reference to the accompanying drawings.