GB2122809A - Integrated circuit interconnection bus structure - Google Patents

Abstract

An interconnected bus structure, for use in corridors (3) between rows of logic elements (2) having exposed metallic contacts (6, 7) of an integrated circuit uncommitted logic array, includes a plurality of, bus metallic tracks arranged on an insulating layer overlying the integrated circuit substrate in groups of four in bus sub-corridors (9) and following bus track grid lines (8). Under the insulating layer and extending at right angles to the track grid lines (8) are conductive tracks (14) of various lengths. The ends of the tracks (14) are accessible from the surface of the insulating layer by metallic contacts (15) extending in apertures through the insulating layer. In order to gain access to the innermost pair of each group of four bus track grid lines the spacing between these two bus track grid lines increases at intervals to allow the underlying conductive tracks (14) io be contacted by means of metal contacts (16) arranged within the groups and extending through respective apertures in the insulating layer. <IMAGE>

Description

SPECIFICATION Integrated circuits This invention relates to integrated circuits and, in particular, to bus structures therefor, and specifically but not exclusively for uncommitted logic arrays.

According to the present invention there is provided an integrated circuit having a bus structure comprising one or more bus subcorridors adapted to accommodate a plurality of bus tracks arranged, or to be arranged, on a surface of an insulating layer by deposition of electrically conductive material, which tracks are, or are to be arranged, such as to follow bus track grid lines extending in a first direction along the length of the sub-corridor(s), a plurality of electrically conductive tracks being arranged under the insulating layer and extending in a direction transverse to the first direction, electrical contacts for the conductive tracks being provided at the surface and connected to the conductive tracks via apertures in the insulating layer, wherein the bus track grid lines are arranged in groups, wherein to enable contact to be made to an inner track or the inner tracks of a group the spacing between two of the bus track grid lines is increased at intervals along their length whereby to accommodate one or more of the contacts within the group of bus track grid lines, and wherein the remainder of the contacts are arranged between adjacent groups of bus track grid lines and/or between the edges of the bus structure and the respective bus track grid line adjacent thereto.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 shows schematically an integrated circuit comprising a logic array and input/output buffer cells, Fig. 2 shows a portion of an 8-bit bus compatible interconnect corridor structure for use in an integrated circuit such as Fig. 1, Fig. 3 shows the structure of Fig. 2 interconnected by a single layer metal pattern, Fig. 4 shows a corresponding 4-bit structure, and Fig. 5 shows a corresponding 12-bit structure.

The integrated circuit chip 1 shown in Fig. 1 comprises a plurality of logic elements 2 which may be completely uncommitted or only partly committed to particular logic functions.

Uncommitted logic arrays are employed in integrated circuit manufacture in order to minimise the number of specific fabrication masks required, and thus the cost, for low volume orders of specific function devices. Thus for each of a family of devices the same fabrication masks are employed up to the metallisation stage, but different metallisation masks are employed.

Therefore, the component layout is standardised and fixed, but for each new application the final metallization pattern is customised. The logic elements 2 are arranged in rows, with corridors 3 between adjacent rows. Around the edge of the chip 1 are a plurality of input/output buffer cells 4.

There is an interconnect corridor, such as 5, between logic elements 2 and the adjacent cells 4.

The present invention is concerned with the structure of the interconnections in the corridors 3, that is between the rows of the logic elements.

In order to provide maximum flexibility for committing of the uncommitted or only partly committed logic elements 2 it is necessary that there is easy access from each of the logic element "pins" to any of the bus conductors to be arranged in the corridor. This should preferably be carried out without requiring complicated crossover arrangements and also be applicable to autorouting techniques, that is the connection together of all of the functions provided on the chip by means of a single layer of metallic tracks provided in the spaces between the islands comprising the logic elements 2 and the input/output buffer cells 4. In the case of an 8-bit bus the initial thought is to have an interconnection corridor eight tracks wide.

However, access is necessary to each track and for ease of access wider corridors are thus required.

Fig. 2 shows a section of an 8-bit bus compatible interconnect structure for use in major corridors such as 3 between rows of logic elements 2. In Fig. 2 the logic element "pins" are indicated by metallic contact pads 6 and 7 on opposite sides of corridor 3.

Fig. 2 shows only a section of interconnect structure, this section is repeated along the length of the corridor. In the case of the 8-bit bus structure shown in Fig. 2 two groups of four bus conductors or tracks running the length of the corridor 3 will be employed. The bus conductors or tracks will be arranged on grid lines 8, which are imaginary, that is they are not present on the actual device and are thus indicated by dotted lines. The bus conductors will be provided by metal on the surface of a passivating oxide layer arranged over the entire surface of the chip. The contact pads 6 and 7 comprise metal areas which are exposed at the surface of this oxide layer. The bus conductor grid lines 8 are arranged in socalled bus sub-corridors 9.Between the bus subcorridors 9 is provided an initially empty (first) sub-corridor 10 providing room for up to three parallel interconnection tracks along the direction of grid lines 11. The grid lines 1 1 are imaginary, that is they are not present on an actual device and are thus indicated by dashed lines, but any electrically-conductive (metal) interconnections formed in these sub-corridors 10 in the direction of the length of the sub-corridors 10 will follow lines corresponding to these imaginary grid lines.

Between the bus sub-corridors 9 and two arrays of interconnect contacts 12 arranged on opposite sides of the interconnect structure is a respective further initially empty (first) sub-corridor 13, also having imaginary grid lines 1 1. Running under the oxide layer on which the bus conductors will be provided and at right angles to the length of the bus conductor grid lines 8 and the imaginary grid lines 1 1 are conductive tracks 14. The tracks 14 may comprise metal or polysilicon or another conductive material, such as titanium silicide, and be provided within the oxide layer simultaneously with gate electrodes and interconnects formed within the logic elements, as, for example, described in our co-pending Application No.

8215940 (Serial No. ) (D. J. Rogers 1).

The conductive tracks 14 are of varying lengths. Some are only sufficiently long to extend under one sub-corridor, whereas others extend under two sub-corridors. At each end of each conductive track 14 is provided a metallic contact 1 5 which extends to the surface of the oxide layer.

In dependence on the interconnection required some of the conductive tracks 14 may extend from one side of the corridor 3 to the other. The number and length of the conductive tracks is preferably determined empirically whereby to obtain maximum flexibility of routing.

In order to gain access to the inner two of the group of four bus conductor grid lines 8, the spacing between two of the bus conductor grid lines 8 is increased at intervals such as to allow contact to be made to the underlying conductive track 14 via metallic contacts 16 which extend through the insulating oxide layer. In order to facilitate such splitting of the bus conductor groups the bus sub-corridors 9 are based on six rather than four imaginary grid lines, whereby between such splits an imaginary grid line 17 (shown chain dotted) is available for interconnection purposes on each side of the group of four bus conductor grid lines 8. The number of such splits in the bus conductors of a corridor is in general determined by the type of logic elements 2. For example, D-type bistable latches each require one such split.

The interconnect structure shown in Fig. 2 and described above is such that any one of the contacts 6, 7 can be interconnected to any one of the bus conductors on the grid lines 8 by the provision of metallic (electrically-conductive) interconnections between selected contacts in a single (metal) layer and without the need for complicated cross-overs. Such a single metal layer interconnection pattern is shown in Fig. 3. The pattern is such that bus conductors A, B, C, D, E, F, G and H are provided on the grid lines 8 of Fig. 2 and are interconnected simultaneously to contacts A, B, C, D, E, F, G and H respectively, on either side of the corridor. The metallisation pattern used for the corridors may be part of the pattern used to commit the uncommitted logic elements which are to be joined at the corridors, or alternatively comprise a pattern applied with a separate mask.

The bus conductors or tracks themselves may, alternatively, be provided by means of a different mask to that which actually interconnects them to the contacts. For example, the bus tracks may be deposited simultaneously with the contacts but only become interconnected thereto when the integrated circuit is committed to a particular function.

In order to provide access to each of the bus conductor grid lines of an 8-bit arrangement, it is necessary to provide contacts between every pair of bus conductor grid lines at two positions along the length of the interconnection structure section, which two positions are adjacent in the arrangement shown in Fig. 2.

Whilst the invention has been described so far with reference to an 8-bit bus, it is not to be considered so limited. An arrangement for a 4-bit bus is shown in Fig. 4. In this arrangement a smaller number of possible conductive tracks 14 per section may be required than for the 8-bit bus.

Various interconnections between the contacts A, B, C and D and bus lines A, B, C and D are shown by way of example. An arrangement for a 12-bit bus is shown in Fig. 5, which arrangement will require more conductive track 14 options per section than shown for maximum flexibility of interconnections. In Fig. 5 the bus track grid lines are indicated by solid lines, rather than broken lines as in Fig. 2. Odd numbers of bus tracks can be similarly catered for, the tracks being generally arranged in pairs or quads and the odd number accounted for in an arangement of three tracks where two of the three tracks are spaced further apart at intervals in order to permit the arrangement of a contact adjacent the inner track and in communication with an underlying conductive track 14.

The interconnection structure of the present invention is particularly applicable to computer designed autorouting patterns since it enables access to be obtained at right angles from any bus grid line to any logic element (island) contact, with a single layer electrically-conductive (metallisation) pattern.

Claims (5)

1. An integrated circuit having a bus structure comprising one or more bus sub-corridors adapted to accommodate a plurality of bus tracks arranged, or to be arranged, on a surface of an insulating layer by deposition of electrically conductive material, which tracks are, or are to be arranged, such as to follow bus track grid lines extending in a first direction along the length of the sub-corridor(s), a plurality of electrically conductive tracks being arranged under the insulating layer and extending in a direction transverse to the first direction, electrical contacts for the conductive tracks being provided at the surface and connected to the conductive tracks via apertures in the insulating layer, wherein the bus track grid lines are arranged in groups, wherein to enable contact to be made to an inner track or the inner tracks of a group the spacing between two of the bus track grid lines is increased at intervals along their length whereby to accommodate one or more of the contacts within the group of bus track grid lines, and wherein the remainder of the contacts are arranged between adjacent groups of bus track grid lines and/or between the edges of the bus structure and the respective bus track grid line adjacent thereto.

2. An integrated circuit as claimed in claim 1, including two groups of bus track grid lines, wherein each group is arranged in a respective bus sub-corridor, wherein the bus sub-corridors are separated from themselves and from the edges of the bus structure by respective first sub-corridors in which further electrically-conductive tracks on the surface can be arranged, the remainder of the contacts being arranged such that there are contacts at the edges of the bus structure and between the sub-corridors, and wherein the conductive tracks are of various lengths, some of which extend only under a respective bus subcorridor, some of which extend only under a respective first sub-corridor and some of which extend under a respective bus sub-corridor and an adjacent first sub-corridor, each contact other than those within the bus track grid line groups being associated with a respective conductive track end.

3. An integrated circuit as claimed in any one of the preceding claims, wherein the conductive tracks under the insulating layer are of polysilicon.

4. An integrated circuit as claimed in any one of the preceding claims and including logic elements adapted to be committed to a desired logic function in dependence on the configuration of an electrically-conductive interconnection pattern to be applied thereto, the bus structure being arranged between rows of said logic elements and the or another electrically-conductive interconnection pattern serving to provide the bus tracks and to interconnect selected contacts of the logic elements to selected bus tracks via the bus structure contacts and the conductive tracks.

5. An integrated circuit including a bus structure and substantially as herein described with reference to and as illustrated in Figs. 1, 2 and 3, 4 or 5 of the accompanying drawings.