GB2110494A - MOS follow-up pulse train generators - Google Patents
MOS follow-up pulse train generators Download PDFInfo
- Publication number
- GB2110494A GB2110494A GB08230735A GB8230735A GB2110494A GB 2110494 A GB2110494 A GB 2110494A GB 08230735 A GB08230735 A GB 08230735A GB 8230735 A GB8230735 A GB 8230735A GB 2110494 A GB2110494 A GB 2110494A
- Authority
- GB
- United Kingdom
- Prior art keywords
- stage
- pulse train
- switching
- transistor
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Pulse Circuits (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
An MOS follow-up pulse train generator for the production of a follow-up pulse train from at least one setting pulse train(s), comprising a switching stage, (SS) a delay stage (D) and an end stage (E). The setting pulse train (S) which is fed in via a switching transistor (ST1) of the switching stage (SS) controls the delay stage (D) and the end stage (E). The switching stage (ST1) can be expanded by the parallel or series connection of further switching transistors to easily effect a OR or AND gate logic-linking of a plurality of setting pulse trains. No further circuitry modifications are needed. The circuit arrangement in accordance with the invention serves preferably for the internal pulse train supply of highly integrated storage modules. <IMAGE>
Description
SPECIFICATION
MOS follow-up pulse train generators
The invention relates to MOS follow-up pulse train generators for producing a follow-up pulse train from at least one setting pulse train.
The German Patent Specification published under the serial number AS 26 59 207 describes a circuit arrangement for the generation of a follow-up pulse train from a setting pulse train, the overall circuit of this known arrangement being referred to as a delay stage, which contains a delay circuit, a switching stage and an end stage. The delay circuit itself consists of two series connected inverters, each comprising a driver transistor and a load transistor. In the following description this particular part of the overall circuit arrangement will itself be referred to as a delay stage.
The setting pulse train is connected to the control electrode of the load transistor of the first inverter, and simultaneously controls the switching stage.
The end stage also consists of two such inverters, that have their drive components connected in parallel. The control electrodes of the driver transistors of the two inverters are directly connected to the output of the delay stage, whereas the switching stage is interposed between the output of the delay stage and the control electrodes of the load transistors of these two inverters.
The output of the first inverter of the end stage features a capacitive feedback to the control electrodes of the two load transistors, in order to produce steeper gradient signal flanks and a sufficiently high upper signal level for the followup pulse train, which can be tapped from the output of the second inverter (a boot-strap circuit). The full effect of the feedback capacitance is achieved due to the delayed control of the driver transistors of the end stage by the output signal of the delay stage.
Under certain circumstances it is necessary to derive a follow-up pulse train from more than one setting pulse train, by combining two or more setting pulse trains using simple logic links. In this case it is necessary to precede the known circuit arrangement by appropriate logic linking elements, which results in an increase in the signal transit time, and in the overall space requirement.
One object of the present invention is to provide a circuit arrangement for the generation of a follow-up pulse train from a setting pulse train, which is of such a configuration that it can be extended in a simple manner so that the requisite composite follow-up pulse train can be derived by the logic-linking of two or more setting pulse trains, in particular in accordance with the
AND or the OR function, without increasing the signal transit time and with virtually negligible additional circuitry.
In accordance with the present invention there is provided an MOS follow-up pulse train generator for the production of a follow-up pulse train from at least one setting pulse train, the output being provided by a second inverter of an end stage which consists of two inverter stages, each comprising the series combination of a load transistor and a driver transistor, the end stage being driven by a delay stage which consists of two inverter stages each comprising the series connection of a load transistor and a driver transistor, the junction of the two transistors in the second inverter of the delay stage providing an output to the control electrodes of both inverters of the end stage, and the delay stage being driven by a setting pulse train applied to a switching stage whose output is connected to the control electrode of the load transistor of the first inverter stage of the delay stage, and to the control electrodes of the two load transistors in the end stage.
The invention will now be described with reference to the drawings, in which:~
Figure 1 schematically illustrates the circuit diagram of one exemplary embodiment;
Figure 2 schematically illustrates details of one alternative embodiment, having a modified switching stage; and
Figures 3 to 5 schematically illustrate three further modified switching stages each suitable for the logic linking of two setting pulse trains.
The embodiment shown in Figure 1 consists of a switching stage SS, a delay stage D and an end stage E, with operating voltage connection points UDD and Uss. The circuit construction of the end stage E is identical to that of the pulse train circuit disclosed in the above-mentioned German Patent
Specification AS 26 59 207. It contains two inverters which comprise the driver transistors and load transistors Tr1, L1 and Tr2, L2 respectively. The control electrodes of the two driver transistors Trl and Tr2 are connected in parallel as are the control electrodes of the two load transistors L1 and L2. The follow-up pulse train T is obtained from the output of the second
inverter, which comprises the transistors Trl and L1 .The output load is represented by a capacitor
Ca, as it is generally predominately capacitive in nature. A capacitor Cs is interposed between the output of the end stage first inverter, Tr2, L2, and the control electrodes of the load transistors L1 and L2, in known manner to increase the control signals for the load transistors L1 and L2.
In contrast to the known pulse train circuit, the
delay stage D consists of two series connected
inverters comprising the transistors Tr3, L3 and
Tr4, L4 respectively, not operated directly by the
setting pulse train S, but driven by the output of
the switching stage SS. In this case the output of
the delay stage is connected in known manner to
the control electrodes of the driver transistors Tr1
and Tr2 of the end stage. The delay stage is
preceded by the switching stage SS, which
comprises the series connected transistors ST1 and RT.The connection point of these transistors,
referred to in the following as the switching node
K, forms the output of the switching stage SS and
is connected to the control electrodes of the load
transistors L1 to L3, i.e. to the load transistor of the first inverter of the delay stage and to both
end stage inverters. The switching transistor ST1
is controlled by the setting pulse train S.
This embodiment of a circuit arrangement to generate a follow-up pulse train must be brought into a determinate basic state before every new pulse of the setting pulse train. This is effected by a reset signal RS formed by a bias voltage or a reset pulse train. The reset signal RS is applied to the transistor RT, the driver transistor Tr3 of the first inverter in the delay stage, and the load transistor L4 of the second inverter of the delay stage, to render them conductive. As a result the load transistors L1 to L3 and the driver transistor
Tr4 become non-conductive, whereas the driver transistors Tr1 and Tr2 become conductive. At the end of the setting signal RS, the transistors
RT, Tr3 and L4 become non-conductive, but the switching state of the other transistors is maintained (at least for a given length of time).If the arrival of a pulse of the setting pulse train S now renders the switching transistor ST1 conductive, the capacitor Cs begins to recharge, so that the transistors L1 to L3 assume the conductive state. With a slight switching delay the transistor Tr4 becomes conductive, and following a further delay this renders the transistors Tr1 and Tr2 non-conductive. This sets in motion an increase in the control voltage at the switching node K, which particularly influences the transistor L1 of the end stage so that the pulse amplitude of the follow-up pulse train T attains the operating voltage potential UDD.
Figure 2 illustrates a modified switching stage, wherein the control electrode of the switching transistor ST1 is connected to the operating voltage potential UDD and the setting pulse train S is connected to its sink electrode. The reset transistor RT is not required, and this is indicated by showing the connection in broken lines. This is because the switching transistors ST1 is permanently conductive and the level of the switching node K is always determined by the level curve of the setting pulse train S. Those components of the overall circuit which have not been illustrated in Fig. 2, namely the delay stage
D and the end stage E, are identical to the corresponding stages of the embodiment shown in Fig. 1.
Examples will now be given of an extension of the new circuit arrangement for the generation of a follow-up pulse train with AND or OR logiclinking of two setting pulse trains, S1 and S2.
Figures 3 to 5 illustrate the modified switching stages, which are effected by the extension measures and which must in each case be supplemented by a delay stage D and an end stage E as shown for the embodiment illustrated in Fig. 1.
Figure 3 illustrates a switching stage suitable for the AND logic-linking of the setting pulse trains S1 and S2, which are connected to the respective control electrodes of two series
connected transistors, ST1 and ST2.
In the embodiment shown in Figure 4, there is
no extra circuitry required for the AND logic
linking of two setting pulse trains S1 and S2, in
comparison to the embodiment shown in Figure
1, since the setting pulse trains S1 and S2 are
respectively connected to the control electrode and the sink electrode of the transistor ST1. It
should be noted that the source of the setting
pulse train S1 is loaded by a capacitance of
greater magnitude than that for the source of the setting pulse train S2.
In the switching stage shown in Figure 5, which serves as an OR gate to logic-link the setting pulse trains 51 and S2, the controlled
channels of the transistors ST1 and ST2 are connected in parallel. The setting pulse trains S1 and S2 are respectively connected to the control electrodes of these two transistors.
The switching stage configurations illustrated by way of examples in Figures 3 to 5 can be readily adopted for the AND or the OR logiclinking of more than two setting pulse trains.
Furthermore the common application of the measures illustrated in Figures 3 and 5 can easily be used to achieve combinations of both AND and
OR logic-linkfunctions. Furthermore in switching stages which are suitable for the AND logiclinking of two or more setting pulse trains it is possible to replace one or possibly more setting pulse trains by blocking signals.
Claims (6)
1. An MOS follow-up pulse train generator for the production of a follow-up pulse train from at least one setting pulse train, the output being provided by a second inverter of an end stage which consists of two inverter stages, each comprising the series combination of a load transistor and a driver transistor, the end stage being driven by a delay stage which consists of two inverter stages each comprising the series connection of a load transistor and a driver transistor, the junction of the two transistors in the second inverter of the delay stage providing an output to the control electrodes of both inverters of the end stage, and the delay stage being driven by a setting pulse train applied to a switching stage whose output is connected to the control electrode of the load transistor of the first inverter stage of the delay stage, and to the control electrodes of the two load transistors in the end stage.
2. A generator as claimed in Claim 1, in which the switching stage consists of the series combination of a switching transistor whose control electrode is controlled by the setting pulse train and a reset transistor which is controlled by a reset signal, the junction point of these transistors forming the output of the switching stage.
3. A generator as claimed in Claim 1, in which the switching stage consists of a switching transistor whose source electrode forms the output of the switching stage, its control electrode being connected to the operating voltage potential that is applied to the sink electrode of the load transistors and its sink electrode connected to receive the setting pulse train.
4. A generator as claimed in Claim 2, comprising an OR-gate for logic-linking a plurality of setting pulse trains, said first switching transistor being connected in parallel with one or more additional switching transistors, each having its control electrode connected to a respective setting pulse train input.
5. A generator as claimed in Claim 2 or Claim 4, comprising an AND gate for logic-linking a plurality of setting pulse trains, said or each said first switching transistor being connected in series with one or more additional switching transistors each having its control electrode connected to a respective setting pulse train input.
6. An MOS follow-up pulse train generator substantially as described with reference to Figure 1, or as modified with reference to any one of
Figures 2 to 5.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19813144513 DE3144513C1 (en) | 1981-11-09 | 1981-11-09 | Circuit arrangement in MOS technology for generating a subsequent clock from at least one set clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2110494A true GB2110494A (en) | 1983-06-15 |
Family
ID=6145989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08230735A Withdrawn GB2110494A (en) | 1981-11-09 | 1982-10-27 | MOS follow-up pulse train generators |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS58129825A (en) |
| DE (1) | DE3144513C1 (en) |
| GB (1) | GB2110494A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58181319A (en) * | 1982-04-19 | 1983-10-24 | Hitachi Ltd | Timing generating circuit |
| JP2518810B2 (en) * | 1983-11-29 | 1996-07-31 | 富士通株式会社 | Semiconductor integrated circuit device |
| JPS6182527A (en) * | 1984-09-29 | 1986-04-26 | Mitsubishi Electric Corp | Pulse generating circuit |
| JPS62239399A (en) * | 1986-04-09 | 1987-10-20 | Nec Corp | Signal generator |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3898479A (en) * | 1973-03-01 | 1975-08-05 | Mostek Corp | Low power, high speed, high output voltage fet delay-inverter stage |
| US4061933A (en) * | 1975-12-29 | 1977-12-06 | Mostek Corporation | Clock generator and delay stage |
| DE2816980C3 (en) * | 1978-04-19 | 1980-10-09 | Ibm Deutschland Gmbh, 7000 Stuttgart | FET driver circuit with short switching times |
-
1981
- 1981-11-09 DE DE19813144513 patent/DE3144513C1/en not_active Expired
-
1982
- 1982-10-27 GB GB08230735A patent/GB2110494A/en not_active Withdrawn
- 1982-11-08 JP JP57195844A patent/JPS58129825A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58129825A (en) | 1983-08-03 |
| DE3144513C1 (en) | 1983-05-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4074148A (en) | Address buffer circuit in semiconductor memory | |
| US4029973A (en) | Voltage booster circuit using level shifter composed of two complementary MIS circuits | |
| US6525587B2 (en) | Semiconductor integrated circuit device including a clock synchronous type logical processing circuit | |
| JPH07120225B2 (en) | Semiconductor circuit device | |
| JPS61126686A (en) | Word line clock boosting cricuit for semiconductor memory | |
| US5010338A (en) | Comparator circuit and analog to digital converter | |
| US5136191A (en) | Output buffer circuit for lsi circuit | |
| US6906569B2 (en) | Digital signal delay device | |
| GB2110494A (en) | MOS follow-up pulse train generators | |
| US5049761A (en) | CMOS pulse width modulator | |
| JP2501590B2 (en) | Driving circuit for semiconductor device | |
| US4195238A (en) | Address buffer circuit in semiconductor memory | |
| KR970067328A (en) | Boost circuit | |
| US4268900A (en) | Device for controlling a plurality of converters | |
| US5170118A (en) | Circuit and method for testing inverter drive logic switching patterns | |
| JPH03222518A (en) | Integrated circuit device | |
| US4730125A (en) | Arrangement for synchronizing the pulse-width-modulated clock signals of several clocked direct voltage converters | |
| EP1303914B8 (en) | Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal | |
| US3210568A (en) | Directly coupled unbalanced tunnel diode pairs for logic circuits | |
| US20240097564A1 (en) | Charge pump circuit and drive device | |
| US3209264A (en) | Multiple output sequential signal source | |
| US6667646B2 (en) | Small-sized digital generator producing clock signals | |
| JP2617930B2 (en) | Pulse output circuit | |
| KR200296046Y1 (en) | A frequency divider | |
| JP2776643B2 (en) | Clock drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |