GB2107926A

GB2107926A - Semiconductor device and method of manufacture

Info

Publication number: GB2107926A
Application number: GB08226962A
Authority: GB
Inventors: D Michael Rynne
Original assignee: Monolithic Memories Inc
Current assignee: Monolithic Memories Inc
Priority date: 1981-10-13
Filing date: 1982-09-21
Publication date: 1983-05-05
Also published as: FR2514559A1; JPS5873132A; DE3237026A1

Abstract

Regions of semiconductor material are separated by grooves, an insulating layer (107) is then formed on the surface of the semiconductor material including the surfaces of the grooves, and polyimide material (108) is formed over the top surface of the insulating layer and the grooves to fill the grooves and to provide a substantially smooth top surface over the structure. An interconnective material (111) such as aluminium is then formed over the polyimide material and contacts active regions (103, 104) in the underlying islands of semiconductor material through vias (120, 121) formed in the polyimide material and the insulating layer. Polyimide is applied to the device in a low temperature process, so the PN junctions defining the active regions of the device are not altered by any high temperature, long duration, thermal oxidation processes and thus device characteristics and yield are improved over prior art structures. <IMAGE>

Description

SPECIFICATION A semiconductor device This invention relates to semiconductor devices and to methods for making semiconductor devices.

Various ways have been proposed to isolate eloctrically a plurality of pockets of semiconductor material, in each of which one or more circuit elements can be formed. Among the ways proposed have been appropriately biased PN junctions (Noyce U.S.Patent Specification No.

3,117,260 issued Jan. 7, 1964), combinations of PN junctions and zones of intrinsic and extrinsic semiconducting materials (Noyce U.S. Patent Specification No. 3,150,299 issued Sept. 22, 1964), dielectric isolation (Frescura U.S. Patent Specification No. 3,391,023 issued July 2, 1968) and mesa etching (Frescura et al U.S. Patent Specification No. 3,489,961 issued Jan. 13, 1970). Tucker and Barry, in U.S. Patent Specification No. 3,736,193, issued May 29, 1973, disclose the use of selectively-doped polycrystalline silicon to isolate islands of singlecrystal silicon in which circuit elements can be formed.

In the manufacture of integrated circuits, several problems arise. First, the area of the wafer required for the placement of the isolation regions between adjacent pockets of semiconductor material is a significant portion of the total wafer area. A large isolation area reduces the number of devices which can be placed in a wafer and thus lowers the "pakcing density" of the circuit elements formed in the wafer. Second, the leads formed on, and adherent to, the insulation on the wafer surface sometimes crack at steps in the insulation on the wafer surface. These steps are often quite steep. Third, several of the isolation techniques result in significant capacitances being introduced into the integrated circuit.While at low frequencies these capacitances do not affect the operation of the circuit, at high frequencies these capacitances can have a significant effect on circuit performance. Fourth, the processes by which prior art integrated circuits are isolated are carried out at a relatively high temperature, resulting in shifts in the locations of previously formed PN junctions, thereby reducing the accuracy with which device characteristics can be predicted. As semiconductor devices become smaller, this effect becomes more important.

This invention approaches the problem of isolating pockets of semiconductor material in an integrated circuit from a different perspective.

Recognizing that important advantages (lower cost, more predictable device characteristics) result by eliminating one or more high temperature processing steps, the preferred embodiment of this invention uses a relatively low temperature process to form the isolated pockets of semiconductor material in an integrated circuit.

Accordingly, one aspect of the present invention provides a semiconductor device comprising: a semiconductor wafer comprising a semiconductor substrate; grooves formed in the top surface of the said substrate to form islands of semiconductor material from the said wafer, each island of semiconductor material being laterally separated from adjacent islands of semiconductor material by grooves formed in the surface of the said semiconductor material; an insulating layer formed on the surface of the semiconductor material including the surfaces of the said grooves; and polyimide material formed over the top surface of the said insulating layer over the said semiconductor material and the said grooves to fill the grooves and to provide a substantially smooth top surface overlying both the grooves and the islands of semiconductor material.

A second aspect provides a method of forming an integrated circuit which comprises: forming selectively doped regions in the top surface of a semiconductor material; forming grooves surrounding selected portions of the top surface of the semiconductor material, the said grooves extending for a selected thickness into the semiconductor material; forming a dielectric layer over the top surface of the grooves and the semiconductor material; and forming a polyimide layer over the dielectric layer of the grooves and the semiconductor material.

In accordance with features or preferred features of this invention, polyimide is placed in grooves in semiconductor material to provide both electrical isolation between adjacent devices within the semiconductor device made from the material and a substantially flat surface for receipt of conductive interconnects. The grooves are formed deep in the semiconductor material, preferably by etching. In the case where the semiconductor device employs an epitaxial silicon layer formed on a silicon substrate, the grooves are formed through the epitaxial layer to the underlying silicon substrate. When the semiconductor material is silicon, the surface of the etched cuts and the semiconductor material is oxidized to provide electrical isolation between the various semiconductive regions exposed by the etched cuts and to provide good adhesion of the polyimide to the wafer.The oxidized etched cuts are then backfilled with polyimide, thus producing a highly smooth device surface. With a smooth device surface, electrical interconnects are formed on the device surface without the sharp steps over the isolation etch cuts experienced by prior art structures.

While polyimide is well known in the prior art, and is described in, for example, U.S. Patent Specification No. 4,273,886, the novel use of polyimide in accordance with this invention has been found to lead to several advantages. Because polyimide is deposited at a relatively low temperature, the locations of previously formed PN junctions are more predictable and device characteristics therefore are more certain. The top surface of the polyimide height changes or "steps" which crack leads. The process for applying polyimide is relatively low temperature, thus not adversely affecting yields.

Polyimide has been used in a variety of ways in the fabrication of semiconductor devices. For example, United States Patent Specification No.

3,978,578 describes a structure utilising polyimide as a protective coating on the top surface of a semiconductor die. After the die is placed in a package and bonding wires are connected between the semiconductor die and external leads, the device and bonding wires are coated with a second polyimide film to protect both the top surface of the semiconductor die and the bonding wires.

Another use of polyimide in the semiconductor art is described in U.S. Patent Specifications Nos.

3,801,880; 3,846,166; 4,001,870; 4,040,083 and 4,060,828, in which a polyimide layer is used to electrically insulate a first layer of electrical interconnects formed on the surface of a substrate from a second layer of electrical interconnects formed above the first layer of interconnects.

None of these references suggests the use of polyimide to assist in electrically isolating the active regions of the semiconductor device.

So that this invention may be more fully understood and so that further features thereof may be appreciated, devices in accordance with the present invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a cross-sectional view of a prior art semiconductor wafer containing a plurality of components; Figure 2 is a cross-sectional view of a semiconductor wafer of the sort shown in Figure 1 but which contains isolation etch cuts and polyimide in accordance with this invention; and Figure 3 is a cross-sectional view of the device of Figure 2 which contains contact openings through the polyimide layer and an interconnect pattern connecting various portions of various devices as desired.

Figure 1 shows a typical prior art NPN transistor. NPN transistor 10 of Figure 1 comprises P type substrate 100, typically of silicon although other semiconductor materials such as germanium can also be used, N type buried layer 101 serving as the collector, Nepitaxial layer 102, P type base region 103, N type emitter region 104 and N type collector contact 105. Such a bipolar transistor is constructed in a conventional manner, such as is described in United States Patent Specification No. 3,025,589.

A bipolar integrated circuit contains a plurality of these or similar devices each typically formed in a separate island of semiconductor material electrically isolated from adjacent islands of semiconductor material.

In accordance with one embodiment of this invention involving the use of a silicon epitaxial layer on a silicon substrate, isolation regions 106 (also called "grooves") are cut into the epitaxial layer 102 between adjacent regions of epitaxial layer 102 which are to be isolated, as is shown in Figure 2. Prior to the formation of these grooves, the active device regions such as base 103, emitter 104, and collector contact 105 have been formed using standard, well-known procedures.

Grooves 106 are preferably formed in a silicon wafer having crystal orientation < 100 > , by an anisotropic etch with, for example KOH as the chemical etchant. The use of such an anisotropic etch to form grooves in a silicon layer having a "V" shape is described in, for example, United States Patent Specification No. 3,924,265, by D. B. Lee in an article entitled "Anisotropic Etching of Silicon" appearing in the Journal of Applied Physics, Vol. 40, No. 11, October 1965, pages 4569 to 4574 and by R. M. Finne and E. L. Klein in an article entitled "A water Amine Complexing Agent System for Etching Silicon" appearing in the Journal of the Electrochemical Society, Solid State Science, September,1967, pages 965 to 970.Alternatively, the grooves may be formed in a silicon wafer having crystal orientation < 100 > or < 111 > using a CF4 plasma etch. In general, any technique for forming isolation cuts or grooves in the epitaxial layer 102 may be employed, since the resulting etch cut need not be of the "V" shape.

Use of isolation grooves of other than the "V" shape results in wider cuts at the base of the grooves 106, thus facilitating alignment of the mask used to define the grooves 106. The grooves 106 are preferably etched completely through the epitaxial layer 102 and slightly into the P type substrate 100, as is shown in Figure 2. In the completed device these isolation grooves will be used to help provide electrical isolation between adjacent islands of semiconductor material within the epitaxial layer 102. For example, due to the presence of grooves 106-1 and 1 06-3, base region 103, emitter region 104 and collector contact 105 are isolated from adjacent devices (not shown) contained within other silicon islands formed from the epitaxial layer 102.

The surfaces of the epitaxial layer 1 02 exposed by the isolation grooves 106 are then oxidized, thus forming a dielectric layer 107. The dielectric layer 107 insulates the surface of the epitaxial layer 102, including etch cuts 106, thus preventing leakage currents between semiconductor regions along the surface of the isolation grooves 106. The dielectric layer 107 also insulates the surface of the epitaxial layer 102 and the first electrical interconnect layer 190.

The use of oxide on the surfaces of isolation grooves is well known and is described in, for example, United States Patent Specification No.

3,391 ,023. Dielectric layers 107 comprising oxide may be formed by, for example, thermal oxidation in steam for approximately 30 minutes at approximately 850-9500C, thus forming oxide layers 107 of approximately 300-1 000A in thickness. Alternatively, dielectric layers 107 may comprise oxide formed by low pressure chemical vapour deposition at approximately 800-9000C to a thickness of approximately 300-1 000A.

Dielectric layers 107 preferably comprise silicon nitride formed by, for example, low pressure chemical vapour deposition at approximately 800--9000C to a thickness of approximately 300-1 000A. Dielectric layers 107 may also comprise a combination of oxide and nitride. The formation of silicon nitride on a prior art wafer required the formation of a thin oxide layer between the silicon wafer and the silicon nitride to provide stress relief at high temperatures due to the mismatch between the thermal coefficient of expansion of silicon and silicon nitride. It has been found possible, in accordance with this invention, to eliminate long, high temperature thermal oxidation, thus eliminating the need for an oxide layer to provide stress relief between the silicon wafer and the silicon nitride.Thus, when silicon nitride is used as the dielectric 107, the process step whereby an intermediate layer of silicon oxide is formed has been eliminated, as has the additional process step required to remove the stress-relief oxide from areas of the wafer where the stress relief oxide is not desired.

Vias are then formed in the dielectric layer 107 to allow the connection of underlying regions to the to-be-formed electrical interconnect layer 190.

Via 122 is formed in dielectric layer 107 by well known photolithographic techniques and etching.

Portions of the dielectric layer 107 which comprise oxide are etched with buffered HF, for example. Portions of dielectric layer 107 which comprise nitride are etched with CF4 plasma, for example.

A first electrical interconnect layer 1 90 is then formed over the surface of the wafer and patterned to provide the desired electrical interconnections. Electrical interconnect layer 190 typically comprises polycrystalline silicon formed to a thickness of approximately 500-5000A by low pressure chemical vapour deposition.

Polycrystalline silicon layer 190 is then patterned by, for example, using well known photolithographic techniques and etching with CF4 plasma. Figure 2 shows electrical interconnection layer 190 patterned to make contact with collector contact 105.

A layer of polyimide 108 is then formed over the entire surface of the wafer to a thickness "d" of approximately 2-4 microns. A coating coupler is formed on the surface of the wafer in order to provide good adherence to the to-be-formed polyimide 108 to the underlying dielectric layer 107. The coating coupler preferably comprises "PlO coupler 3" sold by Hitachi. Approximately 3-5 grams of coupler is applied to a 4" (10 cm) wafer, and the wafer is spun at approximately 4,000 rpm for approximately 30 seconds to form a thin, uniform layer of coupler. The coupler is then cured by baking the wafer at approximately 3500C for approximately 30 minutes in dry air or dry oxygen. This results in a coupler thickness of approximately 100 150A.

The polyimide material is preferably "pit13" polyimide sold by Hitachi. Approximately 2-6 grams of PIQ13 is applied to a 4" (10 cm) wafer, and the wafer is spun at approximately 3,000-3,500 rpm for approximately 30 seconds.

This forms a thin substantially uniform layer of P1013 material on the surface of the wafer. The P1013 material is then cured by baking the wafer at approximately 1 000C for approximately 1 hour in dry nitrogen, followed by baking the wafer at approximately 2000C for approximately 1 hour in dry nitrogen. A second layer of P1013 material is applied to the surface of the wafer, with approximately 2-6 grams of P1013 material being applied to the wafer.The wafer is then spun at approximately 3,000-3,500 rpm for approximately 30 seconds, and the second layer of PIQ13 material is cured by baking the wafer at approximately 1000C for approximately 1 hour in dry nitrogen, followed by baking the wafer at approximately 2000C for approximately 1 hour in dry nitrogen, followed by baking the wafer at approximately 3500C for approximately 1 hour in dry nitrogen. This results in a polyimide layer 108 of approximately 1.5-4.0 microns.

Polyimide 108 adheres well to the coupler (not shown) formed on dielectric 107 and forms a firm base on which to deposit conductive interconnect material for use in forming the interconnect lead pattern required to complete the integrated circuit.

Because the polyimide region 108 is formed to a thickness of approximately 1.5-4.0 microns, the isolation grooves 106, having a depth of approximately 1.0-1.5 microns, are back-filled and the surface of polyimide region 108 is smooth and substantially flat. The fact that the surface of the polyimide region 108 is substantially flat allows the to-be-formed electrical interconnects (typically aluminium) to be applied to the surface of the wafer without the interconnect layer encountering steep "steps" over the isolation grooves 106. Such steep "steps" in interconnects generally pose quality and reliability problems because the thickness of the interconnects at such steps is generally very thin, and the interconnects are thus prone to breakage, thus possibly resulting in an open circuit.Furthermore, without the use of the polyimide layer 108, the to-be-formed interconnect layer will cover the surface of the oxide dielectric layer 107, with the result that any defects or "pinholes" in the oxide dielectric layer 107 will allow an electrical short circuit to be formed between the interconnect layer and the semiconductor region exposed by the pinhole. The pinhole problem has been found to be ellminated by the use of the polyimide layer 108.

Channel stop regions 190-1 and 190-2 are formed in a well known manner within substrate 100 in order to provide electrical isolation between adjacent transistor regions. In Figure 2, channel stops 1 90-1 and 190-2 provide electrical isolation between the transistor comprising buried layer collector region 101, base region 103, emitter region 104, and collector contact 105, from adjacent devices (not shown).

When substrate 100 is a P type substrate, channel stops 190-1 and 1 90-2 are highly doped P+ regions formed by, for example, ion implantation of P type dopants (typically boron) to a density of approximately 1014 atoms per cm2.

As is shown in Figure 3 (not drawn to scale), contact openings are formed within polyimide layer 108 and dielectric layer 107, thus exposing underlying regions which are to be electrically contacted by the to-be-formed electrical interconnects 111. By way of example, Figure 3 shows a contact opening 120 formed to expose the base region 103, and another contact opening 121 formed to expose the emitter region 104. The remaining portions of polyimide layer 108 electrically insulate interconnects 111 from the underlying active device regions.The contact openings 120 and 121 are formed by, for example, suitable photolithographic masking, techniques well known in the semiconductor arts, and by etching undesired portions of the polyimide layer 108 with, for example, a solution of 97% tetramethyl ammonium hydroxide and 3% ethylene diamide, and then etching the dielectric layer 107 as described above. Upon its availability, polyimide 108 preferably comprises photosensitive polyimide. The photosensitive polyimide is formed on the surface of the semiconductor wafer and selective regions of the polyimide are exposed to actinic radiation (typically ultraviolet light) through a contact mask.

The polyimide 108 is then developed, with the regions previously exposed to actinic radiation becoming fixed, and all other regions being removed by a solvent, thus forming a permanent layer 108 of polyimide containing contact openings 120 and 121.

After the formation of the contact openings, a layer of electrically conductive material (typically aluminium) is formed on the surface of the wafer, thus forming electrical contact with regions exposed by the aforementioned contact openings.

Aluminium metalization, if used as the interconnect layer 111, is formed in a well known manner at a sufficiently low temperature to prevent damage to the polyimide layer 108 (see, for example, U.S. Patent Specification No.

3,108,359). The aluminium metalization layer 111 is then patterned utilising well-known techniques, such as masking with photoresist and etching selected regions of aluminium 111 with a well known aluminium etchant, such as a mixture of acetic, nitric and phosphoric acids, or by plasma etching with silicon tetrachloride, thus providing a plurality of electrical interconnects on the surface of the wafer connecting desired regions exposed by the formation of contact openings.

Importantly, the entire isolation process, including the steps of forming the isolation grooves 106, oxide dielectric layers 107, the polyimide layer 108, and the electrical interconnects 111 preferably takes place at temperatures less than approximately 4000 C.

Prior art isolation processes in which thermal oxide is used as the isolation means require the wafer to be subjected to temperatures in the range of approximatley 800-1 0000C for long periods of time after the formation of the buried layer collector 101. In such prior art devices, the dopants within the buried layer collector 101 are redistributed during the growth of thermal oxide isolation, including diffusion of the buried layer dopants upwards into the epitaxial layer. Such upward diffusion reduces the distance between the buried layer collector 101 and the base 103, thus lowering the collector-base breakdown voltage and increasing the current gain (beta) of the transistor, increases the collector-base capacitance, and reduces the switching speed of the transistor.

In contrast, in accordance with preferred embodiments of this invention the need for thermally grown isolation oxide is eliminated, thereby not subjecting the buried layer collector region 101 to the associated high temperatures over long periods of time. Thus, the fabrication of semi-conductor devices in accordance with this invention has allowed the diffusion profiles of dopants to remain substantially unchanged by the formation of the isolation comprising grooves 106-1 to 106-3 and polyimide layer 108, as compared with prior art devices which utilise thermal oxide, which is necessarily formed over long periods of time at high temperatures.The faci that the diffusion profiles remain substantially unchanged is of particular importance at the surfaces of the isolation grooves 106-1 to 106-3. The unchanged diffusion profiles made possible by the use of isolation regions formed in accordance with preferred embodiments of this invention have resulted in a semiconductor device having shallower diffusions, and devices whose junctions terminate at the surfaces of the isolation grooves, rather than terminating at some distance inward from the thermal oxide isolation of prior art devices due to redistribution of the dopants during growth of the thermal oxide. These factors have resulted in the formation of a semiconductor structure having lower leakage currents, and therefore more stable current gain (beta) than prior art devices. Furthermore, structures constructed in accordance with this invention have had decreased capacitance and shorter transit distances for current carriers due to the shallower diffusions, thus resulting in increased switching speed as compared with prior art devices.

Claims

1. A semiconductor device comprising: a semiconductor wafer comprising a semiconductor substrate; grooves formed in the top surface of the said substrate to form islands of semiconductor material from the said wafer, each island of semiconductor material being laterally separated from adjacent islands of semiconductor material by grooves formed in the surface of the said semiconductor material; an insulating layer formed on the surface of the semiconductor material including the surfaces of the said grooves; and polyimide material formed over the top surface of the said insulating layer over the said semiconductor material and the said grooves to fill the grooves and to provide a substantially smooth top surface overlying both the grooves and the islands of semiconductor material.

2. A device according to claim 1 wherein the said isolating layer formed on the surface of the semiconductor material including the surfaces of the grooves comprises an oxide of the semiconductor material.

3. A device according to claim 1 wherein the said insulating layer formed on the surface of the semiconductor material including the surfaces of the grooves comprises a nitride of the semiconductor material.

4. A device according to claim 1 wherein the said insulating layer formed on the surface of the semiconductor material including the surfaces of the grooves comprises a layer of nitride of the semiconductor material formed on a layer of an oxide of the semiconductor material.

5. A device according to any one of the preceding claims which further includes a first interconnection lead pattern between the said insulating layer and the polyimide material.

6. A device according to claim 5 wherein the said first interconnective lead pattern is polycrystalline silicon.

7. A device according to claim 5 or 6 which further includes a first set of vias formed through selected portions of the said insulating layer, thereby allowing contact from the said first interconnecting lead pattern to selected diffused regions formed in the said islands of the semiconductor material.

8. A device according to claim 7 including a second set of vias formed through selected portions of the said polyimide material and the underlying insulator material to form contact regions to selected diffused regions formed in the said islands of the semiconductor material.

9. A device according to claim 8 wherein the said device includes a second interconnective lead pattern formed over the top surface of the device to interconnect selected regions formed in the said islands of semiconductor material through the said vias to form an integrated circuit.

10. A device according to claim 9 wherein the said second interconnective lead pattern comprises aluminium.

11. A device according to any one of the preceding claims wherein the said polyimide semiconductor material is formed over the top surface of the said islands to a selected thickness of no greater than four microns.

12. A device according to any one of the preceding claims wherein the said semiconductor material comprises silicon.

1 3. A device according to any one of the preceding claims which further includes respective highly doped regions beneath the bottoms of selected said grooves, the said highly doped regions serving as channel stop regions.

14. A method of forming an integrated circuit which comprises: forming selectively doped regions in the top surface of a semiconductor material; forming grooves surrounding selected portions of the top surface of the semiconductor material, the said grooves extending for a selected thickness into the semiconductor material; forming a dielectric layer over the top surface of the grooves and the semiconductor material; and forming a polyimide layer over the dielectric layer of the grooves and the semiconductor material.

15. A method according to claim 14 including the additional steps of forming vias through selected regions of the said dielectric layer to expose selected said selectively doped regions and forming an interconnective lead pattern over the dielectric layer and through the said vias to the said selectively-doped regions.

16. A method according to claim 14 including the additional steps of forming vias through selected regions of the said polyimide layer and the underlying dielectric layer to expose selected said selectively-doped regions; and forming an interconnective lead pattern over the top surface of the polyimide layer and through the said vias to the said selectively-doped regions.

17. A method according to claim 15 or 16 wherein the interconnective lead pattern comprises polycrystalline silicon.

18. A method according to claim 15 or 16 wherein the interconnective lead pattern comprises aluminium.

19. A method according to any one of claims 14 to 18 wherein the semiconductor material is silicon.

20. A device comprising: a plurality of conductive regions within a semiconductive substrate and insulation regions formed between the said conductive regions, the insulation regions comprising grooves formed in the substrate having a layer of insulating material formed on the surface of the grooves and filled with polyimide, thereby forming a substantially smooth substrate surface.

21. A semiconductor device substantially as described herein with reference to, and as shown in, Figures 2 and 3 of the accompanying drawings.

22. A method of forming a semiconductor device substantially as described herein with reference to Figures 2 and 3 of the accompanying drawings.

23. Any novel feature or combination of features disclosed herein.