DE3728348A1 - Multilayer wiring for VLSI semiconductor components - Google Patents

Multilayer wiring for VLSI semiconductor components

Info

Publication number
DE3728348A1
DE3728348A1 DE19873728348 DE3728348A DE3728348A1 DE 3728348 A1 DE3728348 A1 DE 3728348A1 DE 19873728348 DE19873728348 DE 19873728348 DE 3728348 A DE3728348 A DE 3728348A DE 3728348 A1 DE3728348 A1 DE 3728348A1
Authority
DE
Germany
Prior art keywords
silicon nitride
layer
polyimide
etching
flanks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19873728348
Other languages
German (de)
Inventor
Alexander Dr Phil Gschwandtner
Nicholas Dr Rer Nat Kokkotakis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19873728348 priority Critical patent/DE3728348A1/en
Publication of DE3728348A1 publication Critical patent/DE3728348A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to multilayer wiring for VLSI (very-large-scale-integrated) semiconductor components containing a multilayer dielectric which consists of polyimide (3) and silicon nitride layers (6, 8) and has through-connections (interfacial connections, feedthroughs) with oblique flanks (5), the flanks (5) of the through-connections being completely covered with silicon nitride (6), and to a method for the fabrication thereof. This in the first instance involves applying a polyimide layer (3) over the first metallisation plane (2) and subjecting it to thermal treatment. The through-connections are defined by means of a photoresist technique (4). In the subsequent reactive ion beam etching of the contact holes (vias), the oblique flanks (5) of the photoresist pattern (4) serving as the etching mask are transferred to the polyimide layer (3). The remaining photoresist pattern (4) is removed, a silicon nitride layer (6) is deposited over the whole area, is oxidised by means of anodic oxidation in the contact hole bottoms and finally removed. This achieves improved insulation of the polyimide layer (3) against absorption of moisture. The oblique flanks (5) of the contact holes ensure that the edges of the next metallisation plane are well covered. <IMAGE>

Description

Die Erfindung betrifft eine Mehrlagenverdrahtung für höchst­ integrierte Halbleiterbauelemente mit einem aus Polyimid- und Siliziumnitridschichten bestehenden Mehrschichtdielektrikum zwischen den Metallisierungsebenen und mit schrägen Flanken auf­ weisenden Durchkontaktierungen, sowie ein Verfahren zu ihrer Herstellung.The invention relates to multi-layer wiring for the highest Integrated semiconductor devices with a polyimide and Silicon nitride layers existing multilayer dielectric between the metallization levels and with sloping flanks pointing vias, and a method for their Manufacturing.

Bei der ständig steigenden Packungsdichte von VLSI-Halbleiter­ bauelementen ist die Mehrschichtmetallisierung einer der be­ grenzenden Faktoren für eine weitere Erhöhung der Integration. Zum Anschluß und zur Verdrahtung der Transistoren und anderer Bauelemente auf VLSI-Chips sind meist mehr als zwei Metalli­ sierungsebenen erforderlich. Verläßliche Strukturen können nur noch dann erhalten werden, wenn die Zwischenschichten vor dem Aufbringen jeder weiteren Metallisierungsebene planarisiert wer­ den.With the ever increasing packing density of VLSI semiconductors multi-layer metallization is one of the components limiting factors for a further increase in integration. For connecting and wiring transistors and others Components on VLSI chips are usually more than two metals levels required. Reliable structures can only still be obtained if the intermediate layers before the Application of every further level of metallization the.

Zum Planarisieren gut geeignet sind Schichten aus Polyimid. Diese ermöglichen einen hohen Einebnungsgrad, sind thermisch stabil und haben die zur Isolation der einzelnen Leiterbahnen erforderlichen exzellenten dielektrischen Eigenschaften. Auch weisen Polyimidschichten eine niedrige Porendichte auf und sind in einem einfachen und billigen Prozeß herzustellen.Layers of polyimide are well suited for planarization. These enable a high degree of leveling and are thermal stable and have the insulation for the individual conductor tracks required excellent dielectric properties. Also have polyimide layers and have a low pore density to manufacture in a simple and inexpensive process.

Allerdings begrenzt der hygroskopische Effekt des Polyimids die Verwendung dieser organischen Schichten auf Halbleiterbauele­ menten. Um eine zu starke Wasseraufnahme zu vermeiden, sind nach dem Aufbringen von Polyimid nur noch "trockene" Techniken erlaubt; Naßätzung etwa muß vermieden werden. Außerdem weisen bevorzugt aus Aluminium/Silizium/Titan-Legierungen gefertigte Leiterbahnen eine schlechte Haftung auf Polyimid auf. However, the hygroscopic effect of the polyimide limits the Use of these organic layers on semiconductor devices ment. To avoid excessive water absorption after the application of polyimide only "dry" techniques allowed; Wet etching, for example, must be avoided. Also point out preferably made of aluminum / silicon / titanium alloys Conductors have poor adhesion to polyimide.  

Einen weitgehenden Feuchtigkeitsausschluß erreicht man bei Ver­ wendung eines sandwichartig aus Polyimid- und Siliziumnitrid­ schichten bestehenden Mehrschichtdielektrikums, wie es zum Bei­ spiel von H. Fritsche et. al. in einem Beitrag zur IEEE VLSI Multilevel Interconnection Conference 1985, Katalog Nr. 85, Sei­ te 253, beschrieben wird. Die Siliziumnitridschicht dient beim Ätzen der Durchkontaktierungen als Ätzmaske für die Polyimid­ schicht und ist einem Beitrag von H. Eggers et. al. zur IEEE VLSI Multilevel Interconnection Conference 1985, Katalog Nr. 85, Seite 163, zu entnehmen.Extensive moisture exclusion can be achieved with Ver application of a sandwich made of polyimide and silicon nitride layers of existing multilayer dielectric, such as for the case game by H. Fritsche et. al. in a contribution to the IEEE VLSI Multilevel Interconnection Conference 1985, Catalog No. 85, Sc te 253. The silicon nitride layer serves for Etching of the vias as an etching mask for the polyimide layer and is a contribution by H. Eggers et. al. to the IEEE VLSI Multilevel Interconnection Conference 1985, catalog no. 85, page 163.

Doch ergeben sich bei dieser Technik verschiedene Nachteile. Bei anisotroper reaktiver Ionenätzung (RIE) geraten die Flanken der Durchkontaktierungen zu steil. Dies führt beim Aufbringen der nächsten Metallisierungsebene zu einer schlechten Kantenbe­ deckung. Mit reaktiver Ionenstrahltechnik (RIBE) werden zwar flachere Flanken erzielt, doch ergeben sich dabei fertigungs­ technische Probleme. Außerdem liegen nach diesem Schritt die Polyimidätzflanken frei und können im nachfolgenden Prozeß­ schritt Feuchtigkeit aufnehmen.However, there are several disadvantages with this technique. In the case of anisotropic reactive ion etching (RIE), the flanks come out the vias too steep. This leads to the application the next level of metallization to a bad edge cover. With reactive ion beam technology (RIBE) flatter flanks achieved, but there are manufacturing technical problems. In addition, after this step the Polyimide etching edges free and can be used in the subsequent process step absorb moisture.

Aufgabe der vorliegenden Erfindung ist es daher, eine Mehrla­ genverdrahtung anzugeben, die diese Nachteile vermeidet, und die in einem einfachen Prozeß herzustellen ist.The object of the present invention is therefore a Mehrla Specify gene wiring that avoids these disadvantages, and which can be produced in a simple process.

Diese Aufgabe wird durch eine Mehrlagenverdrahtung der eingangs erwähnten Art erfindungsgemäß dadurch gelöst, daß die Flanken der Durchkontaktierungen vollständig mit Siliziumnitrid bedeckt sind.This task is accomplished by multi-layer wiring the input mentioned type according to the invention solved in that the flanks of the vias completely covered with silicon nitride are.

Ein Verfahren zum Herstellen der erfindungsgemäßen Mehrlagenver­ drahung besteht aus den folgenden Verfahrensschritten:A method for producing the multi-layer ver drahung consists of the following process steps:

  • a) Aufbringen und Tempern einer Polyimidschicht,a) applying and annealing a polyimide layer,
  • b) Durchführung einer Photolacktechnik zur Definition der Durch­ kontaktierungen,b) Implementation of a photoresist technique to define the through contacts,
  • c) anisotrope Ätzung der Kontaktlöcher bzw. Vias in der Polyi­ midschicht mit der Photolackstruktur als Ätzmaske,c) anisotropic etching of the contact holes or vias in the polyi  mid layer with the photoresist structure as an etching mask,
  • d) Entfernen der restlichen Ätzmaske,d) removing the remaining etching mask,
  • e) ganzflächige Abscheidung einer Siliziumnitridschicht,e) full-surface deposition of a silicon nitride layer,
  • f) anodische Oxidation der Siliziumnitridschicht in den Be­ reichen, wo die Schicht die Böden der Kontaktlöcher bedeckt,f) anodic oxidation of the silicon nitride layer in the Be range where the layer covers the bottoms of the vias,
  • g) Entfernen der oxidierten Siliziumnitridbereiche undg) removing the oxidized silicon nitride regions and
  • h) Aufbringen der nächsten Metallisierungsebene.h) applying the next metallization level.

Weitere Ausgestaltungen der Erfindung sind den Ünteransprüchen zu entnehmen.Further embodiments of the invention are the subclaims refer to.

Durch die erfindungsgemäße vollständige Bedeckung der Polyimid­ ätzflanken mit dem nicht hygroskopischen Siliziumnitrid wird eine nachträgliche Feuchtigkeitsaufnahme des Polyimid vermieden und die Fehlerdichte der Polyimidschicht reduziert. Durch die Verwendung einer organischen Ätzmaske für die Ätzung der Durch­ kontaktierungen in die Polyimidschicht können flache Ätzwinkel erzeugt werden. Die Flanken der Ätzmaske werden dabei auf das Polyimid übertragen. Auf diese Weise läßt sich bei der ab­ schließenden Metallisierung eine gute Kantenbedeckung erzielen. Die Mehrlagenverdrahtung kann somit lunkerfrei fertiggestellt werden.Through the complete covering of the polyimide according to the invention etching edges with the non-hygroscopic silicon nitride subsequent moisture absorption of the polyimide avoided and reduces the defect density of the polyimide layer. Through the Use an organic etch mask for through etching Contacts in the polyimide layer can have flat etching angles be generated. The edges of the etching mask are on the Transfer polyimide. In this way, the can closing metallization achieve good edge coverage. The multi-layer wiring can thus be completed without voids will.

Im folgenden wird die Erfindung anhand eines Ausführungsbei­ spiels und der Fig. 1 bis 5 näher beschrieben.In the following the invention with reference to a game Ausführungsbei and FIGS . 1 to 5 will be described in more detail.

Dabei zeigenShow

die Fig. 1 bis 4 im Querschnitt die wichtigsten Stationen bei der Herstellung der erfindungsgemäßen Mehr­ lagenverdrahtung, Figs. 1 to 4 in cross section the most important stages in the manufacture of multilayer wiring according to the invention,

Fig. 5 zeigt die fertige Struktur nach einer leicht variierten Ausführungsform des Verfahrens. Fig. 5 shows the completed structure after a slightly varied embodiment of the method.

In Fig. 1 sind Leiterbahnen 2 der ersten Metallisierungsebene eines mikroelektronischen Bauelementes (zum Beispiel eines bipo­ laren gate-arrays) auf einer die Transistoren des Bauelements isolierenden SiO2-Schicht 1 angeordnet. In einem spin-on-Prozeß wird darauf eine Polyimidschicht 3 in einer Stärke von zum Bei­ spiel 1,3 µm aufgebracht. Durch kurzzeitige Temperaturerhöhung wird das Polyimid 3 "gebacken" (zyklisiert).In Fig. 1, tracks 2 are arranged in the first metallization of a microelectronic device (for example, a Bipo stellar gate arrays) on one of the component transistors insulating SiO 2 layer 1. In a spin-on process, a polyimide layer 3 is applied in a thickness of, for example, 1.3 µm. The polyimide 3 is “baked” (cyclized) by briefly increasing the temperature.

Fig. 2: Auf der eingeebneten Oberfläche wird nun ganzflächig eine Photolackschicht 4 aufgebracht (siehe Fig. 2) und struk­ turiert. An den für die späteren Durchkontaktierungen vorge­ sehenen Stellen ist der Photolack 4 bis auf die Polyimidschicht 3 abgetragen. Die Durchbrechungen weisen schräge Flanken 5 auf. Fig. 2: A photoresist layer 4 is now applied over the entire surface (see FIG. 2) and structured. At the locations provided for the later plated-through holes, the photoresist 4 is removed down to the polyimide layer 3 . The openings have inclined flanks 5 .

Fig. 3 zeigt die Struktur nach einem anisotropen RIBE (reakti­ ver Ionenstrahl) Ätzprozeß. Hierbei dient die Photolackstruktur 4 als Ätzmaske. Die schrägen Flanken 5 der Maske werden beim Ätzen der Polyimidschicht 3 beibehalten, bis in den geätzten Löchern die Oberfläche der Leiterbahnen 2 freigelegt ist. Fig. 3 shows the structure after an anisotropic RIBE (reactive ion beam) etching process. Here, the photoresist structure 4 serves as an etching mask. The oblique flanks 5 of the mask are retained during the etching of the polyimide layer 3 until the surface of the conductor tracks 2 is exposed in the etched holes.

Fig. 4: Nun entfernt man den übrigen Photolack 4 mit einem Lö­ sungsmittel. Dann wird ganzflächig in einem Plasma unterstütz­ ten CVD-Verfahren (PECVD) eine Siliziumnitridschicht 6 in einer Stärke von zum Beispiel 0,25 µm abgeschieden. Fig. 4: Now remove the remaining photoresist 4 with a solvent. A silicon nitride layer 6 is then deposited over the entire surface in a plasma-assisted CVD process (PECVD) in a thickness of, for example, 0.25 μm.

Anschließend wird das Bauelement bzw. die Leiterbahnen 2 mit einer Stromquelle verbunden, als Anode geschaltet und in einem zum Beispiel wäßrigen Elektrolytbad gegen eine Gegenelektrode elektrolysiert.Subsequently, the component or the conductor tracks 2 are connected to a current source, switched as an anode and electrolyzed in a, for example, aqueous electrolyte bath against a counter electrode.

Fig. 5 zeigt das Ergebnis dieser anodischen Oxidation. In den über den Leiterbahnen 2 liegenden Bereichen 7 ist die Silizium­ nitridschicht oxidiert. Die dadurch veränderten chemischen Ei­ genschaften bzw. das geänderte Ätzverhalten der oxidierten Be­ reiche 7 gegenüber der unveränderten Siliziumnitridschicht 6 er­ möglicht das Entfernen der Bereiche 7, wodurch in den Kontakt­ löchern die Leiterbahnen 2 freigelegt werden. Fig. 5 shows the result of anodic oxidation. The silicon nitride layer is oxidized in the regions 7 lying above the conductor tracks 2 . The resultant change in chemical characteristics or the modified egg etching the oxidized Be rich 7 relative to the unaltered silicon nitride layer 6 it enables the removal of the portions 7, whereby in the contact holes, the conductor tracks 2 are exposed.

Anschließend wird eine zweite Metallisierungsebene erzeugt. Wahl­ weise können gemäß der Lehre der Erfindung durch Wiederholung der Prozeßschritte weitere Metallisierungsebenen geschaffen wer­ den.A second metallization level is then generated. Choice  can, according to the teaching of the invention, by repetition the process steps created additional levels of metallization the.

Fig. 6 zeigt in leichter Abänderung des Verfahrens eine ähnli­ che Struktur nach dem Entfernen der oxidierten Bereiche. Dabei wird jedoch noch vor dem Aufbringen der Polyimidschicht 3 zu­ nächst eine 20 µm starke PECVD-Siliziumnitridschicht 8 abge­ schieden. Die weiteren Schritte sind identisch. Nur werden bei der anisotropen Kontaktlochätzung nicht, wie in Fig. 3 ge­ zeigt, die Leiterbahnen 2 freigelegt, sondern nur bis zur Ni­ tridschicht 8 geätzt. Bei der anodischen Oxidation werden daher in den Bereichen 9 beide hier übereinander liegenden Nitrid­ schichten 8 und 6 oxidiert. Mit dieser Technik gelingt ein noch besseres Isolieren der Polyimidschicht 3, die nun vollständig von zwei Siliziumnitridschichten 6 und 8 umschlossen wird. Fig. 6 shows in a slight modification of the method a similar structure after the removal of the oxidized areas. In this case, however, before the application of the polyimide layer to the next, a 20 .mu.m thick PECVD silicon nitride layer 8 abge eliminated. 3 The next steps are identical. Only in the anisotropic contact hole etching, as is shown in FIG. 3, the conductor tracks 2 are not exposed, but only etched up to the nitride layer 8 . In the anodic oxidation, therefore, both nitride layers 8 and 6 lying here one above the other are oxidized in the regions 9 . This technique enables an even better insulation of the polyimide layer 3 , which is now completely enclosed by two silicon nitride layers 6 and 8 .

Claims (10)

1. Mehrlagenverdrahtung für höchstintegrierte Halbleiterbauele­ mente mit einem aus einer einebnenden Polyimidschicht und einer darüber liegenden dünneren Siliziumnitridschicht bestehenden Mehrschichtdielektrikum zwischen den Metallisierungsebenen und mit schräge Flanken (5) aufweisenden Durchkontaktierungen, dadurch gekennzeichnet, daß die Flanken (5) der Durchkontaktierungen vollständig mit Siliziumnitrid (6) bedeckt sind.1.Multi-layer wiring for highly integrated semiconductor components with a multilayer dielectric consisting of a leveling polyimide layer and an overlying thinner silicon nitride layer between the metallization levels and with inclined flanks ( 5 ) with plated-through holes, characterized in that the flanks ( 5 ) of the plated-through holes are completely coated with silicon nitride ( 6 ) are covered. 2. Mehrlagenverdrahtung nach Anspruch 1, dadurch ge­ kennzeichnet, daß das Mehrschichtdielektrikum eine Dreifachschicht (8, 3, 6) ist, bei der eine einebnende Polyimidschicht (3) zwischen zwei dünneren Siliziumnitridschich­ ten (8, 6) eingebettet ist.2. Multi-layer wiring according to claim 1, characterized in that the multilayer dielectric is a triple layer ( 8 , 3 , 6 ), in which a leveling polyimide layer ( 3 ) between two thinner silicon nitride layers ( 8 , 6 ) is embedded. 3. Verfahren zum Herstellen einer Mehrlagenverdrahtung nach mindestens einem der Ansprüche 1 oder 2, gekennzeich­ net durch folgende Verfahrensschritte:
  • a) Aufbringen und Tempern einer Polyimidschicht (3),
  • b) Durchführung einer Photolacktechnik (4) zur Definition der Durchkontaktierungen,
  • c) Anisotrope Ätzung der Kontaktlöcher bzw. Vias in der Polyimidschicht (3) mit der Photolackstruktur (4) als Ätzmaske,
  • d) Entfernen der restlichen Ätzmaske (4),
  • e) ganzflächige Abscheidung einer Siliziumnitridschicht (6),
  • f) anodische Oxidation der Siliziumnitridschicht (6) in den Be­ reichen (7), wo die Schicht die Böden der Kontaktlöcher be­ deckt,
  • g) Entfernen der oxidierten Siliziumnitridbereiche (7) und
  • h) Aufbringen der nächsten Metallisierungsebene.
3. A method for producing a multilayer wiring according to at least one of claims 1 or 2, characterized by the following method steps:
  • a) applying and annealing a polyimide layer ( 3 ),
  • b) carrying out a photoresist technique ( 4 ) to define the plated-through holes,
  • c) anisotropic etching of the contact holes or vias in the polyimide layer ( 3 ) with the photoresist structure ( 4 ) as an etching mask,
  • d) removing the remaining etching mask ( 4 ),
  • e) full-surface deposition of a silicon nitride layer ( 6 ),
  • f) anodic oxidation of the silicon nitride layer ( 6 ) in the areas ( 7 ) where the layer covers the bottoms of the contact holes,
  • g) removing the oxidized silicon nitride regions ( 7 ) and
  • h) applying the next metallization level.
4. Verfahren nach Anspruch 3, dadurch gekenn­ zeichnet, daß das Ätzen der Durchkontaktierungen mit einer reaktiven Ionenstrahltechnik (RIBE) erfolgt.4. The method according to claim 3, characterized records that the through-etching with reactive ion beam technology (RIBE). 5. Verfahren nach mindestens einem der Ansprüche 3 und 4, dadurch gekennzeichnet, daß die Sili­ ziumnitridschicht (6) in Verfahrensschritt e) in einem Plasma unterstützten CVD-Verfahren (PECVD-Siliziumnitrid) abgeschieden wird.5. The method according to at least one of claims 3 and 4, characterized in that the silicon nitride layer ( 6 ) in process step e) is deposited in a plasma-assisted CVD process (PECVD silicon nitride). 6. Verfahren nach mindestens einem der Ansprüche 3 bis 5, dadurch gekennzeichnet, daß die anodi­ sche Oxidation nach Verfahrensschritt f) in einer wäßrigen Elektrolytlösung vorgenommen wird, wobei das Substrat als Anode geschaltet wird.6. The method according to at least one of claims 3 to 5, characterized in that the anodi cal oxidation after process step f) in an aqueous Electrolyte solution is made, the substrate as an anode is switched. 7. Verfahren nach mindestens einem der Ansprüche 3 bis 6, dadurch gekennzeichnet, daß bei Ver­ fahrensschritt g) die oxidierten Bereiche (7) der Siliziumni­ tridschicht (6) durch eine Naßätzung entfernt werden.7. The method according to at least one of claims 3 to 6, characterized in that in process step G), the oxidized areas ( 7 ) of the silicon nitride layer ( 6 ) are removed by wet etching. 8. Verfahren nach mindestens einem der Ansprüche 3 bis 7, dadurch gekennzeichnet, daß zur Metal­ lisierung mit Silizium und Titan legiertes Aluminium verwendet wird.8. The method according to at least one of claims 3 to 7, characterized in that for metal Aluminum alloyed with silicon and titanium is used becomes. 9. Verfahren nach mindestens einem der Ansprüche 3 bis 8, dadurch gekennzeichnet, daß das Schicht­ dickenverhältnis von Polyimid (3) zu Siliziumnitrid (6) auf einen Wert zwischen 2 und 7 eingestellt wird.9. The method according to at least one of claims 3 to 8, characterized in that the layer thickness ratio of polyimide ( 3 ) to silicon nitride ( 6 ) is set to a value between 2 and 7. 10. Verfahren nach mindestens einem der Ansprüche 3 bis 9, dadurch gekennzeichnet, daß vor dem Ver­ fahrensschritt a) zunächst eine erste Siliziumnitridschicht (8) über einer ersten Metallisierungsebene (2) abgeschieden wird und erst danach die Verfahrensschritte a) bis h) durchgeführt werden.10. The method according to at least one of claims 3 to 9, characterized in that before the process step a) first a first silicon nitride layer ( 8 ) is deposited over a first metallization level ( 2 ) and only then process steps a) to h) are carried out .
DE19873728348 1987-08-25 1987-08-25 Multilayer wiring for VLSI semiconductor components Withdrawn DE3728348A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19873728348 DE3728348A1 (en) 1987-08-25 1987-08-25 Multilayer wiring for VLSI semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19873728348 DE3728348A1 (en) 1987-08-25 1987-08-25 Multilayer wiring for VLSI semiconductor components

Publications (1)

Publication Number Publication Date
DE3728348A1 true DE3728348A1 (en) 1989-03-09

Family

ID=6334452

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873728348 Withdrawn DE3728348A1 (en) 1987-08-25 1987-08-25 Multilayer wiring for VLSI semiconductor components

Country Status (1)

Country Link
DE (1) DE3728348A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0632497A2 (en) * 1993-07-02 1995-01-04 Plessey Semiconductors Limited Multichip module substrate structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2541624C2 (en) * 1975-09-18 1982-09-16 Ibm Deutschland Gmbh, 7000 Stuttgart Aqueous etching solution and method for etching polymer films or foils based on polyimide
DE3237026A1 (en) * 1981-10-13 1983-04-21 Monolithic Memories, Inc., 94086 Sunnyvale, Calif. SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF - PRODUCTION OF PLANAR TRANSISTORS USING POLYIMIDE FOR DIELECTRIC INSULATION -
DE2441170C2 (en) * 1973-09-07 1984-07-12 N.V. Philips' Gloeilampenfabrieken, Eindhoven Method for manufacturing a semiconductor device
EP0177845A1 (en) * 1984-09-28 1986-04-16 Siemens Aktiengesellschaft Integrated circuit with multilayer wiring and method for manufacturing it

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2441170C2 (en) * 1973-09-07 1984-07-12 N.V. Philips' Gloeilampenfabrieken, Eindhoven Method for manufacturing a semiconductor device
DE2541624C2 (en) * 1975-09-18 1982-09-16 Ibm Deutschland Gmbh, 7000 Stuttgart Aqueous etching solution and method for etching polymer films or foils based on polyimide
DE3237026A1 (en) * 1981-10-13 1983-04-21 Monolithic Memories, Inc., 94086 Sunnyvale, Calif. SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF - PRODUCTION OF PLANAR TRANSISTORS USING POLYIMIDE FOR DIELECTRIC INSULATION -
EP0177845A1 (en) * 1984-09-28 1986-04-16 Siemens Aktiengesellschaft Integrated circuit with multilayer wiring and method for manufacturing it

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DE-Z: Siemens Forsch.-u. Entwickl.-Ber., Bd.15, 1986, Nr.2, S64-67 *
US-Z:IBM Technical Disclosure Bulletin, Bd.25, Nr.1, Juni 1987, S.303 *
US-Z:IBM Technical Disclosure Bulletin, Bd.25, Nr.4, Sept. 1982, S.1892-1894 *
US-Z:IBM Technical Disclosure Bulletin, Bd.27, Nr.2, Juli 1984, S.1041-1043 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0632497A2 (en) * 1993-07-02 1995-01-04 Plessey Semiconductors Limited Multichip module substrate structure
EP0632497A3 (en) * 1993-07-02 1995-12-06 Plessey Semiconductors Ltd Multichip module substrate structure.

Similar Documents

Publication Publication Date Title
DE3877412T2 (en) PACKAGE CONTAINING MULTIPLE SEMICONDUCTOR BLOCKS FOR HIGH DEMANDS, MULTILAYER CONNECTING SYSTEM.
DE102016100766B4 (en) STRUCTURING OF CONTACT THROUGH MULTI-PHOTOLITHOGRAPHY AND MULTILATERALITY
DE69531244T2 (en) SIMPLIFIED DOUBLE DAMASCEN PROCESS FOR THE PRODUCTION OF A MULTIPLE LAYER METALIZATION AND A CONNECTING STRUCTURE
DE10218155B4 (en) Semiconductor device and method for manufacturing the same
DE69111890T2 (en) Method of manufacturing a multilayer printed circuit board.
DE69114759T2 (en) Method of making multilayer coplanar conductor / insulator layers using photosensitive polyimides.
DE69133409T2 (en) Process for the production of multilayer structures
DE1930669C2 (en) Method for manufacturing an integrated semiconductor circuit
DE10256346A1 (en) Semiconductor device e.g. digital to analog converter has connection contact plug with copper layer filled in connection contact plug, which is provided on intermediate electrode so as to connect lower and upper electrodes
DE19834917A1 (en) Forming self-aligned vias in a semiconductor device
DE69015564T2 (en) FULLY EFFECTED CONNECTING STRUCTURE WITH TITANIUM / TUNGSTEN AND SELECTIVE CVD TUNGSTEN.
DE19626038C2 (en) Method for producing the connection structure of a semiconductor device
DE69114346T2 (en) Process for making multilayer coplanar line / insulator layers using photosensitive polyimide.
DE102005057076A1 (en) Increasing adhesion of metal layers comprises determination of regions of reduced contact hole density and formation of position-holding contacts with metal
DE2709986A1 (en) METHOD OF PRODUCING COPLANAR LAYERS FROM THIN FILMS
DE68920291T2 (en) Process for making conductive sheets and supports.
DE19626039C2 (en) Method of making a metal line
DE3414781A1 (en) Multi-layer connection structure of a semi-conductor device
DE2709933A1 (en) PROCESS FOR PRODUCING CONTINUOUS METALLIC JOINTS BETWEEN MULTIPLE METALLIZATION LEVELS IN SEMICONDUCTOR DEVICES
EP0698293B1 (en) Method of manufacturing a semiconductor component with supply terminals for high integration density
DE19531602C2 (en) Connection structure of a semiconductor device and its manufacturing method
DE60037599T2 (en) MANUFACTURING METHOD FOR SEMICONDUCTOR ARRANGEMENT WITH REDUCED SIGNAL WAY DELAY TIME
DE2230171A1 (en) METHOD FOR PRODUCING STRIP LADDERS FOR SEMICONDUCTOR COMPONENTS
DE3634168C2 (en)
EP0013728B1 (en) Method for forming electrical connections between conducting layers in semiconductor structures

Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8139 Disposal/non-payment of the annual fee