GB2097631A

GB2097631A - Time division telephone switching systems

Info

Publication number: GB2097631A
Application number: GB8131442A
Authority: GB
Original assignee: Nippon Telegraph and Telephone Corp
Current assignee: Nippon Telegraph and Telephone Corp
Priority date: 1978-02-01
Filing date: 1979-01-15
Publication date: 1982-11-03
Also published as: JPS5758117B2; FR2498037B1; GB2097631B; FR2498037A1; JPS54103611A

Abstract

A plurality of speech path units are controlled by a central processing unit. Each speech path unit includes a time switch which shifts a signal which is time-division-multiplexed from time slots of incoming highways to other time slots on outgoing highways, a digital trunk circuit and speech path control equipment. The time switch includes a speech path memory device divided into m<2> memory blocks (m > 2). The memory blocks have assigned thereto the column and row numbers of an mxm matrix. An incoming highway is accessed to a memory block address of a column of the matrix corresponding to that incoming highway, and similarly with the outgoing highways whereby to treat a plurality of said time slots as a group. This increases the time switch capacity without redundant use of the memory.

Description

SPECIFICATION Time division telephone switching systems This application is divided out from parent application No. 7901369 (publication No. 2 014 018 A), the disclosure of which is incorporated herein by reference.

According to the present invention there is provided a time division telephone switching system in which time division multiplexed signals are exchanged, said system comprising a time switch which includes a speech path memory device for temporarily storing speech information at the time of switching, said memory device being divided into m2 memory blocks, where m is an integer larger than 2; said divided memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, means for accessing an incoming highway to a predetermined address of a memory block belonging to a column of said matrix corresponding to said incoming highway, and means for accessing an outgoing highway to a predetermined address of a memory block belonging to a row of said matrix corresponding to said outgoing highway whereby to treat a plurality of said time slots as a group.

In another aspect this invention provides a time division telephone switching system in which time division multiplexed signals are exchanged, said system comprising a time switch including a speech path memory device adapted to temporarily store speech information at the time of switching operation, said memory device being divided into m2 memory blocks (where m is an integer largerthan 2) adapted to control write and read out addresses, said memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, means for accessing an incoming highway to a predetermined address of a memory block belonging to a column of said matrix corresponding to said incoming highway, means for accessing an outgoing highway to a predetermined address of a memory block belonging to a row of said matrix corresponding to said outgoing highway whereby to treat a plurality of said time slots as a group, a holding memory device for commonly controlling a memory block of said speech path memory device for controlling a write address and a memory block for controlling a read out address, means for supplying a write address to a memory block belonging to a column of said matrix corresponding to the number of said address controlling memory device, and means for supplying a read out address to a memory block belonging to a row of said matrix corresponding to the number of said address controlling memory device, thereby causing an access time of said speech path memory device which is allocated to read out operation to precede an access time allocated to write operation, said access times occuring at least twice per one time slot.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram useful in explaining the invention; Figure2 is a block diagram of a time division telephone switching system according to the invention; Figure 3 is a connection diagram useful in explaining the operation of the system of Figure 2; and Figure 4 is a block diagram showing a modification of the system of Figure 2 incorporated.

Referring to Figure 1 there is shown a schematic further modification of the time division telephone switching network of Figure 19 of the parent patent application No. 7901369. In Figure 1, a time division telephone switching system has an input highway side 91 and an output highway side 102. Speech path memory devices M are randomly accessed by holding memory devices HM 15011, 15012, 151ii, and 15112 in respect of the input and outgoing sides of each highway. The memory devices M comprise speech path memory devices M11, M12, M21, M22, etc., in common for the primary and secondary time switching.

Figure 2 is a block diagram showing more detail of the Figure 1 system. In Figure 2, each one of m incoming highways 917 - 91run is multiplexed by n. In the same manner each of one m outgoing highways 1021 -1 02m is also multiplexed by n. Each of m2 memory devices 16011 - 160rnrn (M11 - Mmm) has a capacity of n/m words (this capacity can be increased or decresed depending upon the quantity of the traffic flow and the internal blocking probability).

Each one of the holding memory devices 1501 - 150, functions as a control memory device which designates the memory number and its address when time division multiplexed signals arrive over respec tive highways 911 - 91m. Each of the holding memory devices 1511 - 151 m acts as a control memory device which designates the number of a read out memory device and the address thereof when a signal is read out from a memory device for the purpose of sending the signal to respective highways 1021 102run.

Each holding memory device has a storage capacity of n words each having log2 m + log2 2/m, where log2 m bits designate the number of the memory device while log2 n/m bits designate the address number in the memory device. Generally stated, the holding memory device 15 1 controls speech memory devices 16011 - 1601run whereas the holding memory device 1511 controls speech memory devices 16011 - 1601m.

This method of control will now be described with reference to Figure 3. Let us assume now that a line having a time slot number a of the incoming highway 911 is to be connected to a line having a time slot number p of the outgoing highway 102m.

The speech path memory device that can be used for establishing this connection is a memory device 1601m and an idle address thereof can be selected by the central processing unit (not shown). Suppose now that an idle address "a" of the memory device 1601m has been designated. Then mis written in the log2 m bits of the address a of the holding memory device 1501 and a is written in the log2 n/m bits so that, at the time slot 13 of the outgoing highway 102m, signal A stored in the address "a" of the speech path memory device 1 601m would be read out. In this manner, the time slot a of the incoming highway 911 and the time slot 8 of the outgoing highway 102m are connected together.The connection in the opposite direction (the connection between the time slot p of the highway 91 m and the time slot a of the highway 1027) is established in the same manner by using the speech path memory device 1 60ml. At this time, the operating period of the speech path memory device may be n times per frame for writing and reading respectively, so that the total number of the channels that can be exchanged is n x m.

Figure 4 shows a pair control system incorporated into the system shown in Figures 2 and 3. In this case, the holding memory devices 1701 - 170run control commonly incoming highway and outgoing highway using the write addresses and the read out addresses of the informations to respective highways. To mutually connect the same highways the speech path memory device is read out during the fore half of one time slot and the data is written into the speech path memory device during the later half.

Since the time division exchange operation is similar to that of the system shown in Figure 3, its description is believed unnecessary.

According to the above described embodiments, the speech path memory device in a time switch is divided into a plurality of blocks which are arranged in a matrix so as to enable the incoming highway to access the memory blocks belonging to the same column and the outgoing highway to access the memory blocks of the same row number. As a consequence, it is possible to increase the capacity of the time switch without redundantly using the memory device and without increasing the operating speed thereof. Thus, according to this invention it becomes possible to fabricate a time division switching network by using large capacity time switch which is constituted by an inexpensive memory device which is suitable to be fabricated as an integrated circuit. Thus, it is possible to readily increase the capacity of a time division switching network.When it is desired to increase further the capacity of the network, the capacity can be increased by combining time switches or space switches in many stages. The time division speech path unit structure described above may be replaced by other suitable structures known to those in the art.

CLAIMS 1. A time division telephone switching system in which time division multiplexed signals are exchanged, said system comprising a time switch which includes a speech path memory device for temporarily storing speech information at the time of switching, said memory device being divided into m2 memory blocks, where m is an integer larger than 2; said divided memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, means for accessing an incoming highway to a predetermined address of a memory block belonging to a column of said matrix corresponding to said incoming highway, and means for accessing and outgoing highway to a predetermined address of a memory block belonging to a row of said matrix corresponding to said outgoing highway whereby to treat a plurality of said time slots as a group.

2. A time division telephone switching system according to claim 1 wherein the number of the words of each memory block is varied by n/m depending upon such conditions as the efficiency of utilization of a highway and the internal blocking probability of said telephone switching system, where n represents the multiplicity of said highway and m the number of the column or row of said matrix.

3. Atime division telephone switching system in which time division multiplexed signals are exchanged, said system comprising a time switch including a speech path memory device adapted to temporarily store speech information at the time of switching operation, said memory device being divided into m2 memory blocks (where m is an integer larger than 2) adapted to control write and read out addreses, said memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, means for accessing an incoming highway to a predetermined address of a memory block belonging to a column of said matrix corresponding to said incoming highway, means for accessing an outgoing highway to a predetermined address of a memory block belonging to a row of said matrix corresponding to said outgoing highway whereby to treat a plurality of said time slots as a group, a holding memory device for commonly controlling a memory block of said speech path memory device for controlling a write address and a memory block for controlling a read out address, means for supplying a write address to a memory block belonging to a column of said matrix corresponding to the number of said address controlling memory device, and means for supplying a read out address to a memory block belonging to a row of said matrix corresponding to the number of said address controlling memory device, thereby causing an access time of said speech path memory device which is allocated to read out operation to precede an access time allocated to write operation, said access times occurring at least twice per one time slot.

4. A time division telephone switching system according to claim 3 wherein the number of the words of each memory block is varied by n/m depending upon such conditions as the efficient of utilization of the highway and the internal blocking probability of the highway, wherein n represents the multiplicity of the highway and m the number of columns or rows of a matrix of said memory blocks.

5. A time division telephone switching system according to any one of claims 1 to 4 including a plurality of speech path units for controlled interconnection; a central processing unit for effecting overall control of said speech path units; each one of said speech path units including a time division speech channel unit for exchanging signals between predetermined time slots, a digital trunk circuit means for processing a channel associated signal containing a register signal and a line operating state signal, and speech path control equipment receiving and distributing control signals, which includes an interface between said time division speech channel unit and said digital trunk circuit means; and wherein said time division speech channel unit includes said time switch.

6. A time division telephone switching system substantially as described herein with reference to Figures 1 to 4 of the accompanying drawings.

New claims or amendments to claims filed on 22 June1982 Superseded claims 1 to 6 New or amended claims:

Claims

1. A time division telephone switching system in which time division multiplexed signals on incoming highway time slots are switched to outgoing highway time slots, said system comprising a time switch which includes speech path memory means for temporarily storing speech information at the time of switching, said memory means comprising m2 speech path memory blocks, where m is an integer largerthan 2; said memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, a holding memory device associated with each of m incoming highways to control the m memory blocks in a column of said matrix, the m columns having column numbers corresponding respectively with said m incoming highways, another holding memory device associated with each of the m outgoing highways to control the m memory blocks in a row of said matrix, the m rows having row numbers corresponding respectively with said m outgoing highways, each said holding memory device being adapted to store words composed of first bits designating the number of the memory block in its column or row, as appropriate to an incoming or outgoing highway, and second bits designating the position in the designating memory block containing the temporarily stored speech information.

2. A time division telephone switching system in which time division multiplexed signals on incoming highway time slots are switched to outgoing highway time slots, said system comprising a time switch including a speech path memory device adapted to temporarily store speech information at the time of switching operation, said memory device being divided into m2 memory blocks (where m is an integer larger than 2) adapted to be controlled by write and read out addresses, said memory blocks having assigned thereto column and row numbers of a matrix having m columns and m rows, a holding memory device common to each pair of m incoming and m outgoing highways to control the m memory blocks in a column of said matrix and the m memory blocks in a row of said matrix, the m columns having column numbers corresponding respectively with said m incoming highways, and them rows having row numbers corresponding respectively with said m outgoing highways, each said holding memory device being adapted to store words each composed of first bits designating the number of the memory block in its column or row, as appropriate to an incoming or outgoing highway, and second bits designating the position in the designated memory blocks containing the temporarily stored speech information, wherein an access time of each said speech path memory device which is allocated to a read-out operation to an outgoing highway precedes an access time allocated to a write operation from an incoming highway, said access times occurring at least twice in each time slot.

3. Atime division telephone switching system substantially as described herein with reference to Figures 2 and 3, or Figure 4, of the accompanying drawings.